[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_0_eng / packages / ti / board / diag / icss_emac / src / icss_emac_startup.c
1 /**
2 * \file icss_emacStartup.c
3 *
4 * \brief Interrupt vector is copied to the internal Ram. After that the
5 * control is given to the application.
6 *
7 * \copyright Copyright (C) 2013 Texas Instruments Incorporated -
8 * http://www.ti.com/
9 */
11 /**
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the
22 * distribution.
23 *
24 * Neither the name of Texas Instruments Incorporated nor the names of
25 * its contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
46 #include <ti/csl/tistdtypes.h>
47 #include <ti/csl/csl_a15Aux.h>
48 #include <ti/csl/csl_armGicAux.h>
49 #include "icss_emac_startup.h"
51 /* ========================================================================== */
52 /* Internal Function Declarations */
53 /* ========================================================================== */
55 #define MMU_PAGETABLE_ALIGN_SIZE (16U * 1024U)
57 void CopyVectorTable(void);
59 void systemInit(void);
61 /* ========================================================================== */
62 /* Global Variables */
63 /* ========================================================================== */
65 /** \brief Vector table */
66 static Uint32 const vecTbl[14]=
67 {
68 0xE59FF018, /* Opcode for loading PC with the contents of [PC + 0x18] */
69 0xE59FF018, /* Opcode for loading PC with the contents of [PC + 0x18] */
70 0xE59FF018, /* Opcode for loading PC with the contents of [PC + 0x18] */
71 0xE59FF018, /* Opcode for loading PC with the contents of [PC + 0x18] */
72 0xE59FF014, /* Opcode for loading PC with the contents of [PC + 0x14] */
73 0xE24FF008, /* Opcode for loading PC with (PC - 8) (eq. to while(1)) */
74 0xE59FF010, /* Opcode for loading PC with the contents of [PC + 0x10] */
75 0xE59FF010, /* Opcode for loading PC with the contents of [PC + 0x10] */
76 (Uint32)Entry,
77 (Uint32)UndefInstHandler,
78 (Uint32)SVC_Handler,
79 (Uint32)AbortHandler,
80 (Uint32)IRQHandler,
81 (Uint32)FIQHandler
82 };
84 CSL_ArmGicDistIntrf distrIntrf;
85 CSL_ArmGicCpuIntrf gCpuIntrf;
87 /** \brief Page table configuration.*/
88 #if 0 /* Enable to use short descriptor */
89 #elif 0 /* Enable to use short descriptor */
91 /** \brief Page tables to hold physical to virtual address mapping. The start
92 address of the page table must be aligned at 16K boundary */
93 #pragma DATA_ALIGN(mmuobj, MMU_PAGETABLE_ALIGN_SIZE);
94 CSL_A15MmuShortDescObj mmuobj;
95 CSL_A15MmuShortDescObj mmuobj
96 __attribute__((aligned(MMU_PAGETABLE_ALIGN_SIZE)));
98 CSL_A15MmuShortDescAttr mmuAttr0;
99 CSL_A15MmuShortDescAttr mmuAttr1;
100 CSL_A15MmuShortDescAttr mmuAttr2;
101 CSL_A15MmuShortDescAttr mmuAttr3;
102 #else
104 /** \brief Page tables to hold physical to virtual address mapping. The start
105 address of the page table must be aligned at 16K boundary */
106 CSL_A15MmuLongDescObj mmuObj
107 __attribute__((aligned(MMU_PAGETABLE_ALIGN_SIZE)));
109 CSL_A15MmuLongDescAttr mmuAttr0;
110 CSL_A15MmuLongDescAttr mmuAttr1;
111 CSL_A15MmuLongDescAttr mmuAttr2;
112 #endif
114 /* ========================================================================== */
115 /* Function Definitions */
116 /* ========================================================================== */
118 /**
119 * \brief This function copies the vector table to a location in OCMC
120 * RAM and sets the vector base address register.
121 *
122 * \param None.
123 * \retval None.
124 *
125 * Note: The default vector table base is in OCMC RAM, but can be moved to
126 * other locations, to make some more space in OCMC RAM for relocating any
127 * other code, if desired. The vector table can be placed anywhere in the
128 * memory map. If the entire code is intended to be run from DDR, it can be
129 * placed in DDR also. In this case, only vector base address register need
130 * to be set with the base address of the vector table.
131 */
132 void CopyVectorTable(void)
133 {
134 Uint32 vectorBase = 0x40300000U;
135 Uint32 ocmcRamSize = 512U * 1024U;
137 vectorBase = vectorBase + ocmcRamSize - 0x400U;
139 Uint32 *dest = (Uint32 *)vectorBase;
140 Uint32 *src = (Uint32 *)vecTbl;
141 Uint32 count;
143 CSL_a15SetVectorTable(vectorBase);
145 for(count = 0; count < sizeof(vecTbl)/sizeof(vecTbl[0]); count++)
146 {
147 dest[count] = src[count];
148 }
149 }
151 void INTCCommonIntrHandler(void)
152 {
153 CSL_armGicCommonIntrHandler(&gCpuIntrf);
154 }
156 void systemInit(void)
157 {
158 uint32_t phyAddr = 0U;
160 #if 0 /* Enable to use short descriptor */
161 #elif 0 /* Enable to use short descriptor */
162 mmuobj.numFirstLvlEntires = CSL_A15_MMU_SHORT_DESC_LVL1_ENTIRES;
163 CSL_a15InitMmuShortDesc(&mmuobj);
165 CSL_a15InitMmuShortDescAttrs(&mmuAttr0);
166 CSL_a15InitMmuShortDescAttrs(&mmuAttr1);
167 CSL_a15InitMmuShortDescAttrs(&mmuAttr2);
168 CSL_a15InitMmuShortDescAttrs(&mmuAttr3);
170 mmuAttr0.type = CSL_A15_MMU_SHORT_DESC_TYPE_SECTION;
171 mmuAttr0.accPerm = 0U;
173 for (phyAddr = 0x00000000U; phyAddr < 0x80000000U; phyAddr += 0x00100000)
174 {
175 CSL_a15SetMmuFirstLevelShortDesc(&mmuobj, (void *)phyAddr, (void *)phyAddr, &mmuAttr0);
176 }
178 mmuAttr1.type = CSL_A15_MMU_SHORT_DESC_TYPE_SECTION;
179 mmuAttr1.bufferable = 1U;
180 mmuAttr1.accPerm = 3U;
181 mmuAttr1.tex = 5U;
182 mmuAttr1.nonSecure = 1U;
184 for (phyAddr = 0x80000000U; phyAddr < 0xA0000000U; phyAddr += 0x00100000)
185 {
186 CSL_a15SetMmuFirstLevelShortDesc(&mmuobj, (void *)phyAddr, (void *)phyAddr, &mmuAttr1);
187 }
189 mmuAttr2.type = CSL_A15_MMU_SHORT_DESC_TYPE_SECTION;
190 mmuAttr2.accPerm = 0U;
192 for (phyAddr = 0xA0000000U; phyAddr < 0xC0000000U; phyAddr += 0x00100000)
193 {
194 CSL_a15SetMmuFirstLevelShortDesc(&mmuobj, (void *)phyAddr, (void *)phyAddr, &mmuAttr2);
195 }
197 mmuAttr3.type = CSL_A15_MMU_SHORT_DESC_TYPE_SECTION;
198 mmuAttr3.accPerm = 0U;
200 for (phyAddr = 0xC0000000U; phyAddr < 0xE0000000U; phyAddr += 0x00100000)
201 {
202 CSL_a15SetMmuFirstLevelShortDesc(&mmuobj, (void *)phyAddr, (void *)phyAddr, &mmuAttr3);
203 }
205 CSL_a15EnableMmu();
206 CSL_a15EnableCache();
207 //#else
208 mmuObj.numFirstLvlEntires = CSL_A15_MMU_LONG_DESC_LVL1_ENTIRES;
209 mmuObj.numSecondLvlEntires = CSL_A15_MMU_LONG_DESC_LVL2_ENTIRES;
210 mmuObj.mairEntires = CSL_A15_MMU_MAIR_LEN_BYTES;
211 mmuObj.mairAttr[0] = 0x44U;
212 mmuObj.mairAttr[1] = 0x0U;
213 mmuObj.mairAttr[2] = 0xFFU;
214 CSL_a15InitMmuLongDesc(&mmuObj);
216 CSL_a15InitMmuLongDescAttrs(&mmuAttr0);
217 CSL_a15InitMmuLongDescAttrs(&mmuAttr1);
218 CSL_a15InitMmuLongDescAttrs(&mmuAttr2);
220 mmuObj.mairAttr[0] = 0x44U;
221 mmuObj.mairAttr[1] = 0x0U;
222 mmuObj.mairAttr[2] = 0xFFU;
223 CSL_a15SetMmuMair(0, mmuObj.mairAttr[0]);
224 CSL_a15SetMmuMair(1, mmuObj.mairAttr[1]);
225 CSL_a15SetMmuMair(2, mmuObj.mairAttr[2]);
227 mmuAttr0.type = CSL_A15_MMU_LONG_DESC_TYPE_BLOCK;
228 mmuAttr0.accPerm = 0U;
229 mmuAttr1.shareable = 2U;
230 mmuAttr0.attrIndx = 1U;
232 for (phyAddr = 0x00000000U; phyAddr < 0x60000000U; phyAddr += 0x00200000U)
233 {
234 CSL_a15SetMmuSecondLevelLongDesc(&mmuObj, (void *)phyAddr, (void *)phyAddr, &mmuAttr0);
235 }
237 mmuAttr1.type = CSL_A15_MMU_LONG_DESC_TYPE_BLOCK;
238 mmuAttr1.accPerm = 0U;
239 mmuAttr1.shareable = 2U;
240 mmuAttr1.attrIndx = 2U;
242 for (phyAddr = 0x80000000; phyAddr < 0xA0000000; phyAddr += 0x00200000U)
243 {
244 CSL_a15SetMmuSecondLevelLongDesc(&mmuObj, (void *)phyAddr, (void *)phyAddr, &mmuAttr1);
245 }
247 mmuAttr2.type = CSL_A15_MMU_LONG_DESC_TYPE_BLOCK;
248 mmuAttr2.accPerm = 0U;
249 mmuAttr2.attrIndx = 0U;
251 for (mmuAttr2.phyAddr[0U] = 0xA0000000; mmuAttr2.phyAddr[0U] < 0xB0000000;
252 mmuAttr2.phyAddr[0U] += 0x00200000U)
253 {
254 CSL_a15SetMmuSecondLevelLongDesc(&mmuObj, (void *)phyAddr, (void *)phyAddr, &mmuAttr2);
255 }
257 CSL_a15EnableMmu();
258 CSL_a15EnableCache();
259 #endif
261 gCpuIntrf.gicDist = &distrIntrf;
262 gCpuIntrf.cpuIntfBasePtr = (void *)0x48212000U;
263 distrIntrf.distBasePtr = (void *)0x48211000U;
264 gCpuIntrf.initStatus = FALSE;
265 gCpuIntrf.gicDist->initStatus = FALSE;
266 gCpuIntrf.pDefaultIntrHandlers = NULL;
267 gCpuIntrf.pDefaultUserParameter = NULL;
269 CSL_armGicInit(&gCpuIntrf);
270 }