[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_0_eng / packages / ti / boot / sbl / example / mpuMulticoreApp / lnk_mpu.cmd
1 /**
2 * \file am5xx_ddr.lds
3 *
4 * \brief This file is the linker script for am5x required for building
5 * applications with the gcc toolchain.
6 *
7 * \copyright Copyright (C) 2013 Texas Instruments Incorporated -
8 * http://www.ti.com/
9 */
11 /**
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the
22 * distribution.
23 *
24 * Neither the name of Texas Instruments Incorporated nor the names of
25 * its contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
42 MEMORY
43 {
44 DDR0 : o = 0x80000400, l = 0x00A0000 /* DDR memory region for loading A15 MPU multicore Application */
45 OCMC_RAM1 (RWIX): org = 0x40300000 , len = 0x0002FFFF /* OCMC_RAM1 Region mapped for IO delay relocation */
46 OCMC_RAM2 (RWIX): org = 0x40400000 , len = 0x00100000 /* OCMC RAM */
47 OCMC_RAM3 (RWIX): org = 0x40500000 , len = 0x00100000 /* OCMC RAM */
48 }
50 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
51 OUTPUT_ARCH(arm)
53 SECTIONS
54 {
55 .startcode :
56 {
57 . = ALIGN(4);
58 *(.public.*)
59 *sbl_init.ao (.text)
60 } >DDR0
62 .text :
63 {
64 . = ALIGN(4);
65 *(.text*)
66 *(.rodata*)
67 } >DDR0
69 .data :
70 {
71 . = ALIGN(4);
72 *(.data*)
73 } >DDR0
75 .bss :
76 {
77 . = ALIGN(4);
78 _bss_start = .;
79 *(.bss*)
80 *(COMMON)
81 _bss_end = .;
82 } >DDR0
84 .heap :
85 {
86 . = ALIGN(4);
87 __end__ = .;
88 end = __end__;
89 __HeapBase = __end__;
90 *(.heap*)
91 . = . + 0x10000;
92 __HeapLimit = .;
93 } >DDR0
95 .stack :
96 {
97 . = ALIGN(4);
98 __StackLimit = . ;
99 *(.stack*)
100 . = . + 0x10000;
101 __StackTop = .;
102 } >DDR0
103 _stack = __StackTop;
105 BOARD_IO_DELAY_CODE :
106 {
107 . = ALIGN(4);
108 *(BOARD_IO_DELAY_CODE*)
109 } > OCMC_RAM1
111 BOARD_IO_DELAY_DATA :
112 {
113 . = ALIGN(4);
114 *(BOARD_IO_DELAY_DATA*)
115 } > OCMC_RAM1
116 }