[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_0_eng / packages / ti / csl / arch / a15 / src / mpu_wugen.c
1 /* =============================================================================
2 * Copyright (c) Texas Instruments Incorporated 2015-2016
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 * \file mpu_wugen.c
36 *
37 * \brief MPU WUGEN related APIs.
38 *
39 * This file contains the APIs for configuring MPU_WUGEN
40 * for ARM Cortex-A15 on AM57x and TDA2xx SOC's.
41 *
42 */
44 /* ========================================================================== */
45 /* Include Files */
46 /* ========================================================================== */
48 #include <stdint.h>
49 #include <ti/csl/hw_types.h>
50 #include <ti/csl/soc.h>
51 #include <ti/csl/arch/csl_arch.h>
53 /* ========================================================================== */
54 /* Macros & Typedefs */
55 /* ========================================================================== */
57 #define REG_IDX_SHIFT (0x05U)
58 /** \brief Register Index */
60 #define REG_BIT_MASK (0x1FU)
61 /** \brief Register Bit Mask */
63 #define NUM_BYTES_REG (uint32_t) (0x4U)
64 /** \brief Address offset per register */
66 /* ========================================================================== */
67 /* Structures and Enums */
68 /* ========================================================================== */
70 /* None */
72 /* ========================================================================== */
73 /* Internal Function Declarations */
74 /* ========================================================================== */
76 /* None */
78 /* ========================================================================== */
79 /* Global Variables */
80 /* ========================================================================== */
82 /* None */
84 /* ========================================================================== */
85 /* Function Declarations */
86 /* ========================================================================== */
88 void MPU_WUGEN_0_DisableAll(void); /* for misra warnings */
89 void MPU_WUGEN_1_DisableAll(void); /* for misra warnings */
90 void MPU_WUGEN_Init(void); /* for misra warnings */
91 void MPU_WUGEN_Init(void)
92 {
93 MPU_WUGEN_0_DisableAll();
94 #if defined (SOC_TDA2EX) || defined (SOC_AM571x)
95 /* Disable not required */
96 #else
97 MPU_WUGEN_1_DisableAll();
98 #endif
99 }
101 void MPU_WUGEN_0_DisableAll(void)
102 {
103 HW_WR_REG32(SOC_MPU_WUGEN_BASE + MPU_WKG_ENB_A_0, 0);
104 HW_WR_REG32(SOC_MPU_WUGEN_BASE + MPU_WKG_ENB_B_0, 0);
105 HW_WR_REG32(SOC_MPU_WUGEN_BASE + MPU_WKG_ENB_C_0, 0);
106 HW_WR_REG32(SOC_MPU_WUGEN_BASE + MPU_WKG_ENB_D_0, 0);
107 HW_WR_REG32(SOC_MPU_WUGEN_BASE + MPU_WKG_ENB_E_0, 0);
108 }
110 void MPU_WUGEN_1_DisableAll(void)
111 {
112 HW_WR_REG32(SOC_MPU_WUGEN_BASE + MPU_WKG_ENB_A_1, 0);
113 HW_WR_REG32(SOC_MPU_WUGEN_BASE + MPU_WKG_ENB_B_1, 0);
114 HW_WR_REG32(SOC_MPU_WUGEN_BASE + MPU_WKG_ENB_C_1, 0);
115 HW_WR_REG32(SOC_MPU_WUGEN_BASE + MPU_WKG_ENB_D_1, 0);
116 HW_WR_REG32(SOC_MPU_WUGEN_BASE + MPU_WKG_ENB_E_1, 0);
117 }
119 void MPU_WUGEN_0_Interrupt_Lookup(void); /* for misra warnings */
120 void MPU_WUGEN_0_Interrupt_Lookup(void)
121 {
122 uint32_t index;
123 uint32_t regval;
125 for (index = 0U; index < 5U; index++)
126 {
127 regval = HW_RD_REG32(SOC_INTC_MPU_DISTRIBUTOR_BASE +
128 (MPU_GICD_ISER1 + (4U * index)));
129 HW_WR_REG32(SOC_MPU_WUGEN_BASE +
130 (MPU_WKG_ENB_A_0 + (4U * index)),
131 regval);
132 }
133 }
135 void MPU_WUGEN_0_Enable(uint16_t intrNum); /* for misra warnings */
136 void MPU_WUGEN_0_Enable(uint16_t intrNum)
137 {
138 uint32_t addr, index, mask, shift;
140 index = (uint32_t) intrNum >> REG_IDX_SHIFT;
141 shift = (uint32_t) intrNum & REG_BIT_MASK;
142 mask = ((uint32_t) 1) << shift;
143 addr = SOC_MPU_WUGEN_BASE + (MPU_WKG_ENB_A_0 + (NUM_BYTES_REG * index));
145 /* Enable the wakeup event for interrupt number passed */
146 HW_WR_FIELD32_RAW(addr,
147 mask,
148 shift,
149 (uint32_t) 1);
150 }
152 void MPU_WUGEN_1_Enable(uint16_t intrNum); /* for misra warnings */
153 void MPU_WUGEN_1_Enable(uint16_t intrNum)
154 {
155 uint32_t addr, index, mask, shift;
157 index = (uint32_t) intrNum >> REG_IDX_SHIFT;
158 shift = (uint32_t) intrNum & REG_BIT_MASK;
159 mask = ((uint32_t) 1) << shift;
160 addr = SOC_MPU_WUGEN_BASE + (MPU_WKG_ENB_A_1 + (NUM_BYTES_REG * index));
162 /* Enable the wakeup event for interrupt number passed */
163 HW_WR_FIELD32_RAW(addr,
164 mask,
165 shift,
166 (uint32_t) 1);
167 }
169 void MPU_WUGEN_0_Disable(uint16_t intrNum); /* for misra warnings */
170 void MPU_WUGEN_0_Disable(uint16_t intrNum)
171 {
172 uint32_t addr, index, mask, shift;
174 index = (uint32_t) intrNum >> REG_IDX_SHIFT;
175 shift = (uint32_t) intrNum & REG_BIT_MASK;
176 mask = ((uint32_t) 1) << shift;
177 addr = SOC_MPU_WUGEN_BASE + (MPU_WKG_ENB_A_0 + (NUM_BYTES_REG * index));
179 /* Enable the wakeup event for interrupt number passed */
180 HW_WR_FIELD32_RAW(addr,
181 mask,
182 shift,
183 0);
184 }
186 void MPU_WUGEN_1_Disable(uint16_t intrNum); /* for misra warnings */
187 void MPU_WUGEN_1_Disable(uint16_t intrNum)
188 {
189 uint32_t addr, index, mask, shift;
191 index = (uint32_t) intrNum >> REG_IDX_SHIFT;
192 shift = (uint32_t) intrNum & REG_BIT_MASK;
193 mask = ((uint32_t) 1) << shift;
194 addr = SOC_MPU_WUGEN_BASE + (MPU_WKG_ENB_A_1 + (NUM_BYTES_REG * index));
196 /* Enable the wakeup event for interrupt number passed */
197 HW_WR_FIELD32_RAW(addr,
198 mask,
199 shift,
200 0);
201 }