psdk_cust/pdk_k2g_1_0_1_0_eng/packages/ti/platform_org/evmk2g/platform_lib/src/evmc66x_dss.c

   1 /*
   2  * Copyright (c) 2015, Texas Instruments Incorporated
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * *  Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  * *  Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * *  Neither the name of Texas Instruments Incorporated nor the names of
  17  *    its contributors may be used to endorse or promote products derived
  18  *    from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  24  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  27  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  28  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  29  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  */
  33
  34 /**
  35  *
  36  *  \file  evmc66x_dss.c
  37  *
  38  *  \brief This file contains C66x DSS specific functions.
  39  *
  40  ******************************************************************************/
  41
  42 #include "platform_internal.h"
  43 #ifdef DISPLAY_LOGO
  44 #include "ti_logo.h"
  45 #endif
  46 #if (PLATFORM_DSS_IN)
  47
  48 volatile Uint32 *pFrameBuffer = (volatile Uint32 *)(DDR_FRAME_ADDRESS_START);
  49 volatile Uint32 count = 0;
  50 volatile Uint32 count_underflow[11];
  51 volatile Uint32 index = 0;
  52
  53 /**
  54  *  \brief    Writes 32 bit value to a register/memory
  55  *
  56  *  This function write a given 32 bit data to the passed address.
  57  *  This function is mainly used to configure the registers of DSS
  58  *
  59  *  \param    baseAddr   [IN]   Base address
  60  *  \param    writeData [IN]   write data to be written to the address.
  61  *
  62  *  \return    - NONE
  63  */
  64 static void reg_wr_32(Uint32 baseAddr,Uint32 writeData)
  65 {
  66   (*(Uint32 *) (baseAddr)) = writeData;
  67 }
  68
  69 /**
  70  *  \brief    Read 32 bit value from a register/memory
  71  *
  72  *  This function reads a 32 bit data from the given address.
  73  *  This function is mainly used to validate/read the status of the DSS
  74  *  registers.
  75  *
  76  *  \param    baseAddr   [IN]   Base address
  77  *
  78  *  \return    - read_data - 32 bit value read from the address
  79  */
  80 static Uint32 reg_rd_32(Uint32 baseAddr)
  81 {
  82   Uint32 read_data;
  83   read_data = (*(Uint32 *) (baseAddr));
  84   return read_data;
  85 }
  86
  87 /**
  88  *  \brief    Puts the given color to the frame buffer
  89  *
  90  *  This function puts the color passed as parameter to the
  91  *  frame buffer to display the given color. This function is
  92  *  used to test the LCD, frame buffer by passing any desired
  93  *  color.
  94  *
  95  *  \param    plcdCfg   [IN]   pointer to lcdCfg to get height and width
  96  *  \param    color     [IN]   color to be displayed on the Display panel
  97  *
  98  *  \return   NONE
  99  */
 100 void dssFrameBufferColor(lcdCfg_t *plcdCfg, Uint32 color)
 101 {
 102   unsigned int x,y;
 103
 104   for (y = 0; y < plcdCfg->LcdHeight; y++)
 105     for (x = 0; x < plcdCfg->LcdWidth; x++)
 106         *(pFrameBuffer + (y * plcdCfg->LcdWidth) + (x) ) = color;
 107
 108 }
 109
 110 /**
 111  *  \brief    Puts the given pic array to the frame buffer
 112  *
 113  *  This function puts the array passed as parameter to the
 114  *  frame buffer to display the given image.
 115  *
 116  *  \param    plcdCfg   [IN]   pointer to lcdCfg to get height and width
 117  *  \param    array     [IN]   array to be displayed on the Display panel
 118  *
 119  *  \return   NONE
 120  */
 121 #ifdef DISPLAY_LOGO
 122 void dssFillFrameBuffer(void)
 123 {
 124         memcpy(TI_logo_rgb32,(const void *) 0x88000000, sizeof(TI_logo_rgb32));
 125 }
 126 #endif
 127
 128 /**
 129  *  \brief    Initialize the Frame buffer
 130  *
 131  *  This function performs initialization of frame buffer, loading of color bar
 132  *  information to the frame buffer or loading a constant value to the frame
 133  *  buffer.
 134  *
 135  *  \param    mode   [IN]   mode of operation for frame buffer
 136  *  \param    height [IN]   height of the frame buffer
 137  *  \param    width  [IN]   width of the frame buffer
 138  *
 139  *  \return   NONE
 140  */
 141 void dssInitFrameBuffer(Uint32 mode, Uint32 width, Uint32 height) {
 142
 143     Uint32 i = 0;
 144     Uint32 j = 0;
 145     Uint32 count = 0;
 146     Uint32 secondCount = 0;
 147     Uint32 currentColor = RED;
 148
 149     switch (mode) {
 150         case RGB888_CONSTANT:
 151             for (j = 0; j < (height * width); j++) {
 152                 *(pFrameBuffer + j) = 0xAAAAAA;
 153             }
 154             break;
 155         case RGB888_GENERATE:
 156             for(i = 0; i < (height * width); i++){
 157                 if ((i % width) == 0) {
 158                     count = count + 1;
 159                 }
 160                 if (count == height/6) {
 161                     count = 0;
 162                     secondCount = secondCount + 1;
 163                     if (secondCount == 1){
 164                         currentColor = GREEN;
 165                     }
 166                     else if (secondCount == 2){
 167                         currentColor = BLUE;
 168                     }
 169                     else if (secondCount == 3){
 170                         currentColor = PURPLE;
 171                     }
 172                     else if (secondCount == 4){
 173                         currentColor = YELLOW;
 174                     }
 175                     else if (secondCount == 5){
 176                         currentColor = PINK;
 177                     }
 178                 }
 179                 *(pFrameBuffer + i) = currentColor;
 180             }
 181
 182             break;
 183         case RGB888_ADDRESS:
 184             for (j = 0; j < (height * width); j++) {
 185                 *(pFrameBuffer + j) = (0x88000000+(j*4));
 186             }
 187             break;
 188         default:
 189             break;
 190     }
 191 }
 192
 193 /**
 194  *  \brief    Configures DISPC_GLOBAL_MFLAG_ATTRIBUTE Register
 195  *
 196  *  This function configures the Mflag attribute configuratin
 197  *
 198  *  \param    baseAddr   [IN]   base address of DSSUL Common cfg register
 199  *  \param    start      [IN]   value of MFlag START to be configured
 200  *  \param    control    [IN]   value of MFlag control to be configured
 201  *
 202  *  \return
 203  *           DSS_RET_OK - if configuration is success
 204  *           DSS_RET_FAILED - if configuration is failed
 205  *
 206  */
 207 DSS_RET dssDispcMflagAttributeCfg(Uint32 baseAddr, Uint32 start, Uint32 control)
 208 {
 209     DSS_RET status = DSS_RET_FAILED;
 210     Uint32 value = 0;
 211     Uint32 value_start = 0;
 212     Uint32 value_control = 0;
 213
 214     value_start = ((start << \
 215            CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_SHIFT) \
 216         & (CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK));
 217
 218     if ((start == CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MFLAGNORMALSTARTMODE) ||
 219         (start == CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MFLAGFORCESTARTMODE))
 220     {
 221         value_start = start;
 222         status = DSS_RET_OK;
 223     }
 224
 225     value_control = ((control << CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_SHIFT) \
 226                       & (CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK));
 227     if ((control == CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MFLAGDIS) || \
 228         (control == CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MFLAGFORCE) ||\
 229         (control == CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MFLAGEN))
 230     {
 231         value_control = control;
 232         status = DSS_RET_OK;
 233     }
 234
 235     if (status == DSS_RET_OK)
 236     {
 237         value = value_start | value_control;
 238         reg_wr_32(baseAddr + CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE, value);
 239     }
 240     return status;
 241 }
 242
 243 /**
 244  *  \brief    Configures DISPC_GLOBAL_MFLAG_ATTRIBUTE Register
 245  *
 246  *  This function configures the Mflag attribute configuratin
 247  *
 248  *  \param    baseAddr     [IN]   base address of DSSUL Video config register
 249  *  \param    lo_threshold [IN]   value of low threshold
 250  *  \param    hi_threshold [IN]   value of high threshold
 251  *
 252  *  \return
 253  *           DSS_RET_OK - if configuration is success
 254  *           DSS_RET_FAILED - if configuration is failed
 255  */
 256 DSS_RET dssDispcMflagThresholdCfg(Uint32 baseAddr,
 257                                   Uint32 lo_threshold,
 258                                   Uint32 hi_threshold)
 259 {
 260     DSS_RET status = DSS_RET_OK;
 261     Uint32 value = 0;
 262
 263     if ((lo_threshold > CSL_DSSVID_MFLAG_THRESHOLD_LT_MFLAG_MAX) ||
 264        (hi_threshold > CSL_DSSVID_MFLAG_THRESHOLD_HT_MFLAG_MAX))
 265     {
 266         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
 267         status = DSS_RET_FAILED;
 268     }
 269     else
 270     {
 271         /* Program X position */
 272         value = ((lo_threshold << CSL_DSSVID_MFLAG_THRESHOLD_LT_MFLAG_SHIFT) &
 273             (CSL_DSSVID_MFLAG_THRESHOLD_LT_MFLAG_MASK));
 274         /* Program Y position */
 275         value |= ((hi_threshold << CSL_DSSVID_MFLAG_THRESHOLD_HT_MFLAG_SHIFT) &
 276             (CSL_DSSVID_MFLAG_THRESHOLD_HT_MFLAG_MASK));
 277         reg_wr_32(baseAddr + CSL_DSSVID_MFLAG_THRESHOLD, value);
 278     }
 279
 280     return status;
 281 }
 282
 283 /**
 284  *  \brief    Configures the DSS initiator priority
 285  *
 286  *  This function configures the DSS Initiator priority
 287  *
 288  *  \param    baseAddr      [IN]   base address of DSSUL Video config register
 289  *  \param    lo_priority   [IN]   value of low priority
 290  *  \param    hi_priority   [IN]   value of high priority
 291  *
 292  *  \return
 293  *           DSS_RET_OK - if configuration is success
 294  *           DSS_RET_FAILED - if configuration is failed
 295  */
 296 DSS_RET dssInitiatorPriorityCfg(Uint32 baseAddr, Uint32 lo_priority,
 297                                 Uint32 hi_priority)
 298 {
 299     DSS_RET status = DSS_RET_OK;
 300     Uint32 value = 0;
 301
 302     reg_wr_32(KICK0_BASE_ADDRESS, KICK0_UNLOCK);
 303     reg_wr_32(KICK1_BASE_ADDRESS, KICK1_UNLOCK);
 304
 305     if (hi_priority > 0x1) {
 306         IFPRINT (platform_write("Warning: DSS initiator hi priority is being \
 307                                 set to greater than 0x1 \n"));
 308     }
 309
 310     if ((lo_priority > 0x7) || (hi_priority > 0x7)) {
 311         status = DSS_RET_FAILED;
 312         IFPRINT (platform_write("DSS initiator priority cannot be greater than\
 313                                 0x7\n"));
 314         printf("DSS initiator priority cannot be greater than\
 315                                         0x7\n");
 316     }
 317     else {
 318         /* Program dss_pri_lo of DSS in Initiator Priority Control Register 1 */
 319         value = ((lo_priority << DSS_INITIATOR_LOPRI_SHIFT) & (DSS_INITIATOR_LOPRI_MASK));
 320         /* Program dss_pri_hi of DSS in Initiator Priority Control Register 1 */
 321         value |= ((hi_priority << DSS_INITIATOR_HIPRI_SHIFT) & (DSS_INITIATOR_HIPRI_MASK));
 322         reg_wr_32(baseAddr + INITIATOR_PRIORITY_1_OFFSET, value);
 323     }
 324     return status ;
 325 }
 326
 327 /**
 328  *  \brief    Configures panel specific timing parameters
 329  *
 330  *  This function configures the DSS Initiator priority
 331  *
 332  *  \param    baseAddr  [IN]   base address of DSSUL Video port register
 333  *  \param    pLcdCfg   [IN]   pointer to LCD configuration
 334  *
 335  *  \return
 336  *           DSS_RET_OK - if configuration is success
 337  *           DSS_RET_FAILED - if configuration is failed
 338  */
 339 DSS_RET dssDispcLcdPanelCfg(Uint32 baseAddr, lcdCfg_t *pLcdCfg)
 340 {
 341     Uint32 value = 0;
 342     DSS_RET status = DSS_RET_OK;
 343
 344     if (pLcdCfg == NULL)
 345     {
 346         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
 347         return DSS_RET_FAILED;
 348     }
 349
 350     /* Program pixels per line */
 351     value = (((pLcdCfg->LcdWidth - 1U) <<
 352               CSL_DSSVP_SIZE_SCREEN_PPL_SHIFT) &
 353               (CSL_DSSVP_SIZE_SCREEN_PPL_MASK));
 354
 355     /* Program lines per panel */
 356     value |= (((pLcdCfg->LcdHeight - 1U) <<
 357                CSL_DSSVP_SIZE_SCREEN_LPP_SHIFT) &
 358               (CSL_DSSVP_SIZE_SCREEN_LPP_MASK));
 359
 360     reg_wr_32(baseAddr + CSL_DSSVP_SIZE_SCREEN, value);
 361
 362     /* Program hsw value */
 363     value = (((pLcdCfg->HsyncWidth - 1U) << CSL_DSSVP_TIMING_H_HSW_SHIFT) &
 364         (CSL_DSSVP_TIMING_H_HSW_MASK));
 365
 366     /* Program hfp value */
 367     value |= (((pLcdCfg->HFrontPorch - 1U) << CSL_DSSVP_TIMING_H_HFP_SHIFT) &
 368         (CSL_DSSVP_TIMING_H_HFP_MASK));
 369
 370     /* Program hbp value */
 371     value |= (((pLcdCfg->HBackPorch - 1U) << CSL_DSSVP_TIMING_H_HBP_SHIFT) &
 372         (CSL_DSSVP_TIMING_H_HBP_MASK));
 373     reg_wr_32(baseAddr + CSL_DSSVP_TIMING_H, value);
 374
 375     /* Program vsw value */
 376     value = (((pLcdCfg->VsyncWidth - 1U) << CSL_DSSVP_TIMING_V_VSW_SHIFT) &
 377         (CSL_DSSVP_TIMING_V_VSW_MASK));
 378
 379     /* Program hfp value */
 380     value |= ((pLcdCfg->VFrontPorch << CSL_DSSVP_TIMING_V_VFP_SHIFT) &
 381         (CSL_DSSVP_TIMING_V_VFP_MASK));
 382
 383     /* Program hbp value */
 384     value |= ((pLcdCfg->VBackPorch << CSL_DSSVP_TIMING_V_VBP_SHIFT) &
 385         (CSL_DSSVP_TIMING_V_VBP_MASK));
 386     reg_wr_32(baseAddr + CSL_DSSVP_TIMING_V, value);
 387
 388     return status;
 389 }
 390
 391 /**
 392  *  \brief    Configures LCD color attributes
 393  *
 394  *  This function configures the LCD color attributes
 395  *
 396  *  \param    baseAddr   [IN]   base address of DSSUL Video port register
 397  *  \param    pDispCfg   [IN]   pointer to LCD configuration
 398  *
 399  *  \return
 400  *           DSS_RET_OK - if configuration is success
 401  *           DSS_RET_FAILED - if configuration is failed
 402  */
 403 DSS_RET dssDispcLcdDisplayAttribCfg(Uint32 baseAddr,
 404                                    dispCfg_t *pDispCfg)
 405 {
 406     DSS_RET status = DSS_RET_OK;
 407     Uint32 value  = 0;
 408
 409     /* Clear display type, monoColor, data lines, mono8bit fields */
 410     value = reg_rd_32(baseAddr + CSL_DSSVP_CONTROL);
 411
 412     value &= (~(CSL_DSSVP_CONTROL_STN_MASK | CSL_DSSVP_CONTROL_MONOCOLOR_MASK |
 413             CSL_DSSVP_CONTROL_VPPROGLINENUMBERMODULO_MASK | CSL_DSSVP_CONTROL_M8B_MASK));
 414
 415     if (NULL != pDispCfg)
 416     {
 417         /* Configure LCD Data Lines */
 418         value |= ((pDispCfg->dataLines << CSL_DSSVP_CONTROL_DATALINES_SHIFT) &
 419                     (CSL_DSSVP_CONTROL_DATALINES_MASK));
 420
 421         /* Configure passive matrix display specific parameters */
 422         if(DSS_LCD_TYPE_PASSIVE == pDispCfg->displayType)
 423         {
 424             /* Configure Color or Monochrome */
 425             value |= ((pDispCfg->colorMode << CSL_DSSVP_CONTROL_MONOCOLOR_SHIFT) &
 426                 (CSL_DSSVP_CONTROL_MONOCOLOR_MASK));
 427             /* Configure Mono8 or Mono4 bit */
 428             if(DSS_LCD_DISPLAY_MONO == pDispCfg->colorMode)
 429             {
 430                 value |= ((pDispCfg->mono8Bit << CSL_DSSVP_CONTROL_M8B_SHIFT) &
 431                     (CSL_DSSVP_CONTROL_M8B_MASK));
 432             }
 433         }
 434         reg_wr_32(baseAddr + CSL_DSSVP_CONTROL, value);
 435     }
 436     else
 437     {
 438         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
 439         status = DSS_RET_FAILED;
 440     }
 441
 442     return status;
 443 }
 444
 445 /**
 446  *  \brief    Configures control signal polarities
 447  *
 448  *  This function configures the control signal polarities
 449  *
 450  *  \param    baseAddr   [IN]   base address of DSSUL Video port register
 451  *  \param    pTmgCfg   [IN]   pointer to timing configuration
 452  *
 453  *  \return
 454  *           DSS_RET_OK - if configuration is success
 455  *           DSS_RET_FAILED - if configuration is failed
 456  */
 457 DSS_RET dssDispcLcdTimingCfg(Uint32 baseAddr,
 458                             tmgCfg_t *pTmgCfg)
 459 {
 460     DSS_RET status = DSS_RET_OK;
 461     Uint32 value = 0;
 462
 463     //reg_wr_32(baseAddr + CSL_DSSVP_POL_FREQ, 0x4000);
 464     if (NULL != pTmgCfg)
 465     {
 466 #if 1
 467         /* Program hsync polarity value */
 468         value = ((pTmgCfg->hsyncPolarity << CSL_DSSVP_POL_FREQ_IHS_SHIFT) &
 469             (CSL_DSSVP_POL_FREQ_IHS_MASK));
 470         /* Program vsync polarity value */
 471         value |= ((pTmgCfg->vsyncPolarity << CSL_DSSVP_POL_FREQ_IVS_SHIFT) &
 472             (CSL_DSSVP_POL_FREQ_IVS_MASK));
 473 #endif
 474         /* Program sync edge type */
 475         value |= ((pTmgCfg->syncEdge << CSL_DSSVP_POL_FREQ_RF_SHIFT) &
 476             (CSL_DSSVP_POL_FREQ_RF_MASK));
 477         /* Program sync edge control */
 478         value |= ((pTmgCfg->syncEdgeCtrl << CSL_DSSVP_POL_FREQ_ONOFF_SHIFT) &
 479             (CSL_DSSVP_POL_FREQ_ONOFF_MASK));
 480         /* Program Output enable polarity */
 481         value |= ((pTmgCfg->outputEnablePolarity << CSL_DSSVP_POL_FREQ_IEO_SHIFT) &
 482             (CSL_DSSVP_POL_FREQ_IEO_MASK));
 483         /* program acb pin frequency */
 484         value |= ((pTmgCfg->acbFrequency << CSL_DSSVP_POL_FREQ_ACB_SHIFT) &
 485             (CSL_DSSVP_POL_FREQ_ACB_MASK));
 486         /* program acb pin transitions per interrupt */
 487         value |= ((pTmgCfg->acbi << CSL_DSSVP_POL_FREQ_ACBI_SHIFT) &
 488             (CSL_DSSVP_POL_FREQ_ACBI_MASK));
 489         /* program pixel clock polarity */
 490 #if 1
 491         value |= ((pTmgCfg->pclkPolarity << CSL_DSSVP_POL_FREQ_IPC_SHIFT) &
 492             (CSL_DSSVP_POL_FREQ_IPC_MASK));
 493 #endif
 494         /* Write into the register */
 495         reg_wr_32(baseAddr + CSL_DSSVP_POL_FREQ, value);
 496
 497         /* Clear clock gated control for sync, acb and pixel clock */
 498         value = reg_rd_32(baseAddr + CSL_DSSVP_CONFIG);
 499         value &= (~(CSL_DSSVP_CONFIG_EXTERNALSYNCEN_MASK | CSL_DSSVP_CONFIG_HSYNCGATED_MASK |
 500                 CSL_DSSVP_CONFIG_VSYNCGATED_MASK | CSL_DSSVP_CONFIG_PIXELGATED_MASK));
 501
 502         /* Program hsync clock gated control */
 503         value |= ((pTmgCfg->hsyncGated << CSL_DSSVP_CONFIG_HSYNCGATED_SHIFT) &
 504             (CSL_DSSVP_CONFIG_HSYNCGATED_MASK));
 505         /* Program vsync clock gated control */
 506         value |= ((pTmgCfg->vsyncGated << CSL_DSSVP_CONFIG_VSYNCGATED_SHIFT) &
 507             (CSL_DSSVP_CONFIG_VSYNCGATED_MASK));
 508         /* Program acb clock gated control */
 509         value |= ((pTmgCfg->acbGated << CSL_DSSVP_CONFIG_EXTERNALSYNCEN_SHIFT) &   //No gated macro for ACBIAS, these should still work. Need to confirm
 510             (CSL_DSSVP_CONFIG_EXTERNALSYNCEN_MASK));
 511         /* Program pixel clock gated control */
 512         value |= ((pTmgCfg->pixelClkGated << CSL_DSSVP_CONFIG_PIXELCLOCKGATED_SHIFT) &
 513                 CSL_DSSVP_CONFIG_PIXELCLOCKGATED_MASK);
 514         reg_wr_32(baseAddr + CSL_DSSVP_CONFIG, value);
 515     }
 516     else
 517     {
 518         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
 519         status = DSS_RET_FAILED;
 520     }
 521     return status;
 522 }
 523
 524 /**
 525  *  \brief    Disables ST Dithering
 526  *
 527  *  This function Disables ST Dithering
 528  *
 529  *  \param    baseAddr   [IN]   base address of DSSUL register
 530  *
 531  *  \return
 532  *          NONE
 533  */
 534 void dssDispcSTDitheringDisable(Uint32 baseAddr)
 535 {
 536     Uint32 value = 0;
 537
 538     value = reg_rd_32(baseAddr + CSL_DSSVP_CONTROL) & (~CSL_DSSVP_CONTROL_STDITHERENABLE_MASK);
 539     reg_wr_32(baseAddr + CSL_DSSVP_CONTROL, value);
 540 }
 541
 542 /**
 543  *  \brief    Bypasses RFBI mode
 544  *
 545  *  This function bypasses RFBI mode
 546  *
 547  *  \param    baseAddr   [IN]   base address of DSSUL register
 548  *
 549  *  \return
 550  *          NONE
 551  */
 552 void dssDispcRfbiModeBypass(Uint32 baseAddr)
 553 {
 554     Uint32 value = 0;
 555
 556     value = reg_rd_32(baseAddr + CSL_DSSRFBI_RFBI_CONTROL);
 557
 558     value |= CSL_DSSRFBI_RFBI_CONTROL_BYPASSMODE_BYPASS;
 559     reg_wr_32(baseAddr + CSL_DSSRFBI_RFBI_CONTROL, value);
 560 }
 561
 562 /**
 563  *  \brief    Clear existing interrupts
 564  *
 565  *  This function clears the interrupt status
 566  *
 567  *  \param    baseAddr   [IN]   base address of DSSUL register
 568  *  \param    intFlag    [IN]   interrupt flag to be cleared
 569  *
 570  *  \return
 571  *          NONE
 572  */
 573 void dssDispcIntStatusClearEx(Uint32 baseAddr, Uint32 intFlag)
 574 {
 575     reg_wr_32(baseAddr + CSL_DSSVP_IRQSTATUS, intFlag);
 576 }
 577
 578 /**
 579  *  \brief    Configures the line number that generates interrupt
 580  *
 581  *  This function configures the line number that generates interrupt
 582  *
 583  *  \param    baseAddr   [IN]   base address of DSSUL register
 584  *  \param    lineNumber [IN]   line number that generates interrupt
 585  *
 586  *  \return
 587  *          NONE
 588  */
 589 void dssDispcProgLineNumberSet(Uint32 baseAddr, Uint32 lineNumber)
 590 {
 591     Uint32 value = 0;
 592
 593     /* Clear the line number field */
 594     value = reg_rd_32(baseAddr + CSL_DSSVP_LINE_NUMBER) & (~CSL_DSSVP_LINE_NUMBER_LINENUMBER_MASK);
 595
 596     /* Program the line number field */
 597     value |= ((lineNumber << CSL_DSSVP_LINE_NUMBER_LINENUMBER_SHIFT) & CSL_DSSVP_LINE_NUMBER_LINENUMBER_MASK);
 598     reg_wr_32(baseAddr + CSL_DSSVP_LINE_NUMBER, value);
 599 }
 600
 601 /**
 602  *  \brief    Enable/Disable DPI Control
 603  *
 604  *  This function enables/disables DPI interface from the registers
 605  *
 606  *  \param    baseAddr   [IN]   base address of DSSUL register
 607  *  \param    enableFlag [IN]   flag to indicate enable/disable
 608  *
 609  *  \return
 610  *          NONE
 611  */
 612 void dssDpiCtrl(Uint32 baseAddr,
 613                 Uint32 enableFlag)
 614 {
 615     Uint32 value = 0;
 616
 617     value = reg_rd_32(baseAddr + CSL_DSS_DSS_DPI_CTRL);
 618
 619     if (TRUE == enableFlag)
 620     {
 621         /* Enable DPI interface */
 622         value |= ((1 << CSL_DSS_DSS_DPI_CTRL_DPI_ENABLE_SHIFT) &
 623             (CSL_DSS_DSS_DPI_CTRL_DPI_ENABLE_MASK));
 624     }
 625     else
 626     {
 627         /* Disable DPI interface */
 628         value &= (~CSL_DSS_DSS_DPI_CTRL_DPI_ENABLE_MASK);
 629     }
 630     reg_wr_32(baseAddr + CSL_DSS_DSS_DPI_CTRL, value);
 631 }
 632
 633 /**
 634  *  \brief    Enable LCD output
 635  *
 636  *  This function enables/disables LCD output
 637  *
 638  *  \param    baseAddr   [IN]   base address of Video Port register
 639  *  \param    enableFlag [IN]   flag to indicate enable/disable
 640  *
 641  *  \return
 642  *          NONE
 643  */
 644 void dssDispcLcdOutputEnableCtrl(Uint32 baseAddr, Uint32 enableFlag)
 645 {
 646     Uint32 value = 0;
 647
 648     value = reg_rd_32(baseAddr + CSL_DSSVP_CONTROL);
 649
 650     if (TRUE == enableFlag)
 651     {
 652         /* Enable LCD output */
 653         value |= ((1 << CSL_DSSVP_CONTROL_LCDEN_SHIFT) &
 654             (CSL_DSSVP_CONTROL_LCDEN_MASK));
 655     }
 656     else
 657     {
 658         /* Disable LCD output */
 659         value &= (~CSL_DSSVP_CONTROL_LCDEN_MASK);
 660     }
 661     reg_wr_32(baseAddr + CSL_DSSVP_CONTROL, value);
 662 }
 663
 664 /**
 665  *  \brief    Performs software reset of the Display Controller
 666  *
 667  *  This function performs software reset of the display controller.
 668  *
 669  *  \param    baseAddr   [IN]   base address of Video Port register
 670  *
 671  *  \return
 672  *          NONE
 673  */
 674 void dssDispcSoftReset(Uint32 baseAddr)
 675 {
 676     Uint32 value = 0;
 677
 678     value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG);
 679
 680     value |= ((CSL_DSSCOMMON_DISPC_SYSCONFIG_SOFTRESET << CSL_DSSCOMMON_DISPC_SYSCONFIG_SOFTRESET_SHIFT) &
 681         (CSL_DSSCOMMON_DISPC_SYSCONFIG_SOFTRESET_MASK));
 682
 683     /* Performing Software Reset of the module */
 684     reg_wr_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG, value);
 685
 686     /* Wait until the process of Module Reset is complete */
 687     while(!((reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSSTATUS)) &
 688         (CSL_DSSCOMMON_DISPC_SYSSTATUS_DISPC_FUNC_RESETDONE_MASK)));
 689 }
 690
 691 /**
 692  *  \brief    Enable/Disable the auto-idle function
 693  *
 694  *  This function enables/disables the auto idle function of the Display
 695  *  controller
 696  *
 697  *  \param    baseAddr   [IN]   base address of Video Port register
 698  *  \param    enableFlag [IN]   flag to indicate enable/disable
 699  *
 700  *  \return
 701  *          NONE
 702  */
 703 void dssDispcAutoIdleEnableCtrl(Uint32 baseAddr, Uint32 enableFlag)
 704 {
 705     Uint32 value = 0;
 706
 707     value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG);
 708
 709     if (TRUE == enableFlag)
 710     {
 711         /* Enable auto idle mechanism */
 712         value |= ((CSL_DSSCOMMON_DISPC_SYSCONFIG_AUTOIDLE_CLKGATED <<
 713                 CSL_DSSCOMMON_DISPC_SYSCONFIG_AUTOIDLE_SHIFT) & (CSL_DSSCOMMON_DISPC_SYSCONFIG_AUTOIDLE_MASK));
 714     }
 715     else
 716     {
 717         /* Disable auto idle mechanism */
 718         value &= (~CSL_DSSCOMMON_DISPC_SYSCONFIG_AUTOIDLE_MASK);
 719     }
 720     reg_wr_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG, value);
 721 }
 722
 723 /**
 724  *  \brief    Configure video pipeline DMA specific parameters
 725  *
 726  *  This function configures video pipeline DMA specific parameters
 727  *
 728  *  \param    baseAddr   [IN]   base address of Video Port register
 729  *  \param    pDmaCfg    [IN]   pointer to DMA configuration
 730  *
 731  *  \return
 732  *           DSS_RET_OK - if configuration is success
 733  *           DSS_RET_FAILED - if configuration is failed
 734  */
 735 DSS_RET dssDispcVidDMAConfig(Uint32 baseAddr,
 736                             dmaCfg_t *pDmaCfg)
 737 {
 738     DSS_RET status = DSS_RET_OK;
 739     Uint32 cfgValue = 0;
 740
 741     if(NULL != pDmaCfg)
 742     {
 743         cfgValue = reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
 744
 745         /* Clear the burst size and preload select fields */
 746         cfgValue &= ~(CSL_DSSVID_ATTRIBUTES_BUFPRELOAD_MASK);
 747         /* Program the preload selection field */
 748         cfgValue |= ((pDmaCfg->preloadSelect <<
 749                 CSL_DSSVID_ATTRIBUTES_BUFPRELOAD_SHIFT) &
 750                 CSL_DSSVID_ATTRIBUTES_BUFPRELOAD_MASK);
 751         reg_wr_32(baseAddr + CSL_DSSVID_ATTRIBUTES, cfgValue);
 752
 753         /* program the low threshold field */
 754         cfgValue = ((pDmaCfg->fifoLoThr << CSL_DSSVID_BUF_THRESHOLD_BUFLOWTHRESHOLD_SHIFT) &
 755             (CSL_DSSVID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK));
 756         /* Program the high threshold field */
 757         cfgValue |= ((pDmaCfg->fifoHiThr << CSL_DSSVID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_SHIFT) &
 758             (CSL_DSSVID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK));
 759         reg_wr_32(baseAddr + CSL_DSSVID_BUF_THRESHOLD, cfgValue);
 760
 761         /* Program row increment value */
 762         cfgValue = ((pDmaCfg->rowInc << CSL_DSSVID_ROW_INC_ROWINC_SHIFT) &
 763                 CSL_DSSVID_ROW_INC_ROWINC_MASK);
 764         reg_wr_32(baseAddr + CSL_DSSVID_ROW_INC, cfgValue);
 765         /* Program pixel increment value */
 766         cfgValue = ((pDmaCfg->pixelInc << CSL_DSSVID_PIXEL_INC_PIXELINC_SHIFT) &
 767             (CSL_DSSVID_PIXEL_INC_PIXELINC_MASK));
 768         reg_wr_32(baseAddr + CSL_DSSVID_PIXEL_INC, cfgValue);
 769     }
 770     else
 771     {
 772         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
 773         status = DSS_RET_FAILED;
 774     }
 775
 776     return status;
 777 }
 778
 779 /**
 780  *  \brief    Video pipeline interrupt enable
 781  *
 782  *  This function enables video pipeline interrupt
 783  *
 784  *  \param    baseAddr [IN]   base address of Video pipeline register
 785  *  \param    intFlag  [IN]   interrupt flag to enable
 786  *
 787  *  \return
 788  *          NONE
 789  */
 790 void dssDispcVidIntEnable(Uint32 baseAddr, Uint32 intFlag)
 791 {
 792     Uint32 value = 0;
 793
 794     value = (reg_rd_32(baseAddr + CSL_DSSVID_IRQENABLE) | (intFlag));
 795     reg_wr_32(baseAddr + CSL_DSSVID_IRQENABLE, value);
 796 }
 797
 798 /**
 799  *  \brief    Video pipeline interrupt disable
 800  *
 801  *  This function disables video pipeline interrupt
 802  *
 803  *  \param    baseAddr [IN]   base address of Video pipeline register
 804  *  \param    intFlag  [IN]   interrupt flag to disable
 805  *
 806  *  \return
 807  *          NONE
 808  */
 809 void dssDispcVidIntDisable(Uint32 baseAddr, Uint32 intFlag)
 810 {
 811     Uint32 value = 0;
 812
 813     value = (reg_rd_32(baseAddr + CSL_DSSVID_IRQENABLE) & ~(intFlag));
 814     reg_wr_32(baseAddr + CSL_DSSVID_IRQENABLE, value);
 815 }
 816
 817 /**
 818  *  \brief    Enable the video pipeline
 819  *
 820  *  This function enables/disables the video pipeline
 821  *
 822  *  \param    baseAddr   [IN]   base address of Video Port register
 823  *  \param    enableFlag [IN]   flag to indicate enable/disable
 824  *
 825  *  \return
 826  *          NONE
 827  */
 828 void dssDispcVidEnableCtrl(Uint32 baseAddr,
 829                            Uint32 enableFlag)
 830 {
 831     Uint32 value = 0;
 832
 833     value = reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
 834     if(TRUE == enableFlag)
 835     {
 836         /* Enable video pipeline */
 837         value |= ((CSL_DSSVID_ATTRIBUTES_ENABLE_VIDEOENB << CSL_DSSVID_ATTRIBUTES_ENABLE_SHIFT) &
 838             (CSL_DSSVID_ATTRIBUTES_ENABLE_MASK));
 839     }
 840     else
 841     {
 842         /* Disable video pipeline */
 843         value &= (~CSL_DSSVID_ATTRIBUTES_ENABLE_MASK);
 844     }
 845     reg_wr_32(baseAddr + CSL_DSSVID_ATTRIBUTES, value);
 846 }
 847
 848 /**
 849  *  \brief    VP interrupt enable
 850  *
 851  *  This function enables VP interrupt
 852  *
 853  *  \param    baseAddr   [IN]   base address of Video Port register
 854  *  \param    intFlag    [IN]   interrupt flag to be enabled
 855  *
 856  *  \return
 857  *          NONE
 858  */
 859 void dssDispcVPIntEnable(Uint32 baseAddr, Uint32 intFlag)
 860 {
 861     Uint32 value = 0;
 862
 863     value = (reg_rd_32(baseAddr + CSL_DSSVP_IRQENABLE) | (intFlag));
 864     reg_wr_32(baseAddr + CSL_DSSVP_IRQENABLE, value);
 865 }
 866
 867 /**
 868  *  \brief    VP interrupt disable
 869  *
 870  *  This function disables VP interrupt
 871  *
 872  *  \param    baseAddr   [IN]   base address of Video Port register
 873  *  \param    intFlag    [IN]   interrupt flag to be disabled
 874  *
 875  *  \return
 876  *          NONE
 877  */
 878 void dssDispcVPIntDisable(Uint32 baseAddr, Uint32 intFlag)
 879 {
 880     Uint32 value = 0;
 881
 882     value = (reg_rd_32(baseAddr + CSL_DSSVP_IRQENABLE) & ~(intFlag));
 883     reg_wr_32(baseAddr + CSL_DSSVP_IRQENABLE, value);
 884 }
 885
 886 /**
 887  *  \brief    Enable interrupts to VID or VP
 888  *
 889  *  This function enables interrupts to VID or VP
 890  *
 891  *  \param    baseAddr   [IN]   base address of Video Port register
 892  *  \param    intFlag    [IN]   interrupt flag to be enabled
 893  *
 894  *  \return
 895  *          NONE
 896  */
 897 void dssDispcCommonIntEnable(Uint32 baseAddr,
 898                            Uint32 intFlag)
 899 {
 900     Uint32 value = 0;
 901
 902     value = (reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_SET) | (intFlag));
 903     reg_wr_32(baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_SET, value);
 904 }
 905
 906 /**
 907  *  \brief    Disable interrupts to VID or VP
 908  *
 909  *  This function disables interrupts to VID or VP
 910  *
 911  *  \param    baseAddr   [IN]   base address of Video Port register
 912  *  \param    intFlag    [IN]   interrupt flag to be disabled
 913  *
 914  *  \return
 915  *          NONE
 916  */
 917 void dssDispcCommonIntDisable(Uint32 baseAddr,
 918                            Uint32 intFlag)
 919 {
 920     Uint32 value = 0;
 921
 922     value = (reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_CLR) | (intFlag));
 923     reg_wr_32(baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_CLR, value);
 924 }
 925
 926 /**
 927  *  \brief    Update shadow registers, set the Go bit
 928  *
 929  *  This function updates shadow registers and sets the GO bit
 930  *
 931  *  \param    baseAddr   [IN]   base address of Video Port register
 932  *
 933  *  \return
 934  *          NONE
 935  */
 936 void dssDispcShadowCfgEnable(Uint32 baseAddr)
 937 {
 938     Uint32 value = 0;
 939
 940     /* Check to ensure that GOLCD bit is clear */
 941     while((reg_rd_32(baseAddr + CSL_DSSVP_CONTROL)) & (CSL_DSSVP_CONTROL_GOBIT_MASK));
 942
 943     value = reg_rd_32(baseAddr + CSL_DSSVP_CONTROL);
 944
 945     /* Set the GoLCD bit */
 946     value |= ((1 << CSL_DSSVP_CONTROL_GOBIT_SHIFT) & (CSL_DSSVP_CONTROL_GOBIT_MASK));
 947     reg_wr_32(baseAddr + CSL_DSSVP_CONTROL, value);
 948 }
 949
 950 /**
 951  *  \brief    Erase frame buffer
 952  *
 953  *  \param    pLcdCfg   [IN]   pointer to LCD Configuration
 954  *
 955  *  \return
 956  *          NONE
 957  */
 958 void dssEraseBuffer(lcdCfg_t *pLcdCfg)
 959 {
 960     unsigned int x,y;
 961
 962     for (y = 0; y < pLcdCfg->LcdHeight; y++)
 963         for (x = 0; x < pLcdCfg->LcdWidth; x++)
 964             *(pFrameBuffer + (y*pLcdCfg->LcdWidth) + (x) ) = BLACK;
 965 }
 966
 967 /**
 968  *  \brief    Set priority of Vid DMA
 969  *
 970  *  This function set the priority of Video DMA
 971  *
 972  *  \param    baseAddr   [IN]   base address of Video Port register
 973  *  \param    priorityFlag [IN]   flag to indicate priority
 974  *
 975  *  \return
 976  *          NONE
 977  */
 978 void dssDispcVidPrioritySet(Uint32 baseAddr, Uint32 priorityFlag)
 979 {
 980     Uint32  value = 0;
 981
 982     /* Clear the priority field */
 983     value = ((reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES)) &
 984         (~CSL_DSSVID_ATTRIBUTES_ARBITRATION_MASK));
 985
 986     /* Program the priority field */
 987     value |= ((priorityFlag << CSL_DSSVID_ATTRIBUTES_ARBITRATION_SHIFT) &
 988             CSL_DSSVID_ATTRIBUTES_ARBITRATION_MASK);
 989     reg_wr_32(baseAddr + CSL_DSSVID_ATTRIBUTES, value);
 990 }
 991
 992 /**
 993  *  \brief    Enable/Disable self refresh
 994  *
 995  *  This function enables/disables the self refresh
 996  *
 997  *  \param    baseAddr   [IN]   base address of Video Port register
 998  *  \param    enableFlag [IN]   flag to indicate enable/disable
 999  *
1000  *  \return
1001  *          NONE
1002  */
1003 void dssDispcVidSelfRefEnableCtrl(Uint32 baseAddr, Uint32 enableFlag)
1004 {
1005     Uint32 value = 0;
1006
1007     value =  reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
1008
1009     if (TRUE == enableFlag)
1010     {
1011         /* Enable self refresh */
1012         value |= ((1 << CSL_DSSVID_ATTRIBUTES_SELFREFRESH_SHIFT) &
1013                 CSL_DSSVID_ATTRIBUTES_SELFREFRESH_MASK);
1014     }
1015     else
1016     {
1017         /* Disable self refresh */
1018         value &= (~CSL_DSSVID_ATTRIBUTES_SELFREFRESH_MASK);
1019     }
1020     reg_wr_32(baseAddr + CSL_DSSVID_ATTRIBUTES, value);
1021 }
1022
1023 /**
1024  *  \brief    Configure base address of frame buffer
1025  *
1026  *  This function configures the base address of frame buffer
1027  *
1028  *  \param    baseAddr      [IN]   base address of Video Port register
1029  *  \param    bufAddr       [IN]   buffer address
1030  *  \param    bufSelectFlag [IN]   buffer select flag
1031  *
1032  *  \return
1033  *          NONE
1034  */
1035 void dssDispcVidSetBufAddr(Uint32 baseAddr,
1036                            Uint32 bufAddr,
1037                            Uint32 bufSelectFlag)
1038 {
1039    reg_wr_32(baseAddr + CSL_DSSVID_BA(bufSelectFlag), bufAddr);
1040 }
1041
1042 /**
1043  *  \brief    Configure video window position
1044  *
1045  *  This function configures the video window position
1046  *
1047  *  \param    baseAddr   [IN]   base address of Video Port register
1048  *  \param    xPos       [IN]   X position of video window
1049  *  \param    yPos       [IN]   Y position of video window
1050  *
1051  *  \return
1052  *           DSS_RET_OK - if configuration is success
1053  *           DSS_RET_FAILED - if configuration is failed
1054  */
1055 DSS_RET dssDispcVidOvlyPositionCfg(Uint32 baseAddr,
1056                                   Uint32 xPos,
1057                                   Uint32 yPos)
1058 {
1059     DSS_RET status = DSS_RET_OK;
1060     Uint32 value = 0;
1061
1062     if ((xPos > DSS_DISPC_VID_WINDOW_XPOS_MAX) ||
1063        (yPos > DSS_DISPC_VID_WINDOW_YPOS_MAX))
1064     {
1065         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
1066         status = DSS_RET_FAILED;
1067     }
1068     else
1069     {
1070         /* Program X position */
1071         value = ((xPos << CSL_DSSVID_POSITION_POSX_SHIFT) &
1072             (CSL_DSSVID_POSITION_POSX_MASK));
1073         /* Program Y position */
1074         value |= ((yPos << CSL_DSSVID_POSITION_POSY_SHIFT) &
1075             (CSL_DSSVID_POSITION_POSY_MASK));
1076         reg_wr_32(baseAddr + CSL_DSSVID_POSITION, value);
1077     }
1078
1079     return status;
1080 }
1081
1082 /**
1083  *  \brief    Configure video window size
1084  *
1085  *  This function configures the video window size
1086  *
1087  *  \param    baseAddr   [IN]   base address of Video Port register
1088  *  \param    width      [IN]   Video width
1089  *  \param    height     [IN]   Video height
1090  *
1091  *  \return
1092  *           DSS_RET_OK - if configuration is success
1093  *           DSS_RET_FAILED - if configuration is failed
1094  */
1095
1096 DSS_RET dssDispcVidSizeCfg(Uint32 baseAddr,
1097                           Uint32 height,
1098                           Uint32 width)
1099 {
1100     DSS_RET status = DSS_RET_OK;
1101     Uint32 value = 0;
1102
1103     if ((width < DSS_DISPC_VID_SIZE_X_MIN) ||
1104         (width > DSS_DISPC_VID_SIZE_X_MAX) ||
1105         (height < DSS_DISPC_VID_SIZE_Y_MIN) ||
1106         (height > DSS_DISPC_VID_SIZE_Y_MAX))
1107     {
1108         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
1109         status = DSS_RET_FAILED;
1110     }
1111     else
1112     {
1113         /* Program Y size(width) */
1114         value = (((width - 1) << CSL_DSSVID_SIZE_SIZEY_SHIFT) &
1115                 CSL_DSSVID_SIZE_SIZEY_MASK);
1116         /* Program X size (height) */
1117         value |= (((height - 1) << CSL_DSSVID_SIZE_SIZEX_SHIFT) &
1118                 CSL_DSSVID_SIZE_SIZEX_MASK);
1119         reg_wr_32(baseAddr + CSL_DSSVID_SIZE, value);
1120
1121         /* UG: Program Picture_Size */
1122         /* Program Y size (width) */
1123         value = (((width - 1) << CSL_DSSVID_PICTURE_SIZE_MEMSIZEY_SHIFT) &
1124                 CSL_DSSVID_PICTURE_SIZE_MEMSIZEY_MASK);
1125
1126         /* Program X size (height) */
1127         value |= (((height - 1) << CSL_DSSVID_PICTURE_SIZE_MEMSIZEX_SHIFT) &
1128                 CSL_DSSVID_PICTURE_SIZE_MEMSIZEX_MASK);
1129         reg_wr_32(baseAddr + CSL_DSSVID_PICTURE_SIZE, value);
1130     }
1131     return status;
1132 }
1133
1134 /**
1135  *  \brief    Configure video window data format
1136  *
1137  *  This function configures the video window data format
1138  *
1139  *  \param    baseAddr    [IN]   base address of Video Port register
1140  *  \param    format      [IN]   format to be configured
1141  *  \param    nibbleModen [IN]   Nibble mode
1142  *
1143  *  \return
1144  *          NONE
1145  */
1146 void dssDispcVidFormatSet(Uint32 baseAddr,
1147                           Uint32 format,
1148                           Uint32 nibbleModen)
1149 {
1150     Uint32 value = 0;
1151
1152     value = reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
1153
1154     /* Clear format, endianness, nibble mode, replication fields */
1155     value &= (~(CSL_DSSVID_ATTRIBUTES_FORMAT_MASK |
1156         CSL_DSSVID_ATTRIBUTES_NIBBLEMODE_MASK));
1157
1158     /* Program the graphics format field */
1159     value |= ((format << CSL_DSSVID_ATTRIBUTES_FORMAT_SHIFT) & CSL_DSSVID_ATTRIBUTES_FORMAT_MASK);
1160     /* Program the nibble mode field */
1161     value |= ((nibbleModen << CSL_DSSVID_ATTRIBUTES_NIBBLEMODE_SHIFT) &
1162             CSL_DSSVID_ATTRIBUTES_NIBBLEMODE_MASK);
1163
1164     reg_wr_32(baseAddr + CSL_DSSVID_ATTRIBUTES, value);
1165 }
1166
1167 /**
1168  *  \brief    DSS Interrupt Handler
1169  *
1170  *  This is the DSS Interrupt Handler
1171  *
1172  *  \return
1173  *          NONE
1174  */
1175 void dssIsr(void)
1176 {
1177     Uint32 vidIrqStatus = 0;
1178     Uint32 vpIrqStatus = 0;
1179
1180     vidIrqStatus = reg_rd_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVID_IRQSTATUS);
1181     vpIrqStatus = reg_rd_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVP_IRQSTATUS);
1182
1183     /*
1184      * Check for Video pipeline interrupts
1185      */
1186     if(vidIrqStatus != 0x0)
1187     {
1188         if(vidIrqStatus & CSL_DSSVID_IRQSTATUS_VIDBUFFERUNDERFLOW_IRQ_MASK)
1189         {
1190             /* Clear the interrupt */
1191             reg_wr_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVID_IRQSTATUS, vidIrqStatus | CSL_DSSVID_IRQSTATUS_VIDBUFFERUNDERFLOW_IRQ_MASK);
1192
1193             count_underflow[index] = count;
1194             index++;
1195             if (index == 10){
1196                 index = 0;
1197             }
1198
1199         }else if(vidIrqStatus & CSL_DSSVID_IRQSTATUS_VIDENDWINDOW_IRQ_MASK)
1200         {
1201             /* Clear the interrupt */
1202             reg_wr_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVID_IRQSTATUS, vidIrqStatus | CSL_DSSVID_IRQSTATUS_VIDENDWINDOW_IRQ_MASK);
1203         }
1204     }
1205
1206     /*
1207      * Check for VP pipeline interrupts
1208      */
1209     if(vpIrqStatus != 0x0)
1210     {
1211         /* Synchronization lost interrupt? */
1212         if(vpIrqStatus && CSL_DSSVP_IRQSTATUS_VPSYNCLOST_IRQ_MASK)
1213         {
1214             /* Clear the interrupt */
1215             reg_wr_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVP_IRQSTATUS, vpIrqStatus | CSL_DSSVP_IRQSTATUS_VPSYNCLOST_IRQ_MASK);
1216
1217         /* Programmed line number interrupt? */
1218         }else if(vpIrqStatus && CSL_DSSVP_IRQSTATUS_VPPROGRAMMEDLINENUMBER_IRQ_MASK)
1219         {
1220             /* Clear the interrupt */
1221             reg_wr_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVP_IRQSTATUS, vpIrqStatus | CSL_DSSVP_IRQSTATUS_VPPROGRAMMEDLINENUMBER_IRQ_MASK);
1222
1223         /* Frame done interrupt? */
1224         }else if(vpIrqStatus && CSL_DSSVP_IRQSTATUS_VPFRAMEDONE_IRQ_MASK)
1225         {
1226             /* Clear the interrupt */
1227             reg_wr_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVP_IRQSTATUS, vpIrqStatus | CSL_DSSVP_IRQSTATUS_VPFRAMEDONE_IRQ_MASK);
1228             count++;
1229         }
1230     }
1231 }
1232 /**
1233  *  \brief    DSS Register Dump
1234  *
1235  *  This function dumps the DSS module register values
1236  *
1237  *  \param    dssInfo    [IN]   dssInfo structure passed from LCD panel init
1238  *
1239  *  \return   none
1240  *
1241  */
1242 #if (PLATFORM_DEBUG)
1243 void dssDumpReg(dssInfo_t *dssInfo)
1244 {
1245         Uint32 baseAddr = 0;
1246         Uint32 value = 0;
1247
1248     lcdCfg_t  lcdCfg;
1249     dispCfg_t dispCfg;
1250     tmgCfg_t  tmgCfg;
1251     dmaCfg_t  vidDmaCfg;
1252
1253     lcdCfg = dssInfo->lcdCfg;
1254     dispCfg = dssInfo->dispCfg;
1255     tmgCfg = dssInfo->tmgCfg;
1256     vidDmaCfg = dssInfo->vidDmaCfg;
1257
1258     IFPRINT(platform_write("%s: LcdWidth-%d\n\n",__FUNCTION__, lcdCfg.LcdWidth));
1259     IFPRINT(platform_write("%s: LcdHeight-%d\n\n",__FUNCTION__, lcdCfg.LcdHeight));
1260     IFPRINT(platform_write("%s: LcdPclk-%d\n\n",__FUNCTION__, lcdCfg.LcdPclk));
1261     IFPRINT(platform_write("%s: HsyncWidth-%d\n\n",__FUNCTION__, lcdCfg.HsyncWidth));
1262     IFPRINT(platform_write("%s: HFrontPorch-%d\n\n",__FUNCTION__, lcdCfg.HFrontPorch));
1263     IFPRINT(platform_write("%s: HBackPorch-%d\n\n",__FUNCTION__, lcdCfg.HBackPorch));
1264     IFPRINT(platform_write("%s: VsyncWidth-%d\n\n",__FUNCTION__, lcdCfg.VsyncWidth));
1265     IFPRINT(platform_write("%s: VFrontPorch-%d\n\n",__FUNCTION__, lcdCfg.VFrontPorch));
1266     IFPRINT(platform_write("%s: VBackPorch-%d\n\n",__FUNCTION__, lcdCfg.VBackPorch));
1267
1268     IFPRINT(platform_write("%s: displayType-%d\n\n",__FUNCTION__, dispCfg.displayType));
1269     IFPRINT(platform_write("%s: colorMode-%d\n\n",__FUNCTION__, dispCfg.colorMode));
1270     IFPRINT(platform_write("%s: dataLines-%d\n\n",__FUNCTION__, dispCfg.dataLines));
1271     IFPRINT(platform_write("%s: mono8Bit-%d\n\n",__FUNCTION__, dispCfg.mono8Bit));
1272
1273     IFPRINT(platform_write("%s: hsyncPolarity-%d\n\n",__FUNCTION__, tmgCfg.hsyncPolarity));
1274     IFPRINT(platform_write("%s: vsyncPolarity-%d\n\n",__FUNCTION__, tmgCfg.vsyncPolarity));
1275     IFPRINT(platform_write("%s: syncEdge-%d\n\n",__FUNCTION__, tmgCfg.syncEdge));
1276     IFPRINT(platform_write("%s: syncEdgeCtrl-%d\n\n",__FUNCTION__, tmgCfg.syncEdgeCtrl));
1277     IFPRINT(platform_write("%s: pclkPolarity-%d\n\n",__FUNCTION__, tmgCfg.pclkPolarity));
1278     IFPRINT(platform_write("%s: acbFrequency-%d\n\n",__FUNCTION__, tmgCfg.acbFrequency));
1279     IFPRINT(platform_write("%s: acbi-%d\n\n",__FUNCTION__, tmgCfg.acbi));
1280     IFPRINT(platform_write("%s: hsyncGated-%d\n\n",__FUNCTION__, tmgCfg.hsyncGated));
1281     IFPRINT(platform_write("%s: vsyncGated-%d\n\n",__FUNCTION__, tmgCfg.vsyncGated));
1282     IFPRINT(platform_write("%s: acbGated-%d\n\n",__FUNCTION__, tmgCfg.acbGated));
1283     IFPRINT(platform_write("%s: pixelClkGated-%d\n\n",__FUNCTION__, tmgCfg.pixelClkGated));
1284
1285     IFPRINT(platform_write("%s: fifoLoThr-%d\n\n",__FUNCTION__, vidDmaCfg.fifoLoThr));
1286     IFPRINT(platform_write("%s: fifoHiThr-%d\n\n",__FUNCTION__, vidDmaCfg.fifoHiThr));
1287     IFPRINT(platform_write("%s: pixelInc-%d\n\n",__FUNCTION__, vidDmaCfg.pixelInc));
1288     IFPRINT(platform_write("%s: rowInc-%d\n\n",__FUNCTION__, vidDmaCfg.rowInc));
1289     IFPRINT(platform_write("%s: preloadSelect-%d\n\n",__FUNCTION__, vidDmaCfg.preloadSelect));
1290     IFPRINT(platform_write("%s: mflagLoThr-%d\n\n",__FUNCTION__, vidDmaCfg.mflagLoThr));
1291     IFPRINT(platform_write("%s: mflagHiThr-%d\n\n",__FUNCTION__, vidDmaCfg.mflagHiThr));
1292     IFPRINT(platform_write("%s: mflagAttrControl-%d\n\n",__FUNCTION__, vidDmaCfg.mflagAttrControl));
1293     IFPRINT(platform_write("%s: mflagAttrStart-%d\n\n",__FUNCTION__, vidDmaCfg.mflagAttrStart));
1294     IFPRINT(platform_write("%s: dssInitiatorPri_Hi-%d\n\n",__FUNCTION__, vidDmaCfg.dssInitiatorPri_Hi));
1295     IFPRINT(platform_write("%s: dssInitiatorPri_Lo-%d\n\n",__FUNCTION__, vidDmaCfg.dssInitiatorPri_Lo));
1296
1297         baseAddr = DSS_DISPC_BASE_ADDRESS;
1298         IFPRINT(platform_write("%s (line%d): Base Address = 0x%x\n", __FUNCTION__, __LINE__, baseAddr));
1299
1300         /*Bit 1 is softreset*/
1301         value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG);
1302         IFPRINT(platform_write("%s (line%d): Value at (DISPC_SYSCONFIG-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG) , value));
1303
1304         /*Bit 0 is module reset complete*/
1305         value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSSTATUS);
1306         IFPRINT(platform_write("%s (line%d): Value at (DISPC_SYSSTATUS-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSCOMMON_DISPC_SYSSTATUS), value));
1307
1308         value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE);
1309         IFPRINT(platform_write("%s (line%d): Value at (DISPC_GLOBAL_MFLAG_ATTRIBUTE-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE), value));
1310
1311         value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_SET);
1312         IFPRINT(platform_write("%s (line%d): Value at (DISPC_IRQENABLE_SET-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_SET), value));
1313
1314         baseAddr = DSS_VID_BASE_ADDRESS;
1315         IFPRINT(platform_write("%s (line%d): Base Address = 0x%x\n", __FUNCTION__, __LINE__, baseAddr));
1316
1317         value = reg_rd_32(baseAddr + CSL_DSSVID_MFLAG_THRESHOLD);
1318         IFPRINT(platform_write("%s (line%d): Value at (MFLAG_THRESHOLD-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_MFLAG_THRESHOLD), value));
1319
1320         value = reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
1321         IFPRINT(platform_write("%s (line%d): Value at (ATTRIBUTES-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_ATTRIBUTES), value));
1322
1323         value = reg_rd_32(baseAddr + CSL_DSSVID_BA(0));
1324         IFPRINT(platform_write("%s (line%d): Value at (DSSVID_BA(0)-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_BA(0)), value));
1325
1326         value = reg_rd_32(baseAddr + CSL_DSSVID_BA(1));
1327         IFPRINT(platform_write("%s (line%d): Value at (DSSVID_BA(1)-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_BA(1)), value));
1328
1329         value = reg_rd_32(baseAddr + CSL_DSSVID_POSITION);
1330         IFPRINT(platform_write("%s (line%d): Value at (VID_POSITION-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_POSITION), value));
1331
1332         value = reg_rd_32(baseAddr + CSL_DSSVID_PICTURE_SIZE);
1333         IFPRINT(platform_write("%s (line%d): Value at (VID_PICTURE_SIZE-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_PICTURE_SIZE), value));
1334
1335         value = reg_rd_32(baseAddr + CSL_DSSVID_IRQENABLE);
1336         IFPRINT(platform_write("%s (line%d): Value at (VID_IRQENABLE-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_IRQENABLE), value));
1337
1338         value = reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
1339         IFPRINT(platform_write("%s (line%d): Value at (ATTRIBUTES-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_ATTRIBUTES), value));
1340
1341         baseAddr = DSS_VP_BASE_ADDRESS;
1342         IFPRINT(platform_write("%s (line%d): Base Address = 0x%x\n", __FUNCTION__, __LINE__, baseAddr));
1343
1344         value = reg_rd_32(baseAddr + CSL_DSSVP_SIZE_SCREEN);
1345         IFPRINT(platform_write("%s (line%d): Value at (VP_SIZE_SCREEN-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_SIZE_SCREEN), value));
1346
1347         value = reg_rd_32(baseAddr + CSL_DSSVP_TIMING_H);
1348         IFPRINT(platform_write("%s (line%d): Value at (VP_TIMING_H-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_TIMING_H), value));
1349
1350         value = reg_rd_32(baseAddr + CSL_DSSVP_TIMING_V);
1351         IFPRINT(platform_write("%s (line%d): Value at (VP_TIMING_V-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_TIMING_V), value));
1352
1353         value = reg_rd_32(baseAddr + CSL_DSSVP_POL_FREQ);
1354         IFPRINT(platform_write("%s (line%d): Value at (VP_POL_FREQ-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_POL_FREQ), value));
1355
1356         value = reg_rd_32(baseAddr + CSL_DSSVP_IRQSTATUS);
1357         IFPRINT(platform_write("%s (line%d): Value at (VP_IRQSTATUS-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_IRQSTATUS), value));
1358
1359         value = reg_rd_32(baseAddr + CSL_DSSVP_IRQENABLE);
1360         IFPRINT(platform_write("%s (line%d): Value at (VP_IRQENABLE-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_IRQENABLE), value));
1361
1362         value = reg_rd_32(baseAddr + CSL_DSSVP_CONTROL);
1363         IFPRINT(platform_write("%s (line%d): Value at (VP_CONTROL-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_CONTROL), value));
1364
1365         baseAddr = DSS_BASE_ADDRESS;
1366         IFPRINT(platform_write("%s (line%d): Base Address = 0x%x\n", __FUNCTION__, __LINE__, baseAddr));
1367
1368         value = reg_rd_32(baseAddr + CSL_DSS_DSS_DPI_CTRL);
1369         IFPRINT(platform_write("%s (line%d): Value at (DSS_DSS_DPI_CTRL-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSS_DSS_DPI_CTRL), value));
1370
1371 }
1372 #endif
1373 /**
1374  *  \brief    DSS Initialization
1375  *
1376  *  This function initializes the DSS module with the given LCD panel
1377  *  information, Timing configuration, Display configuration and DMA
1378  *  configuration.
1379  *
1380  *  \param    dssInfo    [IN]   dssInfo structure passed from LCD panel init
1381  *
1382  *  \return
1383  *           DSS_RET_OK -    status to indicate success
1384  *           DSS_RET_FAILED - if DSS failed to initialize, returns failure.
1385  *
1386  */
1387 DSS_RET dssInit(dssInfo_t *dssInfo)
1388 {
1389     lcdCfg_t  lcdCfg;
1390     dispCfg_t dispCfg;
1391     tmgCfg_t  tmgCfg;
1392     dmaCfg_t  vidDmaCfg;
1393     DSS_RET     status = DSS_RET_FAILED;
1394
1395     lcdCfg = dssInfo->lcdCfg;
1396     dispCfg = dssInfo->dispCfg;
1397     tmgCfg = dssInfo->tmgCfg;
1398     vidDmaCfg = dssInfo->vidDmaCfg;
1399
1400     /* Erase the frame buffer */
1401     dssEraseBuffer(&lcdCfg);
1402
1403     /* Initialize Frame Buffer */
1404     dssInitFrameBuffer(RGB888_ADDRESS, lcdCfg.LcdWidth, lcdCfg.LcdHeight);
1405
1406     /* Perform soft reset of DISPC module*/
1407     dssDispcSoftReset(DSS_DISPC_BASE_ADDRESS);
1408
1409     /* Enable auto-idle */
1410     dssDispcAutoIdleEnableCtrl(DSS_DISPC_BASE_ADDRESS, ENABLE);
1411
1412     status = dssInitiatorPriorityCfg (CSL_BOOT_CFG_REGS, vidDmaCfg.dssInitiatorPri_Lo, vidDmaCfg.dssInitiatorPri_Hi);
1413     if (status == DSS_RET_FAILED)
1414     {
1415         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
1416         return status;
1417     }
1418
1419     status = dssDispcMflagAttributeCfg(DSS_DISPC_BASE_ADDRESS, vidDmaCfg.mflagAttrStart, vidDmaCfg.mflagAttrControl);
1420     if (status == DSS_RET_FAILED)
1421     {
1422         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
1423         return status;
1424     }
1425
1426     status = dssDispcMflagThresholdCfg(DSS_VID_BASE_ADDRESS, vidDmaCfg.mflagLoThr, vidDmaCfg.mflagHiThr);
1427
1428     if (status == DSS_RET_FAILED)
1429     {
1430         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
1431         return status;
1432     }
1433
1434     /* Configure video pipeline DMA parameters*/
1435     status = dssDispcVidDMAConfig(DSS_VID_BASE_ADDRESS, &vidDmaCfg);
1436     if (status == DSS_RET_FAILED)
1437     {
1438         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
1439         return status;
1440     }
1441
1442     /* Configure VID arbitration priority */
1443     dssDispcVidPrioritySet(DSS_VID_BASE_ADDRESS, DSS_DISPC_VID_PRIORITY_HIGH);
1444
1445     /* Disable self refresh */
1446     dssDispcVidSelfRefEnableCtrl(DSS_VID_BASE_ADDRESS, DISABLE);
1447
1448     /* Configure frame buffer base address */
1449     dssDispcVidSetBufAddr(DSS_VID_BASE_ADDRESS, /*&frameBuffer*/((Uint32)pFrameBuffer), DSS_DISPC_VID_BUFFER0);
1450
1451     /* Configure position of the video window */
1452     status = dssDispcVidOvlyPositionCfg(DSS_VID_BASE_ADDRESS, 0, 0);
1453     if (status == DSS_RET_FAILED)
1454     {
1455         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
1456         return status;
1457     }
1458
1459     /* Configure video window size */
1460     status = dssDispcVidSizeCfg(DSS_VID_BASE_ADDRESS, lcdCfg.LcdWidth, lcdCfg.LcdHeight);
1461     if (status == DSS_RET_FAILED)
1462     {
1463         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
1464         return status;
1465     }
1466
1467     /* Configure Vid data format */
1468     dssDispcVidFormatSet(DSS_VID_BASE_ADDRESS, DSS_DISPC_VID_FMT_ABGR32U, DSS_DISPC_VID_NIBBLE_MODE_DISABLE);
1469
1470     /* Configure LCD color attributes */
1471     status = dssDispcLcdDisplayAttribCfg(DSS_VP_BASE_ADDRESS, &dispCfg);
1472     if (status == DSS_RET_FAILED)
1473     {
1474         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
1475         return status;
1476     }
1477
1478     /* Configure LCD panel timing parameters */
1479     status = dssDispcLcdPanelCfg(DSS_VP_BASE_ADDRESS, &lcdCfg);
1480     if (status == DSS_RET_FAILED)
1481     {
1482         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
1483         return status;
1484     }
1485
1486     /* Configure LCD control signal polarities */
1487     status = dssDispcLcdTimingCfg(DSS_VP_BASE_ADDRESS, &tmgCfg);
1488     if (status == DSS_RET_FAILED)
1489     {
1490         IFPRINT(platform_write("ERROR %s: Line%d\n", __FUNCTION__, __LINE__));
1491         return status;
1492     }
1493
1494     /* Clear status of all the interrupts */
1495     dssDispcIntStatusClearEx(DSS_VP_BASE_ADDRESS, 0x1FFFF);
1496
1497     /* Configure the programmable line number which generates interrupt */
1498 //  dssDispcProgLineNumberSet(CSL_DSSUL_0_CFG_REGS, DSS_PROG_LINE_NUMBER);  //This can be used for future testing if necessary
1499
1500     /* Enable the DPI interface */
1501     dssDpiCtrl(DSS_BASE_ADDRESS, ENABLE);
1502
1503     /* Enable interrupts to the VID and VP pipelines */
1504     dssDispcCommonIntEnable(DSS_DISPC_BASE_ADDRESS, CSL_DSSCOMMON_DISPC_IRQENABLE_SET_SET_VID1_IRQ_MASK | CSL_DSSCOMMON_DISPC_IRQENABLE_SET_SET_VP1_IRQ_MASK);
1505
1506     /* Enable the Frame Done interrupt */
1507     dssDispcVPIntEnable(DSS_VP_BASE_ADDRESS, CSL_DSSVP_IRQENABLE_VPFRAMEDONE_EN_MASK);
1508
1509     /* Enable VID1 buffer underflow and end of window interrupts */
1510     dssDispcVidIntEnable(DSS_VID_BASE_ADDRESS, CSL_DSSVID_IRQENABLE_VIDBUFFERUNDERFLOW_EN_GENINT | CSL_DSSVID_IRQENABLE_VIDENDWINDOW_EN_GENINT);
1511
1512     /* Enable VID1 pipeline */
1513     dssDispcVidEnableCtrl(DSS_VID_BASE_ADDRESS, TRUE);
1514
1515     /* Set the GO bit */
1516     dssDispcShadowCfgEnable(DSS_VP_BASE_ADDRESS);
1517
1518     /* Enable LCD output */
1519     dssDispcLcdOutputEnableCtrl(DSS_VP_BASE_ADDRESS, ENABLE);
1520
1521     return status;
1522 }
1523
1524 #endif /* #if (PLATFORM_DSS_IN) */
1525
1526 /* Nothing past this point */