psdk_cust/pdk_k2g_1_0_1_1_eng/packages/ti/board/diag/hdmi/src/evmk2g_dss.c

   1 /*
   2  * Copyright (c) 2016, Texas Instruments Incorporated
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * *  Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  * *  Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * *  Neither the name of Texas Instruments Incorporated nor the names of
  17  *    its contributors may be used to endorse or promote products derived
  18  *    from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  24  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  27  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  28  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  29  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  */
  33
  34 /**
  35  *
  36  *  \file  evmk2g_dss.c
  37  *
  38  *  \brief This file contains DSS specific functions.
  39  *
  40  ******************************************************************************/
  41
  42 #include "platform_internal.h"
  43 #ifdef DISPLAY_LOGO
  44 #include "ti_logo.h"
  45 #endif
  46 #if (PLATFORM_DSS_IN)
  47
  48 volatile Uint32 *pFrameBuffer = (volatile Uint32 *)(DDR_FRAME_ADDRESS_START);
  49 volatile Uint32 count = 0;
  50 volatile Uint32 count_underflow[11];
  51 volatile Uint32 uf_index = 0;
  52
  53 #define ENABLE        (1)
  54 #define DISABLE       (0)
  55
  56 /**
  57  *  \brief    Writes 32 bit value to a register/memory
  58  *
  59  *  This function write a given 32 bit data to the passed address.
  60  *  This function is mainly used to configure the registers of DSS
  61  *
  62  *  \param    baseAddr   [IN]   Base address
  63  *  \param    writeData [IN]   write data to be written to the address.
  64  *
  65  *  \return    - NONE
  66  */
  67 static void reg_wr_32(Uint32 baseAddr,Uint32 writeData)
  68 {
  69   (*(Uint32 *) (baseAddr)) = writeData;
  70 }
  71
  72 /**
  73  *  \brief    Read 32 bit value from a register/memory
  74  *
  75  *  This function reads a 32 bit data from the given address.
  76  *  This function is mainly used to validate/read the status of the DSS
  77  *  registers.
  78  *
  79  *  \param    baseAddr   [IN]   Base address
  80  *
  81  *  \return    - read_data - 32 bit value read from the address
  82  */
  83 static Uint32 reg_rd_32(Uint32 baseAddr)
  84 {
  85   Uint32 read_data;
  86   read_data = (*(Uint32 *) (baseAddr));
  87   return read_data;
  88 }
  89
  90 /**
  91  *  \brief    Puts the given color to the frame buffer
  92  *
  93  *  This function puts the color passed as parameter to the
  94  *  frame buffer to display the given color. This function is
  95  *  used to test the LCD, frame buffer by passing any desired
  96  *  color.
  97  *
  98  *  \param    plcdCfg   [IN]   pointer to lcdCfg to get height and width
  99  *  \param    color     [IN]   color to be displayed on the Display panel
 100  *
 101  *  \return   NONE
 102  */
 103 void dssFrameBufferColor(lcdCfg_t *plcdCfg, Uint32 color)
 104 {
 105   unsigned int x,y;
 106
 107   for (y = 0; y < plcdCfg->LcdHeight; y++)
 108     for (x = 0; x < plcdCfg->LcdWidth; x++)
 109         *(pFrameBuffer + (y * plcdCfg->LcdWidth) + (x) ) = color;
 110
 111 }
 112
 113 /**
 114  *  \brief    Puts the given pic array to the frame buffer
 115  *
 116  *  This function puts the array passed as parameter to the
 117  *  frame buffer to display the given image.
 118  *
 119  *  \param    plcdCfg   [IN]   pointer to lcdCfg to get height and width
 120  *  \param    array     [IN]   array to be displayed on the Display panel
 121  *
 122  *  \return   NONE
 123  */
 124 #ifdef DISPLAY_LOGO
 125 void dssFillFrameBuffer(void)
 126 {
 127         memcpy(TI_logo_rgb32,(const void *) 0x88000000, sizeof(TI_logo_rgb32));
 128 }
 129 #endif
 130
 131 /**
 132  *  \brief    Initialize the Frame buffer
 133  *
 134  *  This function performs initialization of frame buffer, loading of color bar
 135  *  information to the frame buffer or loading a constant value to the frame
 136  *  buffer.
 137  *
 138  *  \param    mode   [IN]   mode of operation for frame buffer
 139  *  \param    height [IN]   height of the frame buffer
 140  *  \param    width  [IN]   width of the frame buffer
 141  *
 142  *  \return   NONE
 143  */
 144 void dssInitFrameBuffer(Uint32 mode, Uint32 width, Uint32 height) {
 145
 146     Uint32 i = 0;
 147     Uint32 j = 0;
 148     Uint32 count = 0;
 149     Uint32 secondCount = 0;
 150     Uint32 currentColor = RED;
 151
 152     switch (mode) {
 153         case RGB888_CONSTANT:
 154             for (j = 0; j < (height * width); j++) {
 155                 *(pFrameBuffer + j) = 0xAAAAAA;
 156             }
 157             break;
 158         case RGB888_GENERATE:
 159             for(i = 0; i < (height * width); i++){
 160                 if ((i % width) == 0) {
 161                     count = count + 1;
 162                 }
 163                 if (count == height/6) {
 164                     count = 0;
 165                     secondCount = secondCount + 1;
 166                     if (secondCount == 1){
 167                         currentColor = GREEN;
 168                     }
 169                     else if (secondCount == 2){
 170                         currentColor = BLUE;
 171                     }
 172                     else if (secondCount == 3){
 173                         currentColor = PURPLE;
 174                     }
 175                     else if (secondCount == 4){
 176                         currentColor = YELLOW;
 177                     }
 178                     else if (secondCount == 5){
 179                         currentColor = PINK;
 180                     }
 181                 }
 182                 *(pFrameBuffer + i) = currentColor;
 183             }
 184
 185             break;
 186         case RGB888_ADDRESS:
 187             for (j = 0; j < (height * width); j++) {
 188                 *(pFrameBuffer + j) = (0x88000000+(j*4));
 189             }
 190             break;
 191         default:
 192             break;
 193     }
 194 }
 195
 196 /**
 197  *  \brief    Configures DISPC_GLOBAL_MFLAG_ATTRIBUTE Register
 198  *
 199  *  This function configures the Mflag attribute configuratin
 200  *
 201  *  \param    baseAddr   [IN]   base address of DSSUL Common cfg register
 202  *  \param    start      [IN]   value of MFlag START to be configured
 203  *  \param    control    [IN]   value of MFlag control to be configured
 204  *
 205  *  \return
 206  *           DSS_RET_OK - if configuration is success
 207  *           DSS_RET_FAILED - if configuration is failed
 208  *
 209  */
 210 DSS_RET dssDispcMflagAttributeCfg(Uint32 baseAddr, Uint32 start, Uint32 control)
 211 {
 212     DSS_RET status = DSS_RET_FAILED;
 213     Uint32 value = 0;
 214     Uint32 value_start = 0;
 215     Uint32 value_control = 0;
 216
 217     value_start = ((start << \
 218            CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_SHIFT) \
 219         & (CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK));
 220
 221     if ((start == CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MFLAGNORMALSTARTMODE) ||
 222         (start == CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MFLAGFORCESTARTMODE))
 223     {
 224         value_start = start;
 225         status = DSS_RET_OK;
 226     }
 227
 228     value_control = ((control << CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_SHIFT) \
 229                       & (CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK));
 230     if ((control == CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MFLAGDIS) || \
 231         (control == CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MFLAGFORCE) ||\
 232         (control == CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MFLAGEN))
 233     {
 234         value_control = control;
 235         status = DSS_RET_OK;
 236     }
 237
 238     if (status == DSS_RET_OK)
 239     {
 240         value = value_start | value_control;
 241         reg_wr_32(baseAddr + CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE, value);
 242     }
 243     return status;
 244 }
 245
 246 /**
 247  *  \brief    Configures DISPC_GLOBAL_MFLAG_ATTRIBUTE Register
 248  *
 249  *  This function configures the Mflag attribute configuratin
 250  *
 251  *  \param    baseAddr     [IN]   base address of DSSUL Video config register
 252  *  \param    lo_threshold [IN]   value of low threshold
 253  *  \param    hi_threshold [IN]   value of high threshold
 254  *
 255  *  \return
 256  *           DSS_RET_OK - if configuration is success
 257  *           DSS_RET_FAILED - if configuration is failed
 258  */
 259 DSS_RET dssDispcMflagThresholdCfg(Uint32 baseAddr,
 260                                   Uint32 lo_threshold,
 261                                   Uint32 hi_threshold)
 262 {
 263     DSS_RET status = DSS_RET_OK;
 264     Uint32 value = 0;
 265
 266     if ((lo_threshold > CSL_DSSVID_MFLAG_THRESHOLD_LT_MFLAG_MAX) ||
 267        (hi_threshold > CSL_DSSVID_MFLAG_THRESHOLD_HT_MFLAG_MAX))
 268     {
 269                 IFPRINT(UART_printf("ERROR %s: Invalid values for \
 270                                                                 thresholds\n", __FUNCTION__));
 271         status = DSS_RET_FAILED;
 272     }
 273     else
 274     {
 275         /* Program X position */
 276         value = ((lo_threshold << CSL_DSSVID_MFLAG_THRESHOLD_LT_MFLAG_SHIFT) &
 277             (CSL_DSSVID_MFLAG_THRESHOLD_LT_MFLAG_MASK));
 278         /* Program Y position */
 279         value |= ((hi_threshold << CSL_DSSVID_MFLAG_THRESHOLD_HT_MFLAG_SHIFT) &
 280             (CSL_DSSVID_MFLAG_THRESHOLD_HT_MFLAG_MASK));
 281         reg_wr_32(baseAddr + CSL_DSSVID_MFLAG_THRESHOLD, value);
 282     }
 283
 284     return status;
 285 }
 286
 287 /**
 288  *  \brief    Configures the DSS initiator priority
 289  *
 290  *  This function configures the DSS Initiator priority
 291  *
 292  *  \param    baseAddr      [IN]   base address of DSSUL Video config register
 293  *  \param    lo_priority   [IN]   value of low priority
 294  *  \param    hi_priority   [IN]   value of high priority
 295  *
 296  *  \return
 297  *           DSS_RET_OK - if configuration is success
 298  *           DSS_RET_FAILED - if configuration is failed
 299  */
 300 DSS_RET dssInitiatorPriorityCfg(Uint32 baseAddr, Uint32 lo_priority,
 301                                 Uint32 hi_priority)
 302 {
 303     DSS_RET status = DSS_RET_OK;
 304     Uint32 value = 0;
 305
 306     reg_wr_32(KICK0_BASE_ADDRESS, KICK0_UNLOCK);
 307     reg_wr_32(KICK1_BASE_ADDRESS, KICK1_UNLOCK);
 308
 309     if (hi_priority > 0x1) {
 310                 IFPRINT (UART_printf("Warning: DSS initiator hi priority is being \
 311                                                                 set to greater than 0x1 \n"));
 312         }
 313
 314     if ((lo_priority > 0x7) || (hi_priority > 0x7)) {
 315         status = DSS_RET_FAILED;
 316                 IFPRINT (UART_printf("DSS initiator priority cannot be greater than\
 317                                                                 0x7\n"));
 318     }
 319     else {
 320         /* Program dss_pri_lo of DSS in Initiator Priority Control Register 1 */
 321         value = ((lo_priority << DSS_INITIATOR_LOPRI_SHIFT) & (DSS_INITIATOR_LOPRI_MASK));
 322         /* Program dss_pri_hi of DSS in Initiator Priority Control Register 1 */
 323         value |= ((hi_priority << DSS_INITIATOR_HIPRI_SHIFT) & (DSS_INITIATOR_HIPRI_MASK));
 324         reg_wr_32(baseAddr + INITIATOR_PRIORITY_1_OFFSET, value);
 325     }
 326     return status ;
 327 }
 328
 329 /**
 330  *  \brief    Configures panel specific timing parameters
 331  *
 332  *  This function configures the DSS Initiator priority
 333  *
 334  *  \param    baseAddr  [IN]   base address of DSSUL Video port register
 335  *  \param    pLcdCfg   [IN]   pointer to LCD configuration
 336  *
 337  *  \return
 338  *           DSS_RET_OK - if configuration is success
 339  *           DSS_RET_FAILED - if configuration is failed
 340  */
 341 DSS_RET dssDispcLcdPanelCfg(Uint32 baseAddr, lcdCfg_t *pLcdCfg)
 342 {
 343     Uint32 value = 0;
 344     DSS_RET status = DSS_RET_OK;
 345
 346     if (pLcdCfg == NULL)
 347     {
 348                 IFPRINT(UART_printf("ERROR %s: LCD configuration \
 349                                                                 pointer is NULL\n", __FUNCTION__));
 350         return DSS_RET_FAILED;
 351     }
 352
 353     /* Program pixels per line */
 354     value = (((pLcdCfg->LcdWidth - 1U) <<
 355               CSL_DSSVP_SIZE_SCREEN_PPL_SHIFT) &
 356               (CSL_DSSVP_SIZE_SCREEN_PPL_MASK));
 357
 358     /* Program lines per panel */
 359     value |= (((pLcdCfg->LcdHeight - 1U) <<
 360                CSL_DSSVP_SIZE_SCREEN_LPP_SHIFT) &
 361               (CSL_DSSVP_SIZE_SCREEN_LPP_MASK));
 362
 363     reg_wr_32(baseAddr + CSL_DSSVP_SIZE_SCREEN, value);
 364
 365     /* Program hsw value */
 366     value = (((pLcdCfg->HsyncWidth - 1U) << CSL_DSSVP_TIMING_H_HSW_SHIFT) &
 367         (CSL_DSSVP_TIMING_H_HSW_MASK));
 368
 369     /* Program hfp value */
 370     value |= (((pLcdCfg->HFrontPorch - 1U) << CSL_DSSVP_TIMING_H_HFP_SHIFT) &
 371         (CSL_DSSVP_TIMING_H_HFP_MASK));
 372
 373     /* Program hbp value */
 374     value |= (((pLcdCfg->HBackPorch - 1U) << CSL_DSSVP_TIMING_H_HBP_SHIFT) &
 375         (CSL_DSSVP_TIMING_H_HBP_MASK));
 376     reg_wr_32(baseAddr + CSL_DSSVP_TIMING_H, value);
 377
 378     /* Program vsw value */
 379     value = (((pLcdCfg->VsyncWidth - 1U) << CSL_DSSVP_TIMING_V_VSW_SHIFT) &
 380         (CSL_DSSVP_TIMING_V_VSW_MASK));
 381
 382     /* Program hfp value */
 383     value |= ((pLcdCfg->VFrontPorch << CSL_DSSVP_TIMING_V_VFP_SHIFT) &
 384         (CSL_DSSVP_TIMING_V_VFP_MASK));
 385
 386     /* Program hbp value */
 387     value |= ((pLcdCfg->VBackPorch << CSL_DSSVP_TIMING_V_VBP_SHIFT) &
 388         (CSL_DSSVP_TIMING_V_VBP_MASK));
 389     reg_wr_32(baseAddr + CSL_DSSVP_TIMING_V, value);
 390
 391     return status;
 392 }
 393
 394 /**
 395  *  \brief    Configures LCD color attributes
 396  *
 397  *  This function configures the LCD color attributes
 398  *
 399  *  \param    baseAddr   [IN]   base address of DSSUL Video port register
 400  *  \param    pDispCfg   [IN]   pointer to LCD configuration
 401  *
 402  *  \return
 403  *           DSS_RET_OK - if configuration is success
 404  *           DSS_RET_FAILED - if configuration is failed
 405  */
 406 DSS_RET dssDispcLcdDisplayAttribCfg(Uint32 baseAddr,
 407                                    dispCfg_t *pDispCfg)
 408 {
 409     DSS_RET status = DSS_RET_OK;
 410     Uint32 value  = 0;
 411
 412     /* Clear display type, monoColor, data lines, mono8bit fields */
 413     value = reg_rd_32(baseAddr + CSL_DSSVP_CONTROL);
 414
 415     value &= (~(CSL_DSSVP_CONTROL_STN_MASK | CSL_DSSVP_CONTROL_MONOCOLOR_MASK |
 416             CSL_DSSVP_CONTROL_VPPROGLINENUMBERMODULO_MASK | CSL_DSSVP_CONTROL_M8B_MASK));
 417
 418     if (NULL != pDispCfg)
 419     {
 420         /* Configure LCD Data Lines */
 421         value |= ((pDispCfg->dataLines << CSL_DSSVP_CONTROL_DATALINES_SHIFT) &
 422                     (CSL_DSSVP_CONTROL_DATALINES_MASK));
 423
 424         /* Configure passive matrix display specific parameters */
 425         if(DSS_LCD_TYPE_PASSIVE == pDispCfg->displayType)
 426         {
 427             /* Configure Color or Monochrome */
 428             value |= ((pDispCfg->colorMode << CSL_DSSVP_CONTROL_MONOCOLOR_SHIFT) &
 429                 (CSL_DSSVP_CONTROL_MONOCOLOR_MASK));
 430             /* Configure Mono8 or Mono4 bit */
 431             if(DSS_LCD_DISPLAY_MONO == pDispCfg->colorMode)
 432             {
 433                 value |= ((pDispCfg->mono8Bit << CSL_DSSVP_CONTROL_M8B_SHIFT) &
 434                     (CSL_DSSVP_CONTROL_M8B_MASK));
 435             }
 436         }
 437         reg_wr_32(baseAddr + CSL_DSSVP_CONTROL, value);
 438     }
 439     else
 440     {
 441                 IFPRINT(UART_printf("ERROR %s: LCD configuration \
 442                                                                 pointer is NULL\n", __FUNCTION__));
 443         status = DSS_RET_FAILED;
 444     }
 445
 446     return status;
 447 }
 448
 449 /**
 450  *  \brief    Configures control signal polarities
 451  *
 452  *  This function configures the control signal polarities
 453  *
 454  *  \param    baseAddr   [IN]   base address of DSSUL Video port register
 455  *  \param    pTmgCfg   [IN]   pointer to timing configuration
 456  *
 457  *  \return
 458  *           DSS_RET_OK - if configuration is success
 459  *           DSS_RET_FAILED - if configuration is failed
 460  */
 461 DSS_RET dssDispcLcdTimingCfg(Uint32 baseAddr,
 462                             tmgCfg_t *pTmgCfg)
 463 {
 464     DSS_RET status = DSS_RET_OK;
 465     Uint32 value = 0;
 466
 467     //reg_wr_32(baseAddr + CSL_DSSVP_POL_FREQ, 0x4000);
 468     if (NULL != pTmgCfg)
 469     {
 470         /* Program hsync polarity value */
 471         value = ((pTmgCfg->hsyncPolarity << CSL_DSSVP_POL_FREQ_IHS_SHIFT) &
 472             (CSL_DSSVP_POL_FREQ_IHS_MASK));
 473         /* Program vsync polarity value */
 474         value |= ((pTmgCfg->vsyncPolarity << CSL_DSSVP_POL_FREQ_IVS_SHIFT) &
 475             (CSL_DSSVP_POL_FREQ_IVS_MASK));
 476         /* Program sync edge type */
 477         value |= ((pTmgCfg->syncEdge << CSL_DSSVP_POL_FREQ_RF_SHIFT) &
 478             (CSL_DSSVP_POL_FREQ_RF_MASK));
 479         /* Program sync edge control */
 480         value |= ((pTmgCfg->syncEdgeCtrl << CSL_DSSVP_POL_FREQ_ONOFF_SHIFT) &
 481             (CSL_DSSVP_POL_FREQ_ONOFF_MASK));
 482         /* Program Output enable polarity */
 483         value |= ((pTmgCfg->outputEnablePolarity << CSL_DSSVP_POL_FREQ_IEO_SHIFT) &
 484             (CSL_DSSVP_POL_FREQ_IEO_MASK));
 485         /* program acb pin frequency */
 486         value |= ((pTmgCfg->acbFrequency << CSL_DSSVP_POL_FREQ_ACB_SHIFT) &
 487             (CSL_DSSVP_POL_FREQ_ACB_MASK));
 488         /* program acb pin transitions per interrupt */
 489         value |= ((pTmgCfg->acbi << CSL_DSSVP_POL_FREQ_ACBI_SHIFT) &
 490             (CSL_DSSVP_POL_FREQ_ACBI_MASK));
 491         /* program pixel clock polarity */
 492         value |= ((pTmgCfg->pclkPolarity << CSL_DSSVP_POL_FREQ_IPC_SHIFT) &
 493             (CSL_DSSVP_POL_FREQ_IPC_MASK));
 494         /* Write into the register */
 495         reg_wr_32(baseAddr + CSL_DSSVP_POL_FREQ, value);
 496
 497         /* Clear clock gated control for sync, acb and pixel clock */
 498         value = reg_rd_32(baseAddr + CSL_DSSVP_CONFIG);
 499         value &= (~(CSL_DSSVP_CONFIG_EXTERNALSYNCEN_MASK | CSL_DSSVP_CONFIG_HSYNCGATED_MASK |
 500                 CSL_DSSVP_CONFIG_VSYNCGATED_MASK | CSL_DSSVP_CONFIG_PIXELGATED_MASK));
 501
 502         /* Program hsync clock gated control */
 503         value |= ((pTmgCfg->hsyncGated << CSL_DSSVP_CONFIG_HSYNCGATED_SHIFT) &
 504             (CSL_DSSVP_CONFIG_HSYNCGATED_MASK));
 505         /* Program vsync clock gated control */
 506         value |= ((pTmgCfg->vsyncGated << CSL_DSSVP_CONFIG_VSYNCGATED_SHIFT) &
 507             (CSL_DSSVP_CONFIG_VSYNCGATED_MASK));
 508         /* Program acb clock gated control */
 509         value |= ((pTmgCfg->acbGated << CSL_DSSVP_CONFIG_EXTERNALSYNCEN_SHIFT) &   //No gated macro for ACBIAS, these should still work. Need to confirm
 510             (CSL_DSSVP_CONFIG_EXTERNALSYNCEN_MASK));
 511         /* Program pixel clock gated control */
 512         value |= ((pTmgCfg->pixelClkGated << CSL_DSSVP_CONFIG_PIXELCLOCKGATED_SHIFT) &
 513                 CSL_DSSVP_CONFIG_PIXELCLOCKGATED_MASK);
 514         reg_wr_32(baseAddr + CSL_DSSVP_CONFIG, value);
 515     }
 516     else
 517     {
 518                 IFPRINT(UART_printf("ERROR %s: Timing configuration \
 519                                                                 pointer is NULL\n", __FUNCTION__));
 520         status = DSS_RET_FAILED;
 521     }
 522     return status;
 523 }
 524
 525 /**
 526  *  \brief    Disables ST Dithering
 527  *
 528  *  This function Disables ST Dithering
 529  *
 530  *  \param    baseAddr   [IN]   base address of DSSUL register
 531  *
 532  *  \return
 533  *          NONE
 534  */
 535 void dssDispcSTDitheringDisable(Uint32 baseAddr)
 536 {
 537     Uint32 value = 0;
 538
 539     value = reg_rd_32(baseAddr + CSL_DSSVP_CONTROL) & (~CSL_DSSVP_CONTROL_STDITHERENABLE_MASK);
 540     reg_wr_32(baseAddr + CSL_DSSVP_CONTROL, value);
 541 }
 542
 543 /**
 544  *  \brief    Bypasses RFBI mode
 545  *
 546  *  This function bypasses RFBI mode
 547  *
 548  *  \param    baseAddr   [IN]   base address of DSSUL register
 549  *
 550  *  \return
 551  *          NONE
 552  */
 553 void dssDispcRfbiModeBypass(Uint32 baseAddr)
 554 {
 555     Uint32 value = 0;
 556
 557     value = reg_rd_32(baseAddr + CSL_DSSRFBI_RFBI_CONTROL);
 558
 559     value |= CSL_DSSRFBI_RFBI_CONTROL_BYPASSMODE_BYPASS;
 560     reg_wr_32(baseAddr + CSL_DSSRFBI_RFBI_CONTROL, value);
 561 }
 562
 563 /**
 564  *  \brief    Clear existing interrupts
 565  *
 566  *  This function clears the interrupt status
 567  *
 568  *  \param    baseAddr   [IN]   base address of DSSUL register
 569  *  \param    intFlag    [IN]   interrupt flag to be cleared
 570  *
 571  *  \return
 572  *          NONE
 573  */
 574 void dssDispcIntStatusClearEx(Uint32 baseAddr, Uint32 intFlag)
 575 {
 576     reg_wr_32(baseAddr + CSL_DSSVP_IRQSTATUS, intFlag);
 577 }
 578
 579 /**
 580  *  \brief    Configures the line number that generates interrupt
 581  *
 582  *  This function configures the line number that generates interrupt
 583  *
 584  *  \param    baseAddr   [IN]   base address of DSSUL register
 585  *  \param    lineNumber [IN]   line number that generates interrupt
 586  *
 587  *  \return
 588  *          NONE
 589  */
 590 void dssDispcProgLineNumberSet(Uint32 baseAddr, Uint32 lineNumber)
 591 {
 592     Uint32 value = 0;
 593
 594     /* Clear the line number field */
 595     value = reg_rd_32(baseAddr + CSL_DSSVP_LINE_NUMBER) & (~CSL_DSSVP_LINE_NUMBER_LINENUMBER_MASK);
 596
 597     /* Program the line number field */
 598     value |= ((lineNumber << CSL_DSSVP_LINE_NUMBER_LINENUMBER_SHIFT) & CSL_DSSVP_LINE_NUMBER_LINENUMBER_MASK);
 599     reg_wr_32(baseAddr + CSL_DSSVP_LINE_NUMBER, value);
 600 }
 601
 602 /**
 603  *  \brief    Enable/Disable DPI Control
 604  *
 605  *  This function enables/disables DPI interface from the registers
 606  *
 607  *  \param    baseAddr   [IN]   base address of DSSUL register
 608  *  \param    enableFlag [IN]   flag to indicate enable/disable
 609  *
 610  *  \return
 611  *          NONE
 612  */
 613 void dssDpiCtrl(Uint32 baseAddr,
 614                 Uint32 enableFlag)
 615 {
 616     Uint32 value = 0;
 617
 618     value = reg_rd_32(baseAddr + CSL_DSS_DSS_DPI_CTRL);
 619
 620     if (TRUE == enableFlag)
 621     {
 622         /* Enable DPI interface */
 623         value |= ((1 << CSL_DSS_DSS_DPI_CTRL_DPI_ENABLE_SHIFT) &
 624             (CSL_DSS_DSS_DPI_CTRL_DPI_ENABLE_MASK));
 625     }
 626     else
 627     {
 628         /* Disable DPI interface */
 629         value &= (~CSL_DSS_DSS_DPI_CTRL_DPI_ENABLE_MASK);
 630     }
 631     reg_wr_32(baseAddr + CSL_DSS_DSS_DPI_CTRL, value);
 632 }
 633
 634 /**
 635  *  \brief    Enable LCD output
 636  *
 637  *  This function enables/disables LCD output
 638  *
 639  *  \param    baseAddr   [IN]   base address of Video Port register
 640  *  \param    enableFlag [IN]   flag to indicate enable/disable
 641  *
 642  *  \return
 643  *          NONE
 644  */
 645 void dssDispcLcdOutputEnableCtrl(Uint32 baseAddr, Uint32 enableFlag)
 646 {
 647     Uint32 value = 0;
 648
 649     value = reg_rd_32(baseAddr + CSL_DSSVP_CONTROL);
 650
 651     if (TRUE == enableFlag)
 652     {
 653         /* Enable LCD output */
 654         value |= ((1 << CSL_DSSVP_CONTROL_LCDEN_SHIFT) &
 655             (CSL_DSSVP_CONTROL_LCDEN_MASK));
 656     }
 657     else
 658     {
 659         /* Disable LCD output */
 660         value &= (~CSL_DSSVP_CONTROL_LCDEN_MASK);
 661     }
 662     reg_wr_32(baseAddr + CSL_DSSVP_CONTROL, value);
 663 }
 664
 665 /**
 666  *  \brief    Performs software reset of the Display Controller
 667  *
 668  *  This function performs software reset of the display controller.
 669  *
 670  *  \param    baseAddr   [IN]   base address of Video Port register
 671  *
 672  *  \return
 673  *          NONE
 674  */
 675 void dssDispcSoftReset(Uint32 baseAddr)
 676 {
 677     Uint32 value = 0;
 678
 679     value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG);
 680
 681     value |= ((CSL_DSSCOMMON_DISPC_SYSCONFIG_SOFTRESET << CSL_DSSCOMMON_DISPC_SYSCONFIG_SOFTRESET_SHIFT) &
 682         (CSL_DSSCOMMON_DISPC_SYSCONFIG_SOFTRESET_MASK));
 683
 684     /* Performing Software Reset of the module */
 685     reg_wr_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG, value);
 686
 687     /* Wait until the process of Module Reset is complete */
 688     while(!((reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSSTATUS)) &
 689         (CSL_DSSCOMMON_DISPC_SYSSTATUS_DISPC_FUNC_RESETDONE_MASK)));
 690 }
 691
 692 /**
 693  *  \brief    Enable/Disable the auto-idle function
 694  *
 695  *  This function enables/disables the auto idle function of the Display
 696  *  controller
 697  *
 698  *  \param    baseAddr   [IN]   base address of Video Port register
 699  *  \param    enableFlag [IN]   flag to indicate enable/disable
 700  *
 701  *  \return
 702  *          NONE
 703  */
 704 void dssDispcAutoIdleEnableCtrl(Uint32 baseAddr, Uint32 enableFlag)
 705 {
 706     Uint32 value = 0;
 707
 708     value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG);
 709
 710     if (TRUE == enableFlag)
 711     {
 712         /* Enable auto idle mechanism */
 713         value |= ((CSL_DSSCOMMON_DISPC_SYSCONFIG_AUTOIDLE_CLKGATED <<
 714                 CSL_DSSCOMMON_DISPC_SYSCONFIG_AUTOIDLE_SHIFT) & (CSL_DSSCOMMON_DISPC_SYSCONFIG_AUTOIDLE_MASK));
 715     }
 716     else
 717     {
 718         /* Disable auto idle mechanism */
 719         value &= (~CSL_DSSCOMMON_DISPC_SYSCONFIG_AUTOIDLE_MASK);
 720     }
 721     reg_wr_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG, value);
 722 }
 723
 724 /**
 725  *  \brief    Configure video pipeline DMA specific parameters
 726  *
 727  *  This function configures video pipeline DMA specific parameters
 728  *
 729  *  \param    baseAddr   [IN]   base address of Video Port register
 730  *  \param    pDmaCfg    [IN]   pointer to DMA configuration
 731  *
 732  *  \return
 733  *           DSS_RET_OK - if configuration is success
 734  *           DSS_RET_FAILED - if configuration is failed
 735  */
 736 DSS_RET dssDispcVidDMAConfig(Uint32 baseAddr,
 737                             dmaCfg_t *pDmaCfg)
 738 {
 739     DSS_RET status = DSS_RET_OK;
 740     Uint32 cfgValue = 0;
 741
 742     if(NULL != pDmaCfg)
 743     {
 744         cfgValue = reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
 745
 746         /* Clear the burst size and preload select fields */
 747         cfgValue &= ~(CSL_DSSVID_ATTRIBUTES_BUFPRELOAD_MASK);
 748         /* Program the preload selection field */
 749         cfgValue |= ((pDmaCfg->preloadSelect <<
 750                 CSL_DSSVID_ATTRIBUTES_BUFPRELOAD_SHIFT) &
 751                 CSL_DSSVID_ATTRIBUTES_BUFPRELOAD_MASK);
 752         reg_wr_32(baseAddr + CSL_DSSVID_ATTRIBUTES, cfgValue);
 753
 754         /* program the low threshold field */
 755         cfgValue = ((pDmaCfg->fifoLoThr << CSL_DSSVID_BUF_THRESHOLD_BUFLOWTHRESHOLD_SHIFT) &
 756             (CSL_DSSVID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK));
 757         /* Program the high threshold field */
 758         cfgValue |= ((pDmaCfg->fifoHiThr << CSL_DSSVID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_SHIFT) &
 759             (CSL_DSSVID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK));
 760         reg_wr_32(baseAddr + CSL_DSSVID_BUF_THRESHOLD, cfgValue);
 761
 762         /* Program row increment value */
 763         cfgValue = ((pDmaCfg->rowInc << CSL_DSSVID_ROW_INC_ROWINC_SHIFT) &
 764                 CSL_DSSVID_ROW_INC_ROWINC_MASK);
 765         reg_wr_32(baseAddr + CSL_DSSVID_ROW_INC, cfgValue);
 766         /* Program pixel increment value */
 767         cfgValue = ((pDmaCfg->pixelInc << CSL_DSSVID_PIXEL_INC_PIXELINC_SHIFT) &
 768             (CSL_DSSVID_PIXEL_INC_PIXELINC_MASK));
 769         reg_wr_32(baseAddr + CSL_DSSVID_PIXEL_INC, cfgValue);
 770     }
 771     else
 772     {
 773                 IFPRINT(UART_printf("ERROR %s: DMA configuration \
 774                                                                 pointer is NULL\n", __FUNCTION__));
 775         status = DSS_RET_FAILED;
 776     }
 777
 778     return status;
 779 }
 780
 781 /**
 782  *  \brief    Video pipeline interrupt enable
 783  *
 784  *  This function enables video pipeline interrupt
 785  *
 786  *  \param    baseAddr [IN]   base address of Video pipeline register
 787  *  \param    intFlag  [IN]   interrupt flag to enable
 788  *
 789  *  \return
 790  *          NONE
 791  */
 792 void dssDispcVidIntEnable(Uint32 baseAddr, Uint32 intFlag)
 793 {
 794     Uint32 value = 0;
 795
 796     value = (reg_rd_32(baseAddr + CSL_DSSVID_IRQENABLE) | (intFlag));
 797     reg_wr_32(baseAddr + CSL_DSSVID_IRQENABLE, value);
 798 }
 799
 800 /**
 801  *  \brief    Video pipeline interrupt disable
 802  *
 803  *  This function disables video pipeline interrupt
 804  *
 805  *  \param    baseAddr [IN]   base address of Video pipeline register
 806  *  \param    intFlag  [IN]   interrupt flag to disable
 807  *
 808  *  \return
 809  *          NONE
 810  */
 811 void dssDispcVidIntDisable(Uint32 baseAddr, Uint32 intFlag)
 812 {
 813     Uint32 value = 0;
 814
 815     value = (reg_rd_32(baseAddr + CSL_DSSVID_IRQENABLE) & ~(intFlag));
 816     reg_wr_32(baseAddr + CSL_DSSVID_IRQENABLE, value);
 817 }
 818
 819 /**
 820  *  \brief    Enable the video pipeline
 821  *
 822  *  This function enables/disables the video pipeline
 823  *
 824  *  \param    baseAddr   [IN]   base address of Video Port register
 825  *  \param    enableFlag [IN]   flag to indicate enable/disable
 826  *
 827  *  \return
 828  *          NONE
 829  */
 830 void dssDispcVidEnableCtrl(Uint32 baseAddr,
 831                            Uint32 enableFlag)
 832 {
 833     Uint32 value = 0;
 834
 835     value = reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
 836     if(TRUE == enableFlag)
 837     {
 838         /* Enable video pipeline */
 839         value |= ((CSL_DSSVID_ATTRIBUTES_ENABLE_VIDEOENB << CSL_DSSVID_ATTRIBUTES_ENABLE_SHIFT) &
 840             (CSL_DSSVID_ATTRIBUTES_ENABLE_MASK));
 841     }
 842     else
 843     {
 844         /* Disable video pipeline */
 845         value &= (~CSL_DSSVID_ATTRIBUTES_ENABLE_MASK);
 846     }
 847     reg_wr_32(baseAddr + CSL_DSSVID_ATTRIBUTES, value);
 848 }
 849
 850 /**
 851  *  \brief    VP interrupt enable
 852  *
 853  *  This function enables VP interrupt
 854  *
 855  *  \param    baseAddr   [IN]   base address of Video Port register
 856  *  \param    intFlag    [IN]   interrupt flag to be enabled
 857  *
 858  *  \return
 859  *          NONE
 860  */
 861 void dssDispcVPIntEnable(Uint32 baseAddr, Uint32 intFlag)
 862 {
 863     Uint32 value = 0;
 864
 865     value = (reg_rd_32(baseAddr + CSL_DSSVP_IRQENABLE) | (intFlag));
 866     reg_wr_32(baseAddr + CSL_DSSVP_IRQENABLE, value);
 867 }
 868
 869 /**
 870  *  \brief    VP interrupt disable
 871  *
 872  *  This function disables VP interrupt
 873  *
 874  *  \param    baseAddr   [IN]   base address of Video Port register
 875  *  \param    intFlag    [IN]   interrupt flag to be disabled
 876  *
 877  *  \return
 878  *          NONE
 879  */
 880 void dssDispcVPIntDisable(Uint32 baseAddr, Uint32 intFlag)
 881 {
 882     Uint32 value = 0;
 883
 884     value = (reg_rd_32(baseAddr + CSL_DSSVP_IRQENABLE) & ~(intFlag));
 885     reg_wr_32(baseAddr + CSL_DSSVP_IRQENABLE, value);
 886 }
 887
 888 /**
 889  *  \brief    Enable interrupts to VID or VP
 890  *
 891  *  This function enables interrupts to VID or VP
 892  *
 893  *  \param    baseAddr   [IN]   base address of Video Port register
 894  *  \param    intFlag    [IN]   interrupt flag to be enabled
 895  *
 896  *  \return
 897  *          NONE
 898  */
 899 void dssDispcCommonIntEnable(Uint32 baseAddr,
 900                            Uint32 intFlag)
 901 {
 902     Uint32 value = 0;
 903
 904     value = (reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_SET) | (intFlag));
 905     reg_wr_32(baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_SET, value);
 906 }
 907
 908 /**
 909  *  \brief    Disable interrupts to VID or VP
 910  *
 911  *  This function disables interrupts to VID or VP
 912  *
 913  *  \param    baseAddr   [IN]   base address of Video Port register
 914  *  \param    intFlag    [IN]   interrupt flag to be disabled
 915  *
 916  *  \return
 917  *          NONE
 918  */
 919 void dssDispcCommonIntDisable(Uint32 baseAddr,
 920                            Uint32 intFlag)
 921 {
 922     Uint32 value = 0;
 923
 924     value = (reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_CLR) | (intFlag));
 925     reg_wr_32(baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_CLR, value);
 926 }
 927
 928 /**
 929  *  \brief    Update shadow registers, set the Go bit
 930  *
 931  *  This function updates shadow registers and sets the GO bit
 932  *
 933  *  \param    baseAddr   [IN]   base address of Video Port register
 934  *
 935  *  \return
 936  *          NONE
 937  */
 938 void dssDispcShadowCfgEnable(Uint32 baseAddr)
 939 {
 940     Uint32 value = 0;
 941
 942     /* Check to ensure that GOLCD bit is clear */
 943     while((reg_rd_32(baseAddr + CSL_DSSVP_CONTROL)) & (CSL_DSSVP_CONTROL_GOBIT_MASK));
 944
 945     value = reg_rd_32(baseAddr + CSL_DSSVP_CONTROL);
 946
 947     /* Set the GoLCD bit */
 948     value |= ((1 << CSL_DSSVP_CONTROL_GOBIT_SHIFT) & (CSL_DSSVP_CONTROL_GOBIT_MASK));
 949     reg_wr_32(baseAddr + CSL_DSSVP_CONTROL, value);
 950 }
 951
 952 /**
 953  *  \brief    Erase frame buffer
 954  *
 955  *  \param    pLcdCfg   [IN]   pointer to LCD Configuration
 956  *
 957  *  \return
 958  *          NONE
 959  */
 960 void dssEraseBuffer(lcdCfg_t *pLcdCfg)
 961 {
 962     unsigned int x,y;
 963
 964     for (y = 0; y < pLcdCfg->LcdHeight; y++)
 965         for (x = 0; x < pLcdCfg->LcdWidth; x++)
 966             *(pFrameBuffer + (y*pLcdCfg->LcdWidth) + (x) ) = BLACK;
 967 }
 968
 969 /**
 970  *  \brief    Set priority of Vid DMA
 971  *
 972  *  This function set the priority of Video DMA
 973  *
 974  *  \param    baseAddr   [IN]   base address of Video Port register
 975  *  \param    priorityFlag [IN]   flag to indicate priority
 976  *
 977  *  \return
 978  *          NONE
 979  */
 980 void dssDispcVidPrioritySet(Uint32 baseAddr, Uint32 priorityFlag)
 981 {
 982     Uint32  value = 0;
 983
 984     /* Clear the priority field */
 985     value = ((reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES)) &
 986         (~CSL_DSSVID_ATTRIBUTES_ARBITRATION_MASK));
 987
 988     /* Program the priority field */
 989     value |= ((priorityFlag << CSL_DSSVID_ATTRIBUTES_ARBITRATION_SHIFT) &
 990             CSL_DSSVID_ATTRIBUTES_ARBITRATION_MASK);
 991     reg_wr_32(baseAddr + CSL_DSSVID_ATTRIBUTES, value);
 992 }
 993
 994 /**
 995  *  \brief    Enable/Disable self refresh
 996  *
 997  *  This function enables/disables the self refresh
 998  *
 999  *  \param    baseAddr   [IN]   base address of Video Port register
1000  *  \param    enableFlag [IN]   flag to indicate enable/disable
1001  *
1002  *  \return
1003  *          NONE
1004  */
1005 void dssDispcVidSelfRefEnableCtrl(Uint32 baseAddr, Uint32 enableFlag)
1006 {
1007     Uint32 value = 0;
1008
1009     value =  reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
1010
1011     if (TRUE == enableFlag)
1012     {
1013         /* Enable self refresh */
1014         value |= ((1 << CSL_DSSVID_ATTRIBUTES_SELFREFRESH_SHIFT) &
1015                 CSL_DSSVID_ATTRIBUTES_SELFREFRESH_MASK);
1016     }
1017     else
1018     {
1019         /* Disable self refresh */
1020         value &= (~CSL_DSSVID_ATTRIBUTES_SELFREFRESH_MASK);
1021     }
1022     reg_wr_32(baseAddr + CSL_DSSVID_ATTRIBUTES, value);
1023 }
1024
1025 /**
1026  *  \brief    Configure base address of frame buffer
1027  *
1028  *  This function configures the base address of frame buffer
1029  *
1030  *  \param    baseAddr      [IN]   base address of Video Port register
1031  *  \param    bufAddr       [IN]   buffer address
1032  *  \param    bufSelectFlag [IN]   buffer select flag
1033  *
1034  *  \return
1035  *          NONE
1036  */
1037 void dssDispcVidSetBufAddr(Uint32 baseAddr,
1038                            Uint32 bufAddr,
1039                            Uint32 bufSelectFlag)
1040 {
1041    reg_wr_32(baseAddr + CSL_DSSVID_BA(bufSelectFlag), bufAddr);
1042 }
1043
1044 /**
1045  *  \brief    Configure video window position
1046  *
1047  *  This function configures the video window position
1048  *
1049  *  \param    baseAddr   [IN]   base address of Video Port register
1050  *  \param    xPos       [IN]   X position of video window
1051  *  \param    yPos       [IN]   Y position of video window
1052  *
1053  *  \return
1054  *           DSS_RET_OK - if configuration is success
1055  *           DSS_RET_FAILED - if configuration is failed
1056  */
1057 DSS_RET dssDispcVidOvlyPositionCfg(Uint32 baseAddr,
1058                                   Uint32 xPos,
1059                                   Uint32 yPos)
1060 {
1061     DSS_RET status = DSS_RET_OK;
1062     Uint32 value = 0;
1063
1064     if ((xPos > DSS_DISPC_VID_WINDOW_XPOS_MAX) ||
1065        (yPos > DSS_DISPC_VID_WINDOW_YPOS_MAX))
1066     {
1067                 IFPRINT(UART_printf("ERROR %s: Invalid values for \
1068                                                                 x,y position\n", __FUNCTION__, __LINE__));
1069         status = DSS_RET_FAILED;
1070     }
1071     else
1072     {
1073         /* Program X position */
1074         value = ((xPos << CSL_DSSVID_POSITION_POSX_SHIFT) &
1075             (CSL_DSSVID_POSITION_POSX_MASK));
1076         /* Program Y position */
1077         value |= ((yPos << CSL_DSSVID_POSITION_POSY_SHIFT) &
1078             (CSL_DSSVID_POSITION_POSY_MASK));
1079         reg_wr_32(baseAddr + CSL_DSSVID_POSITION, value);
1080     }
1081
1082     return status;
1083 }
1084
1085 /**
1086  *  \brief    Configure video window size
1087  *
1088  *  This function configures the video window size
1089  *
1090  *  \param    baseAddr   [IN]   base address of Video Port register
1091  *  \param    width      [IN]   Video width
1092  *  \param    height     [IN]   Video height
1093  *
1094  *  \return
1095  *           DSS_RET_OK - if configuration is success
1096  *           DSS_RET_FAILED - if configuration is failed
1097  */
1098
1099 DSS_RET dssDispcVidSizeCfg(Uint32 baseAddr,
1100                           Uint32 height,
1101                           Uint32 width)
1102 {
1103     DSS_RET status = DSS_RET_OK;
1104     Uint32 value = 0;
1105
1106     if ((width < DSS_DISPC_VID_SIZE_X_MIN) ||
1107         (width > DSS_DISPC_VID_SIZE_X_MAX) ||
1108         (height < DSS_DISPC_VID_SIZE_Y_MIN) ||
1109         (height > DSS_DISPC_VID_SIZE_Y_MAX))
1110     {
1111                 IFPRINT(UART_printf("ERROR %s: Invalid values for video height and \
1112                                                                 width\n", __FUNCTION__, __LINE__));
1113         status = DSS_RET_FAILED;
1114     }
1115     else
1116     {
1117         /* Program Y size(width) */
1118         value = (((width - 1) << CSL_DSSVID_SIZE_SIZEY_SHIFT) &
1119                 CSL_DSSVID_SIZE_SIZEY_MASK);
1120         /* Program X size (height) */
1121         value |= (((height - 1) << CSL_DSSVID_SIZE_SIZEX_SHIFT) &
1122                 CSL_DSSVID_SIZE_SIZEX_MASK);
1123         reg_wr_32(baseAddr + CSL_DSSVID_SIZE, value);
1124
1125         /* UG: Program Picture_Size */
1126         /* Program Y size (width) */
1127         value = (((width - 1) << CSL_DSSVID_PICTURE_SIZE_MEMSIZEY_SHIFT) &
1128                 CSL_DSSVID_PICTURE_SIZE_MEMSIZEY_MASK);
1129
1130         /* Program X size (height) */
1131         value |= (((height - 1) << CSL_DSSVID_PICTURE_SIZE_MEMSIZEX_SHIFT) &
1132                 CSL_DSSVID_PICTURE_SIZE_MEMSIZEX_MASK);
1133         reg_wr_32(baseAddr + CSL_DSSVID_PICTURE_SIZE, value);
1134     }
1135     return status;
1136 }
1137
1138 /**
1139  *  \brief    Configure video window data format
1140  *
1141  *  This function configures the video window data format
1142  *
1143  *  \param    baseAddr    [IN]   base address of Video Port register
1144  *  \param    format      [IN]   format to be configured
1145  *  \param    nibbleModen [IN]   Nibble mode
1146  *
1147  *  \return
1148  *          NONE
1149  */
1150 void dssDispcVidFormatSet(Uint32 baseAddr,
1151                           Uint32 format,
1152                           Uint32 nibbleModen)
1153 {
1154     Uint32 value = 0;
1155
1156     value = reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
1157
1158     /* Clear format, endianness, nibble mode, replication fields */
1159     value &= (~(CSL_DSSVID_ATTRIBUTES_FORMAT_MASK |
1160         CSL_DSSVID_ATTRIBUTES_NIBBLEMODE_MASK));
1161
1162     /* Program the graphics format field */
1163     value |= ((format << CSL_DSSVID_ATTRIBUTES_FORMAT_SHIFT) & CSL_DSSVID_ATTRIBUTES_FORMAT_MASK);
1164     /* Program the nibble mode field */
1165     value |= ((nibbleModen << CSL_DSSVID_ATTRIBUTES_NIBBLEMODE_SHIFT) &
1166             CSL_DSSVID_ATTRIBUTES_NIBBLEMODE_MASK);
1167
1168     reg_wr_32(baseAddr + CSL_DSSVID_ATTRIBUTES, value);
1169 }
1170
1171 /**
1172  *  \brief    DSS Interrupt Handler
1173  *
1174  *  This is the DSS Interrupt Handler
1175  *
1176  *  \return
1177  *          NONE
1178  */
1179 void dssIsr(void)
1180 {
1181     Uint32 vidIrqStatus = 0;
1182     Uint32 vpIrqStatus = 0;
1183
1184     vidIrqStatus = reg_rd_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVID_IRQSTATUS);
1185     vpIrqStatus = reg_rd_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVP_IRQSTATUS);
1186
1187     /*
1188      * Check for Video pipeline interrupts
1189      */
1190     if(vidIrqStatus != 0x0)
1191     {
1192         if(vidIrqStatus & CSL_DSSVID_IRQSTATUS_VIDBUFFERUNDERFLOW_IRQ_MASK)
1193         {
1194             /* Clear the interrupt */
1195             reg_wr_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVID_IRQSTATUS, vidIrqStatus | CSL_DSSVID_IRQSTATUS_VIDBUFFERUNDERFLOW_IRQ_MASK);
1196
1197             count_underflow[uf_index] = count;
1198             uf_index++;
1199             if (uf_index == 10){
1200                 uf_index = 0;
1201             }
1202
1203         }else if(vidIrqStatus & CSL_DSSVID_IRQSTATUS_VIDENDWINDOW_IRQ_MASK)
1204         {
1205             /* Clear the interrupt */
1206             reg_wr_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVID_IRQSTATUS, vidIrqStatus | CSL_DSSVID_IRQSTATUS_VIDENDWINDOW_IRQ_MASK);
1207         }
1208     }
1209
1210     /*
1211      * Check for VP pipeline interrupts
1212      */
1213     if(vpIrqStatus != 0x0)
1214     {
1215         /* Synchronization lost interrupt? */
1216         if(vpIrqStatus && CSL_DSSVP_IRQSTATUS_VPSYNCLOST_IRQ_MASK)
1217         {
1218             /* Clear the interrupt */
1219             reg_wr_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVP_IRQSTATUS, vpIrqStatus | CSL_DSSVP_IRQSTATUS_VPSYNCLOST_IRQ_MASK);
1220
1221         /* Programmed line number interrupt? */
1222         }else if(vpIrqStatus && CSL_DSSVP_IRQSTATUS_VPPROGRAMMEDLINENUMBER_IRQ_MASK)
1223         {
1224             /* Clear the interrupt */
1225             reg_wr_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVP_IRQSTATUS, vpIrqStatus | CSL_DSSVP_IRQSTATUS_VPPROGRAMMEDLINENUMBER_IRQ_MASK);
1226
1227         /* Frame done interrupt? */
1228         }else if(vpIrqStatus && CSL_DSSVP_IRQSTATUS_VPFRAMEDONE_IRQ_MASK)
1229         {
1230             /* Clear the interrupt */
1231             reg_wr_32(CSL_DSSUL_0_CFG_REGS + CSL_DSSVP_IRQSTATUS, vpIrqStatus | CSL_DSSVP_IRQSTATUS_VPFRAMEDONE_IRQ_MASK);
1232             count++;
1233         }
1234     }
1235 }
1236 /**
1237  *  \brief    DSS Register Dump
1238  *
1239  *  This function dumps the DSS module register values
1240  *
1241  *  \param    dssInfo    [IN]   dssInfo structure passed from LCD panel init
1242  *
1243  *  \return   none
1244  *
1245  */
1246 #if (PLATFORM_DEBUG)
1247 void dssDumpReg(dssInfo_t *dssInfo)
1248 {
1249         Uint32 baseAddr = 0;
1250         Uint32 value = 0;
1251
1252     lcdCfg_t  lcdCfg;
1253     dispCfg_t dispCfg;
1254     tmgCfg_t  tmgCfg;
1255     dmaCfg_t  vidDmaCfg;
1256
1257     lcdCfg = dssInfo->lcdCfg;
1258     dispCfg = dssInfo->dispCfg;
1259     tmgCfg = dssInfo->tmgCfg;
1260     vidDmaCfg = dssInfo->vidDmaCfg;
1261
1262     IFPRINT(UART_printf("%s: LcdWidth-%d\n\n",__FUNCTION__, lcdCfg.LcdWidth));
1263     IFPRINT(UART_printf("%s: LcdHeight-%d\n\n",__FUNCTION__, lcdCfg.LcdHeight));
1264     IFPRINT(UART_printf("%s: LcdPclk-%d\n\n",__FUNCTION__, lcdCfg.LcdPclk));
1265     IFPRINT(UART_printf("%s: HsyncWidth-%d\n\n",__FUNCTION__, lcdCfg.HsyncWidth));
1266     IFPRINT(UART_printf("%s: HFrontPorch-%d\n\n",__FUNCTION__, lcdCfg.HFrontPorch));
1267     IFPRINT(UART_printf("%s: HBackPorch-%d\n\n",__FUNCTION__, lcdCfg.HBackPorch));
1268     IFPRINT(UART_printf("%s: VsyncWidth-%d\n\n",__FUNCTION__, lcdCfg.VsyncWidth));
1269     IFPRINT(UART_printf("%s: VFrontPorch-%d\n\n",__FUNCTION__, lcdCfg.VFrontPorch));
1270     IFPRINT(UART_printf("%s: VBackPorch-%d\n\n",__FUNCTION__, lcdCfg.VBackPorch));
1271
1272     IFPRINT(UART_printf("%s: displayType-%d\n\n",__FUNCTION__, dispCfg.displayType));
1273     IFPRINT(UART_printf("%s: colorMode-%d\n\n",__FUNCTION__, dispCfg.colorMode));
1274     IFPRINT(UART_printf("%s: dataLines-%d\n\n",__FUNCTION__, dispCfg.dataLines));
1275     IFPRINT(UART_printf("%s: mono8Bit-%d\n\n",__FUNCTION__, dispCfg.mono8Bit));
1276
1277     IFPRINT(UART_printf("%s: hsyncPolarity-%d\n\n",__FUNCTION__, tmgCfg.hsyncPolarity));
1278     IFPRINT(UART_printf("%s: vsyncPolarity-%d\n\n",__FUNCTION__, tmgCfg.vsyncPolarity));
1279     IFPRINT(UART_printf("%s: syncEdge-%d\n\n",__FUNCTION__, tmgCfg.syncEdge));
1280     IFPRINT(UART_printf("%s: syncEdgeCtrl-%d\n\n",__FUNCTION__, tmgCfg.syncEdgeCtrl));
1281     IFPRINT(UART_printf("%s: pclkPolarity-%d\n\n",__FUNCTION__, tmgCfg.pclkPolarity));
1282     IFPRINT(UART_printf("%s: acbFrequency-%d\n\n",__FUNCTION__, tmgCfg.acbFrequency));
1283     IFPRINT(UART_printf("%s: acbi-%d\n\n",__FUNCTION__, tmgCfg.acbi));
1284     IFPRINT(UART_printf("%s: hsyncGated-%d\n\n",__FUNCTION__, tmgCfg.hsyncGated));
1285     IFPRINT(UART_printf("%s: vsyncGated-%d\n\n",__FUNCTION__, tmgCfg.vsyncGated));
1286     IFPRINT(UART_printf("%s: acbGated-%d\n\n",__FUNCTION__, tmgCfg.acbGated));
1287     IFPRINT(UART_printf("%s: pixelClkGated-%d\n\n",__FUNCTION__, tmgCfg.pixelClkGated));
1288
1289     IFPRINT(UART_printf("%s: fifoLoThr-%d\n\n",__FUNCTION__, vidDmaCfg.fifoLoThr));
1290     IFPRINT(UART_printf("%s: fifoHiThr-%d\n\n",__FUNCTION__, vidDmaCfg.fifoHiThr));
1291     IFPRINT(UART_printf("%s: pixelInc-%d\n\n",__FUNCTION__, vidDmaCfg.pixelInc));
1292     IFPRINT(UART_printf("%s: rowInc-%d\n\n",__FUNCTION__, vidDmaCfg.rowInc));
1293     IFPRINT(UART_printf("%s: preloadSelect-%d\n\n",__FUNCTION__, vidDmaCfg.preloadSelect));
1294     IFPRINT(UART_printf("%s: mflagLoThr-%d\n\n",__FUNCTION__, vidDmaCfg.mflagLoThr));
1295     IFPRINT(UART_printf("%s: mflagHiThr-%d\n\n",__FUNCTION__, vidDmaCfg.mflagHiThr));
1296     IFPRINT(UART_printf("%s: mflagAttrControl-%d\n\n",__FUNCTION__, vidDmaCfg.mflagAttrControl));
1297     IFPRINT(UART_printf("%s: mflagAttrStart-%d\n\n",__FUNCTION__, vidDmaCfg.mflagAttrStart));
1298     IFPRINT(UART_printf("%s: dssInitiatorPri_Hi-%d\n\n",__FUNCTION__, vidDmaCfg.dssInitiatorPri_Hi));
1299     IFPRINT(UART_printf("%s: dssInitiatorPri_Lo-%d\n\n",__FUNCTION__, vidDmaCfg.dssInitiatorPri_Lo));
1300
1301         baseAddr = DSS_DISPC_BASE_ADDRESS;
1302         IFPRINT(UART_printf("%s (line%d): Base Address = 0x%x\n", __FUNCTION__, __LINE__, baseAddr));
1303
1304         /*Bit 1 is softreset*/
1305         value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG);
1306         IFPRINT(UART_printf("%s (line%d): Value at (DISPC_SYSCONFIG-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSCOMMON_DISPC_SYSCONFIG) , value));
1307
1308         /*Bit 0 is module reset complete*/
1309         value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_SYSSTATUS);
1310         IFPRINT(UART_printf("%s (line%d): Value at (DISPC_SYSSTATUS-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSCOMMON_DISPC_SYSSTATUS), value));
1311
1312         value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE);
1313         IFPRINT(UART_printf("%s (line%d): Value at (DISPC_GLOBAL_MFLAG_ATTRIBUTE-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSCOMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE), value));
1314
1315         value = reg_rd_32(baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_SET);
1316         IFPRINT(UART_printf("%s (line%d): Value at (DISPC_IRQENABLE_SET-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSCOMMON_DISPC_IRQENABLE_SET), value));
1317
1318         baseAddr = DSS_VID_BASE_ADDRESS;
1319         IFPRINT(UART_printf("%s (line%d): Base Address = 0x%x\n", __FUNCTION__, __LINE__, baseAddr));
1320
1321         value = reg_rd_32(baseAddr + CSL_DSSVID_MFLAG_THRESHOLD);
1322         IFPRINT(UART_printf("%s (line%d): Value at (MFLAG_THRESHOLD-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_MFLAG_THRESHOLD), value));
1323
1324         value = reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
1325         IFPRINT(UART_printf("%s (line%d): Value at (ATTRIBUTES-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_ATTRIBUTES), value));
1326
1327         value = reg_rd_32(baseAddr + CSL_DSSVID_BA(0));
1328         IFPRINT(UART_printf("%s (line%d): Value at (DSSVID_BA(0)-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_BA(0)), value));
1329
1330         value = reg_rd_32(baseAddr + CSL_DSSVID_BA(1));
1331         IFPRINT(UART_printf("%s (line%d): Value at (DSSVID_BA(1)-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_BA(1)), value));
1332
1333         value = reg_rd_32(baseAddr + CSL_DSSVID_POSITION);
1334         IFPRINT(UART_printf("%s (line%d): Value at (VID_POSITION-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_POSITION), value));
1335
1336         value = reg_rd_32(baseAddr + CSL_DSSVID_PICTURE_SIZE);
1337         IFPRINT(UART_printf("%s (line%d): Value at (VID_PICTURE_SIZE-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_PICTURE_SIZE), value));
1338
1339         value = reg_rd_32(baseAddr + CSL_DSSVID_IRQENABLE);
1340         IFPRINT(UART_printf("%s (line%d): Value at (VID_IRQENABLE-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_IRQENABLE), value));
1341
1342         value = reg_rd_32(baseAddr + CSL_DSSVID_ATTRIBUTES);
1343         IFPRINT(UART_printf("%s (line%d): Value at (ATTRIBUTES-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVID_ATTRIBUTES), value));
1344
1345         baseAddr = DSS_VP_BASE_ADDRESS;
1346         IFPRINT(UART_printf("%s (line%d): Base Address = 0x%x\n", __FUNCTION__, __LINE__, baseAddr));
1347
1348         value = reg_rd_32(baseAddr + CSL_DSSVP_SIZE_SCREEN);
1349         IFPRINT(UART_printf("%s (line%d): Value at (VP_SIZE_SCREEN-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_SIZE_SCREEN), value));
1350
1351         value = reg_rd_32(baseAddr + CSL_DSSVP_TIMING_H);
1352         IFPRINT(UART_printf("%s (line%d): Value at (VP_TIMING_H-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_TIMING_H), value));
1353
1354         value = reg_rd_32(baseAddr + CSL_DSSVP_TIMING_V);
1355         IFPRINT(UART_printf("%s (line%d): Value at (VP_TIMING_V-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_TIMING_V), value));
1356
1357         value = reg_rd_32(baseAddr + CSL_DSSVP_POL_FREQ);
1358         IFPRINT(UART_printf("%s (line%d): Value at (VP_POL_FREQ-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_POL_FREQ), value));
1359
1360         value = reg_rd_32(baseAddr + CSL_DSSVP_IRQSTATUS);
1361         IFPRINT(UART_printf("%s (line%d): Value at (VP_IRQSTATUS-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_IRQSTATUS), value));
1362
1363         value = reg_rd_32(baseAddr + CSL_DSSVP_IRQENABLE);
1364         IFPRINT(UART_printf("%s (line%d): Value at (VP_IRQENABLE-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_IRQENABLE), value));
1365
1366         value = reg_rd_32(baseAddr + CSL_DSSVP_CONTROL);
1367         IFPRINT(UART_printf("%s (line%d): Value at (VP_CONTROL-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSSVP_CONTROL), value));
1368
1369         baseAddr = DSS_BASE_ADDRESS;
1370         IFPRINT(UART_printf("%s (line%d): Base Address = 0x%x\n", __FUNCTION__, __LINE__, baseAddr));
1371
1372         value = reg_rd_32(baseAddr + CSL_DSS_DSS_DPI_CTRL);
1373         IFPRINT(UART_printf("%s (line%d): Value at (DSS_DSS_DPI_CTRL-0x%x) is 0x%x\n", __FUNCTION__, __LINE__, (baseAddr + CSL_DSS_DSS_DPI_CTRL), value));
1374
1375 }
1376 #endif
1377 /**
1378  *  \brief    DSS Initialization
1379  *
1380  *  This function initializes the DSS module with the given LCD panel
1381  *  information, Timing configuration, Display configuration and DMA
1382  *  configuration.
1383  *
1384  *  \param    dssInfo    [IN]   dssInfo structure passed from LCD panel init
1385  *
1386  *  \return
1387  *           DSS_RET_OK -    status to indicate success
1388  *           DSS_RET_FAILED - if DSS failed to initialize, returns failure.
1389  *
1390  */
1391 DSS_RET dssInit(dssInfo_t *dssInfo)
1392 {
1393     lcdCfg_t  lcdCfg;
1394     dispCfg_t dispCfg;
1395     tmgCfg_t  tmgCfg;
1396     dmaCfg_t  vidDmaCfg;
1397     DSS_RET     status = DSS_RET_FAILED;
1398
1399     lcdCfg = dssInfo->lcdCfg;
1400     dispCfg = dssInfo->dispCfg;
1401     tmgCfg = dssInfo->tmgCfg;
1402     vidDmaCfg = dssInfo->vidDmaCfg;
1403
1404     /* Erase the frame buffer */
1405     dssEraseBuffer(&lcdCfg);
1406
1407     /* Initialize Frame Buffer */
1408     dssInitFrameBuffer(RGB888_ADDRESS, lcdCfg.LcdWidth, lcdCfg.LcdHeight);
1409
1410     /* Perform soft reset of DISPC module*/
1411     dssDispcSoftReset(DSS_DISPC_BASE_ADDRESS);
1412
1413     /* Enable auto-idle */
1414     dssDispcAutoIdleEnableCtrl(DSS_DISPC_BASE_ADDRESS, ENABLE);
1415
1416     status = dssInitiatorPriorityCfg (CSL_BOOT_CFG_REGS, vidDmaCfg.dssInitiatorPri_Lo, vidDmaCfg.dssInitiatorPri_Hi);
1417     if (status == DSS_RET_FAILED)
1418     {
1419                 IFPRINT(UART_printf("ERROR: Configuring DSS initiator \
1420                                                                 priority failed\n"));
1421         return status;
1422     }
1423
1424     status = dssDispcMflagAttributeCfg(DSS_DISPC_BASE_ADDRESS, vidDmaCfg.mflagAttrStart, vidDmaCfg.mflagAttrControl);
1425     if (status == DSS_RET_FAILED)
1426     {
1427                 IFPRINT(UART_printf("ERROR: Configuring DMA attributes failed\n"));
1428         return status;
1429     }
1430
1431     status = dssDispcMflagThresholdCfg(DSS_VID_BASE_ADDRESS, vidDmaCfg.mflagLoThr, vidDmaCfg.mflagHiThr);
1432
1433     if (status == DSS_RET_FAILED)
1434     {
1435                 IFPRINT(UART_printf("ERROR: Configuring thresholds failed\n"));
1436         return status;
1437     }
1438
1439     /* Configure video pipeline DMA parameters*/
1440     status = dssDispcVidDMAConfig(DSS_VID_BASE_ADDRESS, &vidDmaCfg);
1441     if (status == DSS_RET_FAILED)
1442     {
1443                 IFPRINT(UART_printf("ERROR: Configuring Video Pipeline \
1444                                                                 DMA failed\n"));
1445         return status;
1446     }
1447
1448     /* Configure VID arbitration priority */
1449     dssDispcVidPrioritySet(DSS_VID_BASE_ADDRESS, DSS_DISPC_VID_PRIORITY_HIGH);
1450
1451     /* Disable self refresh */
1452     dssDispcVidSelfRefEnableCtrl(DSS_VID_BASE_ADDRESS, DISABLE);
1453
1454     /* Configure frame buffer base address */
1455     dssDispcVidSetBufAddr(DSS_VID_BASE_ADDRESS, /*&frameBuffer*/((Uint32)pFrameBuffer), DSS_DISPC_VID_BUFFER0);
1456
1457     /* Configure position of the video window */
1458     status = dssDispcVidOvlyPositionCfg(DSS_VID_BASE_ADDRESS, 0, 0);
1459     if (status == DSS_RET_FAILED)
1460     {
1461                 IFPRINT(UART_printf("ERROR: Configuring video window \
1462                                                                 position failed\n"));
1463         return status;
1464     }
1465
1466     /* Configure video window size */
1467     status = dssDispcVidSizeCfg(DSS_VID_BASE_ADDRESS, lcdCfg.LcdWidth, lcdCfg.LcdHeight);
1468     if (status == DSS_RET_FAILED)
1469     {
1470                 IFPRINT(UART_printf("ERROR: Configuring video window \
1471                                                                 size failed\n"));
1472         return status;
1473     }
1474
1475     /* Configure Vid data format */
1476     dssDispcVidFormatSet(DSS_VID_BASE_ADDRESS, DSS_DISPC_VID_FMT_ABGR32U, DSS_DISPC_VID_NIBBLE_MODE_DISABLE);
1477
1478     /* Configure LCD color attributes */
1479     status = dssDispcLcdDisplayAttribCfg(DSS_VP_BASE_ADDRESS, &dispCfg);
1480     if (status == DSS_RET_FAILED)
1481     {
1482                 IFPRINT(UART_printf("ERROR: Configuring LCD color \
1483                                                                 attributes failed\n"));
1484         return status;
1485     }
1486
1487     /* Configure LCD panel timing parameters */
1488     status = dssDispcLcdPanelCfg(DSS_VP_BASE_ADDRESS, &lcdCfg);
1489     if (status == DSS_RET_FAILED)
1490     {
1491                 IFPRINT(UART_printf("ERROR: Configuring LCD panel \
1492                                                                 timing parameters failed\n"));
1493         return status;
1494     }
1495
1496     /* Configure LCD control signal polarities */
1497     status = dssDispcLcdTimingCfg(DSS_VP_BASE_ADDRESS, &tmgCfg);
1498     if (status == DSS_RET_FAILED)
1499     {
1500                 IFPRINT(UART_printf("ERROR: Configuring LCD control \
1501                                                                 signal polarities failed\n"));
1502         return status;
1503     }
1504
1505     /* Clear status of all the interrupts */
1506     dssDispcIntStatusClearEx(DSS_VP_BASE_ADDRESS, 0x1FFFF);
1507
1508     /* Configure the programmable line number which generates interrupt */
1509 //  dssDispcProgLineNumberSet(CSL_DSSUL_0_CFG_REGS, DSS_PROG_LINE_NUMBER);  //This can be used for future testing if necessary
1510
1511     /* Enable the DPI interface */
1512     dssDpiCtrl(DSS_BASE_ADDRESS, ENABLE);
1513
1514     /* Enable interrupts to the VID and VP pipelines */
1515     dssDispcCommonIntEnable(DSS_DISPC_BASE_ADDRESS, CSL_DSSCOMMON_DISPC_IRQENABLE_SET_SET_VID1_IRQ_MASK | CSL_DSSCOMMON_DISPC_IRQENABLE_SET_SET_VP1_IRQ_MASK);
1516
1517     /* Enable the Frame Done interrupt */
1518     dssDispcVPIntEnable(DSS_VP_BASE_ADDRESS, CSL_DSSVP_IRQENABLE_VPFRAMEDONE_EN_MASK);
1519
1520     /* Enable VID1 buffer underflow and end of window interrupts */
1521     dssDispcVidIntEnable(DSS_VID_BASE_ADDRESS, CSL_DSSVID_IRQENABLE_VIDBUFFERUNDERFLOW_EN_GENINT | CSL_DSSVID_IRQENABLE_VIDENDWINDOW_EN_GENINT);
1522
1523     /* Enable VID1 pipeline */
1524     dssDispcVidEnableCtrl(DSS_VID_BASE_ADDRESS, TRUE);
1525
1526     /* Set the GO bit */
1527     dssDispcShadowCfgEnable(DSS_VP_BASE_ADDRESS);
1528
1529     /* Enable LCD output */
1530     dssDispcLcdOutputEnableCtrl(DSS_VP_BASE_ADDRESS, ENABLE);
1531
1532     return status;
1533 }
1534
1535 #endif /* #if (PLATFORM_DSS_IN) */
1536
1537 /* Nothing past this point */