[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / board / src / evmAM571x / evmAM571x_ddr.c
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32 *****************************************************************************/
34 #include "board_cfg.h"
35 #include "board_internal.h"
37 #include <ti/csl/csl_emif4fAux.h>
38 #include <ti/csl/cslr_dmm.h>
39 #include <ti/csl/cslr_ma_mpu_lsm.h>
40 #include <ti/csl/src/ip/emif4/V2/csl_emif4d5.h>
42 /** \brief Compute EMIF phy control. */
43 #define EXT_PHY_CTRL_VALUE(ctrlSlaveRatio) \
44 ((ctrlSlaveRatio << 20U) | (ctrlSlaveRatio << 10U) | (ctrlSlaveRatio << 0U))
46 /** \brief Compute EMIF phy FIFO WE. */
47 #define EXT_PHY_FIFO_WE_VALUE(fifoWeSlaveRatio) \
48 ((fifoWeSlaveRatio << 16U) | (fifoWeSlaveRatio << 0U))
50 /** \brief Compute EMIF phy read DQS. */
51 #define EXT_PHY_RD_DQS_VALUE(rdDqsSlaveRatio) \
52 ((rdDqsSlaveRatio << 16U) | (rdDqsSlaveRatio << 0U))
54 /** \brief Compute EMIF phy write data. */
55 #define EXT_PHY_WR_DATA_VALUE(wrDataslaveRatio) \
56 ((wrDataslaveRatio << 16U) | (wrDataslaveRatio << 0U))
58 /** \brief Compute EMIF phy write DQS. */
59 #define EXT_PHY_WR_DQS_VALUE(wrDqsSlaveRatio) \
60 ((wrDqsSlaveRatio << 16U) | (wrDqsSlaveRatio << 0U))
62 /** \brief Compute EMIF phy DQ. */
63 #define EXT_PHY_DQ_VALUE(dqOffset) \
64 ((dqOffset << 21U) | (dqOffset << 14U) | (dqOffset << 7U) | (dqOffset << 0U))
66 /** \brief Compute EMIF phy gate level init. */
67 #define EXT_PHY_GATE_LVL_INIT_VALUE(gateLvlInitRatio) \
68 ((gateLvlInitRatio << 16U) | (gateLvlInitRatio << 0U))
70 /** \brief Compute EMIF phy gate level init. */
71 #define EXT_PHY_WR_LVL_INIT_VALUE(wrLvlInitRatio) \
72 ((wrLvlInitRatio << 16U) | (wrLvlInitRatio << 0U))
74 /** \brief Compute EMIF phy . */
75 #define EXT_PHY_RANK0_DELAY_VALUE(dqOffset, gateLvlInitRatio, rank0Delay, \
76 wrDataslaveRatio) \
77 ((dqOffset << 24U) | (gateLvlInitRatio << 16U) | (rank0Delay << 12U) | \
78 (wrDataslaveRatio << 0U))
80 /** \brief Compute EMIF phy slave and Rank0 delays. */
81 #define EXT_PHY_RANK0_DELAY_MODE(dqOffset, gateLvlInitMode, rank0Delay, \
82 wrDataslaveDelay) \
83 ((dqOffset << 24U) | (gateLvlInitMode << 16U) | (rank0Delay << 12U) | \
84 (wrDataslaveDelay << 0U))
86 /** \brief Compute FIFO_WE_IN and Phy control slave delay .*/
87 #define EXT_PHY_FIFO_WE_SLAVE_CTRL_DELAY(fifoWeInDelay, ctrlSlaveDelay) \
88 ((fifoWeInDelay << 16U) | (ctrlSlaveDelay << 0U))
90 /** \brief Compute WR_LVL_NUM_DQ0 and GATE_LVL_NUM_DQ0.*/
91 #define EXT_PHY_WR_LVL_GATE_LVL_NUM_DQ0(wrLvlNumDq0, gateLvlNumDq0) \
92 ((wrLvlNumDq0 << 4U) | (gateLvlNumDq0 << 0U))
94 /** \brief Compute Read and WriteDQS slave delay. */
95 #define EXT_PHY_WR_RD_DQS_SLAVE_DELAY(wrDqsSlaveDelay, rdDqsSlaveDelay) \
96 ((wrDqsSlaveDelay << 16U) | (rdDqsSlaveDelay << 0U))
98 #define HW_WR_REG32(addr, data) *(unsigned int*)(addr) =(unsigned int)(data)
100 static void ddr_delay(uint32_t ix);
102 static void ddr_delay(uint32_t ix)
103 {
104 while (ix--) {
105 asm(" NOP");
106 }
107 }
109 void emifConfigureDdr3
110 (
111 CSL_emifHandle hEmif,
112 CSL_emifDdrConfig *ddr3Config,
113 Uint32 enableHwLeveling
114 );
116 /* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
117 Board_STATUS Board_DDR3Init()
118 {
119 CSL_emifObj emifObj1;
120 CSL_emifHandle hEmif1 = &emifObj1;
121 CSL_emifDdrConfig ddr3Config1;
122 CSL_ckgen_cm_core_aonRegs *hCkgenCmCoreAon =
123 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
124 CSL_control_core_padRegs *hCtrlCorePad =
125 (CSL_control_core_padRegs *) CSL_MPU_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_REGS;
126 CSL_control_core_wkupRegs *hCtrlCoreWkup =
127 (CSL_control_core_wkupRegs *) CSL_MPU_CTRL_MODULE_WKUP_CORE_REGISTERS_REGS;
128 CSL_DmmRegs *hDmmCfg =(CSL_DmmRegs *) CSL_MPU_DMM_CONF_REGS_REGS;
129 CSL_MampuLsmRegs *hMampuLsm = (CSL_MampuLsmRegs *) CSL_MPU_MA_MPU_LSM_REGS;
131 hEmif1->regs = (CSL_emifRegsOvly)CSL_MPU_EMIF1_CONF_REGS_REGS;
133 /* DLL override disable =0 ; enable = 1 */
134 hCkgenCmCoreAon->CM_DLL_CTRL_REG = 0x00000000;
136 /*
137 * CONTROL_DDR3CH1_0 -- channel_1 CMDs
138 * -- 40Ohm Ron (011)
139 * -- SR=slowest-3 (111) on CMDs
140 * -- CLK SR=slow (011)
141 * -- No pulls (00)
142 */
143 hCtrlCorePad->CONTROL_DDRCACH1_0 = 0x80808080;
145 /*
146 * CONTROL_DDR3CH2_0 -- channel_2 CMDs
147 * -- 40Ohm Ron (011)
148 * -- SR=slowest-3 (111) on CMDs
149 * -- CLK SR=slow (011)
150 * -- No pulls (00)
151 */
152 hCtrlCorePad->CONTROL_DDRCACH2_0 = 0x80808080;
154 /*
155 * CONTROL_DDRCH1_0 -- channel_1 DATA byte 0+1
156 * -- 40Ohm Ron (011)
157 * -- SR=faster (001)
158 * -- Pull-up (10) on DQS
159 * -- No pull (00) on DQ
160 */
161 hCtrlCorePad->CONTROL_DDRCH1_0 = 0x40404040;
163 /*
164 * CONTROL_DDRCH1_1 -- channel_1 DATA byte 2+3
165 * -- 40Ohm Ron (011)
166 * -- SR=faster (001)
167 * -- Pull-up (10) on DQS
168 * -- No pull (00) on DQ
169 */
170 hCtrlCorePad->CONTROL_DDRCH1_1 = 0x40404040;
172 /*
173 * CONTROL_DDRCH2_0 -- channel_2 DATA byte 0+1
174 * -- 40Ohm Ron (011)
175 * -- SR=faster (001)
176 * -- Pull-up (10) on DQS
177 * -- No pull (00) on DQ
178 */
179 hCtrlCorePad->CONTROL_DDRCH2_0 = 0x40404040;
181 /*
182 * CONTROL_DDRCH2_1 -- channel_2 DATA byte 2+3
183 * -- 40Ohm Ron (011)
184 * -- SR=faster (001)
185 * -- Pull-up (10) on DQS
186 * -- No pull (00) on DQ
187 */
188 hCtrlCorePad->CONTROL_DDRCH2_1 = 0x40404040;
190 /*
191 * CONTROL_LPDDR2CH1_0
192 * -- channel_1 LPDDR2 CMD PHYs IOs not used
193 */
194 hCtrlCorePad->CONTROL_DDRCH1_2 = 0x40404040;
196 /*
197 * CONTROL_CONTROL_LPDDR2CH1_1
198 * -- channel_1 LPDDR2 CMD PHYs IOs not used
199 */
200 hCtrlCorePad->CONTROL_DDRCH2_2 = 0x80808080;
202 /*
203 * DDRIO_0 -- VREF cells
204 * (CH1 DQ3/0 INT 2uA / Cap to GND / CMD1/0 DDR3 INT-OUT 32uA / Cap to GND)
205 */
206 hCtrlCorePad->CONTROL_DDRIO_0 = 0xA2084210;
208 /*
209 * DDRIO_1 -- VREF cells
210 * (CH1 OUT 32uA Cap to GND / CH2 DQ3/0 INT 2uA / Cap to GND / CH2 OUT 32uA Cap to GND)
211 */
212 hCtrlCorePad->CONTROL_DDRIO_1 = 0x84210840;
214 /*
215 * DDRIO_2 -- VREF cells (LPDDR2 CH1/2 CA INT/OUT - unused on OMAP5432)
216 */
217 hCtrlCorePad->CONTROL_HYST_1 = 0x84210000;
219 /* CONTROL_DDRIO_EXT_0 */
220 hCtrlCorePad->CONTROL_DDRIO_EXT_0 = 0xA2000000;
222 /*
223 * EMIF1_SDRAM_CONFIG_EXT
224 * -- cslice_en[2:0]=111 / Local_odt=01 / dyn_pwrdn=1 / dis_reset=0 / rd_lvl_samples=11 (128)
225 */
226 hCtrlCoreWkup->EMIF1_SDRAM_CONFIG_EXT = 0x0001C127;
228 ddr3Config1.emifDdrParam.ddrPhyCtrl = 0x0024400AU;
229 ddr3Config1.emifDdrParam.sdramTim1 = 0xCEEF266BU;
230 ddr3Config1.emifDdrParam.sdramTim2 = 0x328F7FDAU;
231 ddr3Config1.emifDdrParam.sdramTim3 = 0x427F88A8U;
232 ddr3Config1.emifDdrParam.sdramCfg = 0x61851B32U;
233 ddr3Config1.emifDdrParam.sdramCfg2 = 0x00000000U;
234 ddr3Config1.emifDdrParam.sdramRefCtrl = 0x00001035U;
235 ddr3Config1.emifDdrParam.zqConfig = 0x0007190BU;
236 ddr3Config1.emifDdrParam.sdramPwrMngtCtrl = 0x00000000U;
238 ddr3Config1.emifDdrPhyParam.ctrlSlaveRatio = 0x100U;
239 ddr3Config1.emifDdrPhyParam.gateLevelRatio = 0x40U;
240 ddr3Config1.emifDdrPhyParam.writeLevelInitRatio = 0x00;
241 ddr3Config1.emifDdrPhyParam.writeDqsSlaveRatio = 0U;
242 ddr3Config1.emifDdrPhyParam.fifoWeSlaveRatio = 0U;
243 ddr3Config1.emifDdrPhyParam.useRank0Delays = 0U;
244 ddr3Config1.emifDdrPhyParam.fifoWeInDelay = 0x0U;
245 ddr3Config1.emifDdrPhyParam.ctrlSlaveDelay = 0x0U;
246 ddr3Config1.emifDdrPhyParam.readDqsSlaveDelay = 0x0020U;
247 ddr3Config1.emifDdrPhyParam.writeDqsSlaveDelay = 0x0060U;
248 ddr3Config1.emifDdrPhyParam.dqOffset = 0x40U;
249 ddr3Config1.emifDdrPhyParam.gateLevelInitMode = 0x01U;
250 ddr3Config1.emifDdrPhyParam.writeDataSlaveDelay = 0x80U;
251 ddr3Config1.emifDdrPhyParam.gateLevelNumDq0 = 0xFU;
252 ddr3Config1.emifDdrPhyParam.writeLevelNumDq0 = 0xFU;
254 emifConfigureDdr3(hEmif1, &ddr3Config1, 1U);
256 /* MA_LISA_MAP_i */
257 hMampuLsm->MAP_0 = 0x80600100U;
258 hMampuLsm->MAP_1 = 0x00000000U;
259 hMampuLsm->MAP_2 = 0x00000000U;
260 hMampuLsm->MAP_3 = 0x00000000U;
262 /* DMM_LISA_MAP_i */
263 hDmmCfg->LISA_MAP[0U] = 0x80600100U;
264 hDmmCfg->LISA_MAP[1U] = 0x00000000U;
265 hDmmCfg->LISA_MAP[2U] = 0x00000000U;
266 hDmmCfg->LISA_MAP[3U] = 0x00000000U;
268 return BOARD_SOK;
269 }
271 void emifConfigureDdr3
272 (
273 CSL_emifHandle hEmif,
274 CSL_emifDdrConfig *ddr3Config,
275 Uint32 enableHwLeveling
276 )
277 {
278 Uint32 regVal = 0U;
280 hEmif->regs->DDR_PHY_CONTROL_1 = ddr3Config->emifDdrParam.ddrPhyCtrl;
281 hEmif->regs->DDR_PHY_CONTROL_1_SHADOW = ddr3Config->emifDdrParam.ddrPhyCtrl;
283 regVal = EXT_PHY_CTRL_VALUE(ddr3Config->emifDdrPhyParam.ctrlSlaveRatio);
284 hEmif->regs->EXT_PHY_CONTROL_1 = regVal;
285 hEmif->regs->EXT_PHY_CONTROL_1_SHADOW = regVal;
287 /* Force Slave ratio values not required if HW levelling is enabled */
289 /* Use Init values if HW leveling is enabled */
290 /* Gate level Init ratios */
291 regVal = EXT_PHY_GATE_LVL_INIT_VALUE(ddr3Config->emifDdrPhyParam.gateLevelRatio);
292 hEmif->regs->EXT_PHY_CONTROL_26 = regVal;
293 hEmif->regs->EXT_PHY_CONTROL_26_SHADOW = regVal;
294 hEmif->regs->EXT_PHY_CONTROL_27 = regVal;
295 hEmif->regs->EXT_PHY_CONTROL_27_SHADOW = regVal;
296 hEmif->regs->EXT_PHY_CONTROL_28 = regVal;
297 hEmif->regs->EXT_PHY_CONTROL_28_SHADOW = regVal;
298 hEmif->regs->EXT_PHY_CONTROL_29 = regVal;
299 hEmif->regs->EXT_PHY_CONTROL_29_SHADOW = regVal;
300 hEmif->regs->EXT_PHY_CONTROL_30 = regVal;
301 hEmif->regs->EXT_PHY_CONTROL_30_SHADOW = regVal;
303 /* WR DQS Init ratios */
304 regVal = EXT_PHY_WR_LVL_INIT_VALUE(ddr3Config->emifDdrPhyParam.writeLevelInitRatio);
305 hEmif->regs->EXT_PHY_CONTROL_31 = regVal;
306 hEmif->regs->EXT_PHY_CONTROL_31_SHADOW = regVal;
307 hEmif->regs->EXT_PHY_CONTROL_32 = regVal;
308 hEmif->regs->EXT_PHY_CONTROL_32_SHADOW = regVal;
309 hEmif->regs->EXT_PHY_CONTROL_33 = regVal;
310 hEmif->regs->EXT_PHY_CONTROL_33_SHADOW = regVal;
311 hEmif->regs->EXT_PHY_CONTROL_34 = regVal;
312 hEmif->regs->EXT_PHY_CONTROL_34_SHADOW = regVal;
313 hEmif->regs->EXT_PHY_CONTROL_35 = regVal;
314 hEmif->regs->EXT_PHY_CONTROL_35_SHADOW = regVal;
316 /* PHY settings for DQ offset, DLL override delay, levelling etc. */
317 regVal = EXT_PHY_FIFO_WE_SLAVE_CTRL_DELAY(ddr3Config->emifDdrPhyParam.fifoWeInDelay,
318 ddr3Config->emifDdrPhyParam.ctrlSlaveDelay);
319 hEmif->regs->EXT_PHY_CONTROL_22 = regVal;
320 hEmif->regs->EXT_PHY_CONTROL_22_SHADOW = regVal;
321 regVal = EXT_PHY_WR_RD_DQS_SLAVE_DELAY(ddr3Config->emifDdrPhyParam.writeDqsSlaveDelay,
322 ddr3Config->emifDdrPhyParam.readDqsSlaveDelay);
323 hEmif->regs->EXT_PHY_CONTROL_23 = regVal;
324 hEmif->regs->EXT_PHY_CONTROL_23_SHADOW = regVal;
325 regVal = EXT_PHY_RANK0_DELAY_VALUE(ddr3Config->emifDdrPhyParam.dqOffset,
326 ddr3Config->emifDdrPhyParam.gateLevelInitMode,
327 ddr3Config->emifDdrPhyParam.useRank0Delays,
328 ddr3Config->emifDdrPhyParam.writeDataSlaveDelay);
329 hEmif->regs->EXT_PHY_CONTROL_24 = regVal;
330 hEmif->regs->EXT_PHY_CONTROL_24_SHADOW = regVal;
331 regVal = EXT_PHY_DQ_VALUE(ddr3Config->emifDdrPhyParam.dqOffset);
332 hEmif->regs->EXT_PHY_CONTROL_25 = regVal;
333 hEmif->regs->EXT_PHY_CONTROL_25_SHADOW = regVal;
334 regVal = EXT_PHY_WR_LVL_GATE_LVL_NUM_DQ0(ddr3Config->emifDdrPhyParam.writeLevelNumDq0,
335 ddr3Config->emifDdrPhyParam.gateLevelNumDq0);
336 hEmif->regs->EXT_PHY_CONTROL_36 = regVal;
337 hEmif->regs->EXT_PHY_CONTROL_36_SHADOW = regVal;
339 /* Apply PHY RESET to latch all the PHY registers */
340 hEmif->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL = 0x00002011;
341 hEmif->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL = 0x00002411;
342 hEmif->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL = 0x00002011;
344 /* Disable initialization and refreshes until the EMIF is programmed */
345 hEmif->regs->SDRAM_REFRESH_CONTROL = 0x80003000;
346 hEmif->regs->SDRAM_REFRESH_CONTROL_SHADOW = 0x80003000;
348 /* Set up the EMIF registers */
349 hEmif->regs->SDRAM_TIMING_1 = ddr3Config->emifDdrParam.sdramTim1;
350 hEmif->regs->SDRAM_TIMING_1_SHADOW = ddr3Config->emifDdrParam.sdramTim1;
351 hEmif->regs->SDRAM_TIMING_2 = ddr3Config->emifDdrParam.sdramTim2;
352 hEmif->regs->SDRAM_TIMING_2_SHADOW = ddr3Config->emifDdrParam.sdramTim2;
353 hEmif->regs->SDRAM_TIMING_3 = ddr3Config->emifDdrParam.sdramTim3;
354 hEmif->regs->SDRAM_TIMING_3_SHADOW = ddr3Config->emifDdrParam.sdramTim3;
356 hEmif->regs->POWER_MANAGEMENT_CONTROL = ddr3Config->emifDdrParam.sdramPwrMngtCtrl;
357 hEmif->regs->POWER_MANAGEMENT_CONTROL_SHADOW = ddr3Config->emifDdrParam.sdramPwrMngtCtrl;
359 /* Leave these as RESET values */
360 hEmif->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL = 0x00002011U;
361 hEmif->regs->SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG = ddr3Config->emifDdrParam.zqConfig;
362 hEmif->regs->READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000;
363 hEmif->regs->READ_WRITE_LEVELING_RAMP_CONTROL = 0x80000000;
364 hEmif->regs->READ_WRITE_LEVELING_CONTROL = 0x00000000;
366 /* Set up long refresh time so that RESET-CKE timing is met */
367 hEmif->regs->SDRAM_REFRESH_CONTROL_SHADOW = 0x3000;
368 hEmif->regs->SDRAM_REFRESH_CONTROL = 0x3000;
369 hEmif->regs->SDRAM_CONFIG_2 = ddr3Config->emifDdrParam.sdramCfg2;
370 hEmif->regs->SDRAM_CONFIG = ddr3Config->emifDdrParam.sdramCfg;
372 /* Now update with the correct refresh time */
373 hEmif->regs->SDRAM_REFRESH_CONTROL_SHADOW = ddr3Config->emifDdrParam.sdramRefCtrl;
374 hEmif->regs->SDRAM_REFRESH_CONTROL = ddr3Config->emifDdrParam.sdramRefCtrl;
376 /* Some clock cycle delay for refresh to complete. */
377 ddr_delay(100000);
379 regVal = hEmif->regs->EXT_PHY_CONTROL_36;
380 regVal = (regVal | 0x00000100U);
381 hEmif->regs->EXT_PHY_CONTROL_36 = regVal;
382 regVal = hEmif->regs->EXT_PHY_CONTROL_36_SHADOW;
383 regVal = (regVal | 0x00000100U);
384 hEmif->regs->EXT_PHY_CONTROL_36_SHADOW = regVal;
386 hEmif->regs->READ_WRITE_LEVELING_RAMP_CONTROL = 0x80000000;
387 hEmif->regs->READ_WRITE_LEVELING_CONTROL = 0x80000000;
389 /* hwlvmod wait for read and write levelling bit to clear RDWRLVLFULL_START bit 31 */
390 while((hEmif->regs->READ_WRITE_LEVELING_CONTROL & 0x80000000) != 0x0U);
391 }