[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / board / src / evmAM572x / evmAM572x_pll.c
1 /******************************************************************************
2 * Copyright (c) 2010-2015 Texas Instruments Incorporated - http://www.ti.com
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
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13 * documentation and/or other materials provided with the
14 * distribution.
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17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *****************************************************************************/
34 #include "board_cfg.h"
35 #include "board_internal.h"
37 /**
38 * \brief This structure defines the various Configuration Parameters for
39 * a DPLL.
40 */
41 typedef struct {
42 Uint32 mult;
43 /**< Multiplier(m) Value */
44 Uint32 div;
45 /**< Divider(n) Value */
46 Uint32 dccEnable;
47 /**< Divider(n) Value */
48 Uint32 autoDpllMode;
49 /**< Auto DPLL Mode, refer to enum #sbllibAutoDpllMode_t for values */
50 Uint32 divM2;
51 /**< M2 Divider Value */
52 Uint32 divM3;
53 /**< M3 Divider Value */
54 Uint32 divH11;
55 /**< H11 Divider Value */
56 Uint32 divH12;
57 /**< H12 Divider Value */
58 Uint32 divH13;
59 /**< H13 Divider Value */
60 Uint32 divH14;
61 /**< H14 Divider Value */
62 Uint32 divH21;
63 /**< H21 Divider Value */
64 Uint32 divH22;
65 /**< H22 Divider Value */
66 Uint32 divH23;
67 /**< H23 Divider Value */
68 Uint32 divH24;
69 /**< H24 Divider Value */
70 } pllcParam;
72 /**
73 * \brief This structure defines the various Configuration Parameters for
74 * a MPU DPLL.
75 */
76 typedef struct {
77 Uint32 mult;
78 /**< Multiplier(m) Value */
79 Uint32 div;
80 /**< Divider(n) Value */
81 Uint32 dccEnable;
82 /**< Divider(n) Value */
83 Uint32 divM2;
84 /**< M2 Divider Value */
85 } pllcMpuParam;
87 /**
88 * \brief This structure defines the various Configuration Parameters for
89 * a peripheral DPLL.
90 */
91 typedef struct {
92 Uint32 mult;
93 /**< Multiplier(m) Value */
94 Uint32 div;
95 /**< Divider(n) Value */
96 Uint32 divM2;
97 /**< M2 Divider Value */
98 Uint32 divM3;
99 /**< M3 Divider Value */
100 Uint32 divH11;
101 /**< H11 Divider Value */
102 Uint32 divH12;
103 /**< H12 Divider Value */
104 Uint32 divH13;
105 /**< H13 Divider Value */
106 Uint32 divH14;
107 /**< H14 Divider Value */
108 } pllcPerParam;
110 /**
111 * \brief This structure defines the various Configuration Parameters for
112 * a core DPLL.
113 */
114 typedef struct {
115 Uint32 l3ClkSel;
116 /**< L3 divider */
117 Uint32 l4ClkSel;
118 /**< L3 divider */
119 Uint32 mult;
120 /**< Multiplier(m) Value */
121 Uint32 div;
122 /**< Divider(n) Value */
123 Uint32 divM2;
124 /**< M2 Divider Value */
125 Uint32 divM3;
126 /**< M3 Divider Value */
127 Uint32 divH12;
128 /**< H12 Divider Value */
129 Uint32 divH13;
130 /**< H13 Divider Value */
131 Uint32 divH14;
132 /**< H14 Divider Value */
133 Uint32 divH22;
134 /**< H22 Divider Value */
135 Uint32 divH23;
136 /**< H23 Divider Value */
137 Uint32 divH24;
138 /**< H24 Divider Value */
139 } pllcCoreParam;
141 /**
142 * \brief This structure defines the various Configuration Parameters for
143 * an ABE DPLL.
144 */
145 typedef struct {
146 Uint32 mult;
147 /**< Multiplier(m) Value */
148 Uint32 div;
149 /**< Divider(n) Value */
150 Uint32 divM2;
151 /**< M2 Divider Value */
152 Uint32 divM3;
153 /**< M3 Divider Value */
154 } pllcAbeParam;
156 /**
157 * \brief This structure defines the various Configuration Parameters for
158 * an IVA DPLL.
159 */
160 typedef struct {
161 Uint32 mult;
162 /**< Multiplier(m) Value */
163 Uint32 div;
164 /**< Divider(n) Value */
165 Uint32 divM2;
166 /**< M2 Divider Value */
167 } pllcIvaParam;
169 /**
170 * \brief This structure defines the various Configuration Parameters for
171 * a GMAC DPLL.
172 */
173 typedef struct {
174 Uint32 mult;
175 /**< Multiplier(m) Value */
176 Uint32 div;
177 /**< Divider(n) Value */
178 Uint32 divM2;
179 /**< M2 Divider Value */
180 Uint32 divM3;
181 /**< M3 Divider Value */
182 Uint32 divH11;
183 /**< H11 Divider Value */
184 Uint32 divH12;
185 /**< H12 Divider Value */
186 Uint32 divH13;
187 /**< H13 Divider Value */
188 } pllcGmacParam;
190 /**
191 * \brief This structure defines the various Configuration Parameters for
192 * a PCIE DPLL.
193 */
194 typedef struct {
195 Uint32 mult;
196 /**< Multiplier(m) Value */
197 Uint32 div;
198 /**< Divider(n) Value */
199 Uint32 divM2;
200 /**< M2 Divider Value */
201 } pllcPcieParam;
203 /**
204 * \brief This structure defines the various Configuration Parameters for
205 * a DDR DPLL.
206 */
207 typedef struct {
208 Uint32 mult;
209 /**< Multiplier(m) Value */
210 Uint32 div;
211 /**< Divider(n) Value */
212 Uint32 divM2;
213 /**< M2 Divider Value */
214 Uint32 divM3;
215 /**< M3 Divider Value */
216 Uint32 divH11;
217 /**< H11 Divider Value */
218 } pllcDdrParam;
220 /**
221 * \brief This structure defines the various Configuration Parameters for
222 * a GPU DPLL.
223 */
224 typedef struct {
225 Uint32 mult;
226 /**< Multiplier(m) Value */
227 Uint32 div;
228 /**< Divider(n) Value */
229 Uint32 divM2;
230 /**< M2 Divider Value */
231 } pllcGpuParam;
233 /**
234 * \brief This structure defines the various Configuration Parameters for
235 * a DSP DPLL.
236 */
237 typedef struct {
238 Uint32 mult;
239 /**< Multiplier(m) Value */
240 Uint32 div;
241 /**< Divider(n) Value */
242 Uint32 divM2;
243 /**< M2 Divider Value */
244 Uint32 divM3;
245 /**< M3 Divider Value */
246 } pllcDspParam;
248 void pllcMpuUnlock(void);
250 void pllcMpuLock(void);
252 void pllcMpuConfigure(pllcMpuParam *mpuPllcParam);
254 void pllcIvaUnlock(void);
256 void pllcIvaLock(void);
258 void pllcIvaConfigure(pllcIvaParam *ivaPllcParam);
260 void pllcCoreUnlock(void);
262 void pllcCoreLock(void);
264 void pllcCoreConfigure(pllcCoreParam *corePllcParam);
266 void pllcAbeUnlock(void);
268 void pllcAbeLock(void);
270 void pllcAbeConfigure(pllcAbeParam *abePllcParam);
272 void pllcDdrUnlock(void);
274 void pllcDdrLock(void);
276 void pllcDdrConfigure(pllcDdrParam *ddrPllcParam);
278 void pllcDspUnlock(void);
280 void pllcDspLock(void);
282 void pllcDspConfigure(pllcDspParam *dspPllcParam);
284 void pllcGmacUnlock(void);
286 void pllcGmacLock(void);
288 void pllcGmacConfigure(pllcGmacParam *gmacPllcParam);
290 void pllcGpuUnlock(void);
292 void pllcGpuLock(void);
294 void pllcGpuConfigure(pllcGpuParam *gpuPllcParam);
296 void pllcPcieUnlock(void);
298 void pllcPcieLock(void);
300 void pllcPcieConfigure(pllcPcieParam *pciePllcParam);
302 void pllcPerUnlock(void);
304 void pllcPerLock(void);
306 void pllcPerConfigure(pllcPerParam *perPllcParam);
309 /* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
310 Board_STATUS Board_PLLInit(Uint32 opp)
311 {
312 pllcMpuParam mpuPllcParam;
313 pllcIvaParam ivaPllcParam;
314 pllcCoreParam corePllcParam;
315 pllcAbeParam abePllcParam;
316 pllcDdrParam ddrPllcParam;
317 pllcDspParam dspPllcParam;
318 pllcGmacParam gmacPllcParam;
319 pllcGpuParam gpuPllcParam;
320 pllcPcieParam pciePllcParam;
321 pllcPerParam perPllcParam;
322 CSL_ckgen_prmRegs *hCkgenPrm =
323 (CSL_ckgen_prmRegs *) CSL_MPU_CKGEN_PRM_REGS;
325 if (OPP_HIGH == opp)
326 {
327 /* 1500MHz at 20MHz sys_clk */
328 mpuPllcParam.mult = 600U;
329 mpuPllcParam.div = 7U;
330 mpuPllcParam.dccEnable = 1U;
331 mpuPllcParam.divM2 = 1U;
332 }
333 else if (OPP_OD == opp)
334 {
335 /* 1176MHz at 20MHz sys_clk */
336 mpuPllcParam.mult = 294U;
337 mpuPllcParam.div = 4U;
338 mpuPllcParam.dccEnable = 0U;
339 mpuPllcParam.divM2 = 1U;
340 }
341 else
342 {
343 /* Default to OPP_NOM */
344 /* 1000MHz at 20MHz sys_clk */
345 mpuPllcParam.mult = 500U;
346 mpuPllcParam.div = 9U;
347 mpuPllcParam.dccEnable = 0U;
348 mpuPllcParam.divM2 = 1U;
349 }
351 pllcMpuUnlock();
352 pllcMpuConfigure(&mpuPllcParam);
353 pllcMpuLock();
355 if (OPP_HIGH == opp)
356 {
357 /* 532MHz at 20MHz sys_clk */
358 ivaPllcParam.mult = 266U;
359 ivaPllcParam.div = 4U;
360 ivaPllcParam.divM2 = 2U;
361 }
362 else if (OPP_OD == opp)
363 {
364 /* 430MHz at 20MHz sys_clk */
365 ivaPllcParam.mult = 172U;
366 ivaPllcParam.div = 3U;
367 ivaPllcParam.divM2 = 2U;
368 }
369 else
370 {
371 /* Default to OPP_NOM */
372 /* 388.3MHz at 20MHz sys_clk */
373 ivaPllcParam.mult = 233U;
374 ivaPllcParam.div = 3U;
375 ivaPllcParam.divM2 = 3U;
376 }
377 pllcIvaUnlock();
378 pllcIvaConfigure(&ivaPllcParam);
379 pllcIvaLock();
381 perPllcParam.mult = 0x60U;
382 perPllcParam.div = 4U;
383 perPllcParam.divM2 = 4U;
384 perPllcParam.divM3 = 1U;
385 perPllcParam.divH11 = 3U;
386 perPllcParam.divH12 = 4U;
387 perPllcParam.divH13 = 4U;
388 perPllcParam.divH14 = 2U;
389 pllcPerUnlock();
390 pllcPerConfigure(&perPllcParam);
391 pllcPerLock();
393 corePllcParam.l3ClkSel = 1U;
394 corePllcParam.l4ClkSel = 1U;
395 corePllcParam.mult = 0x10AU;
396 corePllcParam.div = 0x4U;
397 corePllcParam.divM2 = 2U;
398 corePllcParam.divM3 = 1U;
399 corePllcParam.divH12 = 4U;
400 corePllcParam.divH13 = 0x3EU;
401 corePllcParam.divH14 = 0x5U;
402 corePllcParam.divH22 = 0x5U;
403 corePllcParam.divH23 = 0x4U;
404 corePllcParam.divH24 = 0x6U;
405 pllcCoreUnlock();
406 pllcCoreConfigure(&corePllcParam);
407 pllcCoreLock();
409 hCkgenPrm->CM_CLKSEL_ABE_PLL_REF_REG = 0x00000000U;
411 abePllcParam.mult = 0x13U;
412 abePllcParam.div = 0x1U;
413 abePllcParam.divM2 = 1U;
414 abePllcParam.divM3 = 1U;
415 pllcAbeUnlock();
416 pllcAbeConfigure(&abePllcParam);
417 pllcAbeLock();
419 gmacPllcParam.mult = 0xFAU;
420 gmacPllcParam.div = 0x4U;
421 gmacPllcParam.divM2 = 0x4U;
422 gmacPllcParam.divM3 = 0xAU;
423 gmacPllcParam.divH11 = 0x28U;
424 gmacPllcParam.divH12 = 0x8U;
425 gmacPllcParam.divH13 = 0xAU;
426 pllcGmacUnlock();
427 pllcGmacConfigure(&gmacPllcParam);
428 pllcGmacLock();
430 if(OPP_HIGH == opp)
431 {
432 /* 532MHz at 20MHz sys_clk */
433 gpuPllcParam.mult = 266U;
434 gpuPllcParam.div = 4U;
435 gpuPllcParam.divM2 = 2U;
436 }
437 else if(OPP_OD == opp)
438 {
439 /* 500MHz at 20MHz sys_clk */
440 gpuPllcParam.mult = 200U;
441 gpuPllcParam.div = 3U;
442 gpuPllcParam.divM2 = 2U;
443 }
444 else
445 {
446 /* Default to OPP_NOM */
447 /* 425MHz at 20MHz sys_clk */
448 gpuPllcParam.mult = 170U;
449 gpuPllcParam.div = 3U;
450 gpuPllcParam.divM2 = 2U;
451 }
452 pllcGpuUnlock();
453 pllcGpuConfigure(&gpuPllcParam);
454 pllcGpuLock();
456 if(OPP_HIGH == opp)
457 {
458 /* 750MHz at 20MHz sys_clk */
459 dspPllcParam.mult = 150U;
460 dspPllcParam.div = 3U;
461 dspPllcParam.divM2 = 1U;
462 dspPllcParam.divM3 = 3U;
463 }
464 else if(OPP_OD == opp)
465 {
466 /* 500MHz at 20MHz sys_clk */
467 dspPllcParam.mult = 130U;
468 dspPllcParam.div = 3U;
469 dspPllcParam.divM2 = 1U;
470 dspPllcParam.divM3 = 3U;
471 }
472 else
473 {
474 /* Default to OPP_NOM */
475 /* 425MHz at 20MHz sys_clk */
476 dspPllcParam.mult = 150U;
477 dspPllcParam.div = 4U;
478 dspPllcParam.divM2 = 1U;
479 dspPllcParam.divM3 = 3U;
480 }
481 pllcDspUnlock();
482 pllcDspConfigure(&dspPllcParam);
483 pllcDspLock();
485 pciePllcParam.mult = 750U;
486 pciePllcParam.div = 9U;
487 pciePllcParam.divM2 = 15U;
488 pllcPcieUnlock();
489 pllcPcieConfigure(&pciePllcParam);
490 pllcPcieLock();
492 ddrPllcParam.mult = 0x10AU;
493 ddrPllcParam.div = 0x4U;
494 ddrPllcParam.divM2 = 0x2U;
495 ddrPllcParam.divM3 = 0x1U;
496 ddrPllcParam.divH11 = 0x8U;
497 pllcDdrUnlock();
498 pllcDdrConfigure(&ddrPllcParam);
499 pllcDdrLock();
500 return BOARD_SOK;
501 }
503 void CtrlLockMMR(void)
504 {
505 CSL_control_coreRegs *ctrlCoreReg =
506 (CSL_control_coreRegs *) CSL_MPU_CTRL_MODULE_CORE_CORE_REGISTERS_REGS;
508 /* unlock MMR1 space for region 0x0100 to 0x079F */
509 ctrlCoreReg->MMR_LOCK_1 = 438075716U;
510 /* unlock MMR2 space for region 0x07A0 to 0x0D9F */
511 ctrlCoreReg->MMR_LOCK_2 = 4260648240U;
512 /* unlock MMR3 space for region 0x0DA0 to 0x0FFF */
513 ctrlCoreReg->MMR_LOCK_3 = 451339040U;
514 /* unlock MMR4 space for region 0x1000 to 0x13FF */
515 ctrlCoreReg->MMR_LOCK_4 = 515838749U;
516 /* unlock MMR5 space for region 0x1400 to 0x1FFF */
517 ctrlCoreReg->MMR_LOCK_5 = 339706668U;
518 }
520 void pllcMpuUnlock(void)
521 {
522 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
523 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
525 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_MPU_REG,
526 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_MPU_REG_DPLL_EN,
527 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_MPU_REG_DPLL_EN_DPLL_LP_BYP_MODE);
528 }
530 void pllcMpuLock(void)
531 {
532 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
533 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
535 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_MPU_REG,
536 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_MPU_REG_DPLL_EN,
537 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_MPU_REG_DPLL_EN_DPLL_LOCK_MODE);
538 }
540 void pllcMpuConfigure(pllcMpuParam *mpuPllcParam)
541 {
542 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
543 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
545 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_MPU_REG,
546 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_MPU_REG_DPLL_DIV, mpuPllcParam->div);
547 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_MPU_REG,
548 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_MPU_REG_DPLL_MULT, mpuPllcParam->mult);
549 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_MPU_REG,
550 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_MPU_REG_DCC_EN, mpuPllcParam->dccEnable);
551 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_MPU_REG,
552 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_MPU_REG_DIVHS, mpuPllcParam->divM2);
553 }
555 void pllcIvaUnlock(void)
556 {
557 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
558 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
560 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_IVA_REG,
561 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_IVA_REG_DPLL_EN,
562 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_IVA_REG_DPLL_EN_DPLL_LP_BYP_MODE);
563 }
565 void pllcIvaLock(void)
566 {
567 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
568 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
570 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_IVA_REG,
571 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_IVA_REG_DPLL_EN,
572 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_IVA_REG_DPLL_EN_DPLL_LOCK_MODE);
573 }
575 void pllcIvaConfigure(pllcIvaParam *ivaPllcParam)
576 {
577 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
578 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
580 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_IVA_REG,
581 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_IVA_REG_DPLL_DIV, ivaPllcParam->div);
582 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_IVA_REG,
583 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_IVA_REG_DPLL_MULT, ivaPllcParam->mult);
584 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_IVA_REG,
585 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_IVA_REG_DIVHS, ivaPllcParam->divM2);
586 }
588 void pllcCoreUnlock(void)
589 {
590 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
591 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
593 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_CORE_REG,
594 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_CORE_REG_DPLL_EN,
595 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_CORE_REG_DPLL_EN_DPLL_LP_BYP_MODE);
596 }
598 void pllcCoreLock(void)
599 {
600 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
601 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
603 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_CORE_REG,
604 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_CORE_REG_DPLL_EN,
605 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_CORE_REG_DPLL_EN_DPLL_LOCK_MODE);
606 }
608 void pllcCoreConfigure(pllcCoreParam *corePllcParam)
609 {
610 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
611 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
613 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_CORE_REG,
614 CKGEN_CM_CORE_AON_CM_CLKSEL_CORE_REG_CLKSEL_L3, corePllcParam->l3ClkSel);
615 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_CORE_REG,
616 CKGEN_CM_CORE_AON_CM_CLKSEL_CORE_REG_CLKSEL_L4, corePllcParam->l4ClkSel);
617 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_CORE_REG,
618 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_CORE_REG_DPLL_DIV, corePllcParam->div);
619 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_CORE_REG,
620 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_CORE_REG_DPLL_MULT, corePllcParam->mult);
621 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_CORE_REG,
622 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_CORE_REG_DIVHS, corePllcParam->divM2);
623 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M3_DPLL_CORE_REG,
624 CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_CORE_REG_DIVHS, corePllcParam->divM3);
625 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H12_DPLL_CORE_REG,
626 CKGEN_CM_CORE_AON_CM_DIV_H12_DPLL_CORE_REG_DIVHS, corePllcParam->divH12);
627 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H13_DPLL_CORE_REG,
628 CKGEN_CM_CORE_AON_CM_DIV_H13_DPLL_CORE_REG_DIVHS, corePllcParam->divH13);
629 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H14_DPLL_CORE_REG,
630 CKGEN_CM_CORE_AON_CM_DIV_H14_DPLL_CORE_REG_DIVHS, corePllcParam->divH14);
631 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H22_DPLL_CORE_REG,
632 CKGEN_CM_CORE_AON_CM_DIV_H22_DPLL_CORE_REG_DIVHS, corePllcParam->divH22);
633 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H23_DPLL_CORE_REG,
634 CKGEN_CM_CORE_AON_CM_DIV_H23_DPLL_CORE_REG_DIVHS, corePllcParam->divH23);
635 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H24_DPLL_CORE_REG,
636 CKGEN_CM_CORE_AON_CM_DIV_H24_DPLL_CORE_REG_DIVHS, corePllcParam->divH24);
637 }
639 void pllcAbeUnlock(void)
640 {
641 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
642 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
644 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_ABE_REG,
645 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN,
646 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LP_BYP_MODE);
647 }
649 void pllcAbeLock(void)
650 {
651 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
652 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
654 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_ABE_REG,
655 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN,
656 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_ABE_REG_DPLL_EN_DPLL_LOCK_MODE);
657 }
659 void pllcAbeConfigure(pllcAbeParam *abePllcParam)
660 {
661 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
662 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
664 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_ABE_REG,
665 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_DIV, abePllcParam->div);
666 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_ABE_REG,
667 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_ABE_REG_DPLL_MULT, abePllcParam->mult);
668 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_ABE_REG,
669 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_ABE_REG_DIVHS, abePllcParam->divM2);
670 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M3_DPLL_ABE_REG,
671 CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_ABE_REG_DIVHS, abePllcParam->divM3);
672 }
674 void pllcDdrUnlock(void)
675 {
676 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
677 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
679 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_DDR_REG,
680 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DDR_REG_DPLL_EN,
681 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DDR_REG_DPLL_EN_DPLL_LP_BYP_MODE);
682 }
684 void pllcDdrLock(void)
685 {
686 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
687 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
689 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_DDR_REG,
690 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DDR_REG_DPLL_EN,
691 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DDR_REG_DPLL_EN_DPLL_LOCK_MODE);
692 }
694 void pllcDdrConfigure(pllcDdrParam *ddrPllcParam)
695 {
696 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
697 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
699 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_DDR_REG,
700 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_DDR_REG_DPLL_DIV, ddrPllcParam->div);
701 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_DDR_REG,
702 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_DDR_REG_DPLL_MULT, ddrPllcParam->mult);
703 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_DDR_REG,
704 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_DDR_REG_DIVHS, ddrPllcParam->divM2);
705 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M3_DPLL_DDR_REG,
706 CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_DDR_REG_DIVHS, ddrPllcParam->divM3);
707 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H11_DPLL_DDR_REG,
708 CKGEN_CM_CORE_AON_CM_DIV_H11_DPLL_DDR_REG_DIVHS, ddrPllcParam->divH11);
709 }
711 void pllcDspUnlock(void)
712 {
713 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
714 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
716 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_DSP_REG,
717 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DSP_REG_DPLL_EN,
718 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DSP_REG_DPLL_EN_DPLL_LP_BYP_MODE);
719 }
721 void pllcDspLock(void)
722 {
723 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
724 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
726 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_DSP_REG,
727 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DSP_REG_DPLL_EN,
728 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_DSP_REG_DPLL_EN_DPLL_LOCK_MODE);
729 }
731 void pllcDspConfigure(pllcDspParam *dspPllcParam)
732 {
733 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
734 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
736 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_DSP_REG,
737 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_DSP_REG_DPLL_DIV, dspPllcParam->div);
738 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_DSP_REG,
739 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_DSP_REG_DPLL_MULT, dspPllcParam->mult);
740 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_DSP_REG,
741 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_DSP_REG_DIVHS, dspPllcParam->divM2);
742 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M3_DPLL_DSP_REG,
743 CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_DSP_REG_DIVHS, dspPllcParam->divM3);
744 }
746 void pllcGmacUnlock(void)
747 {
748 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
749 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
751 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_GMAC_REG,
752 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GMAC_REG_DPLL_EN,
753 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GMAC_REG_DPLL_EN_DPLL_LP_BYP_MODE);
754 }
756 void pllcGmacLock(void)
757 {
758 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
759 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
761 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_GMAC_REG,
762 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GMAC_REG_DPLL_EN,
763 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GMAC_REG_DPLL_EN_DPLL_LOCK_MODE);
764 }
766 void pllcGmacConfigure(pllcGmacParam *gmacPllcParam)
767 {
768 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
769 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
771 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_GMAC_REG,
772 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_GMAC_REG_DPLL_DIV, gmacPllcParam->div);
773 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_GMAC_REG,
774 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_GMAC_REG_DPLL_MULT, gmacPllcParam->mult);
775 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_GMAC_REG,
776 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_GMAC_REG_DIVHS, gmacPllcParam->divM2);
777 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M3_DPLL_GMAC_REG,
778 CKGEN_CM_CORE_AON_CM_DIV_M3_DPLL_GMAC_REG_DIVHS, gmacPllcParam->divM3);
779 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H11_DPLL_GMAC_REG,
780 CKGEN_CM_CORE_AON_CM_DIV_H11_DPLL_GMAC_REG_DIVHS, gmacPllcParam->divH11);
781 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H12_DPLL_GMAC_REG,
782 CKGEN_CM_CORE_AON_CM_DIV_H12_DPLL_GMAC_REG_DIVHS, gmacPllcParam->divH12);
783 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_H13_DPLL_GMAC_REG,
784 CKGEN_CM_CORE_AON_CM_DIV_H13_DPLL_GMAC_REG_DIVHS, gmacPllcParam->divH13);
785 }
787 void pllcGpuUnlock(void)
788 {
789 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
790 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
792 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_GPU_REG,
793 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GPU_REG_DPLL_EN,
794 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GPU_REG_DPLL_EN_DPLL_LP_BYP_MODE);
795 }
797 void pllcGpuLock(void)
798 {
799 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
800 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
802 CSL_FINS(ckgenCmCoreAonReg->CM_CLKMODE_DPLL_GPU_REG,
803 CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GPU_REG_DPLL_EN,
804 CSL_CKGEN_CM_CORE_AON_CM_CLKMODE_DPLL_GPU_REG_DPLL_EN_DPLL_LOCK_MODE);
805 }
807 void pllcGpuConfigure(pllcGpuParam *gpuPllcParam)
808 {
809 CSL_ckgen_cm_core_aonRegs *ckgenCmCoreAonReg =
810 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
812 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_GPU_REG,
813 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_GPU_REG_DPLL_DIV, gpuPllcParam->div);
814 CSL_FINS(ckgenCmCoreAonReg->CM_CLKSEL_DPLL_GPU_REG,
815 CKGEN_CM_CORE_AON_CM_CLKSEL_DPLL_GPU_REG_DPLL_MULT, gpuPllcParam->mult);
816 CSL_FINS(ckgenCmCoreAonReg->CM_DIV_M2_DPLL_GPU_REG,
817 CKGEN_CM_CORE_AON_CM_DIV_M2_DPLL_GPU_REG_DIVHS, gpuPllcParam->divM2);
818 }
820 void pllcPcieUnlock(void)
821 {
822 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =
823 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;
825 CSL_FINS(ckgenCmCoreReg->CM_CLKMODE_DPLL_PCIE_REF_REG,
826 CKGEN_CM_CORE_CM_CLKMODE_DPLL_PCIE_REF_REG_DPLL_EN,
827 CSL_CKGEN_CM_CORE_CM_CLKMODE_DPLL_PCIE_REF_REG_DPLL_EN_DPLL_LP_BYP_MODE);
828 }
830 void pllcPcieLock(void)
831 {
832 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =
833 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;
835 CSL_FINS(ckgenCmCoreReg->CM_CLKMODE_DPLL_PCIE_REF_REG,
836 CKGEN_CM_CORE_CM_CLKMODE_DPLL_PCIE_REF_REG_DPLL_EN,
837 CSL_CKGEN_CM_CORE_CM_CLKMODE_DPLL_PCIE_REF_REG_DPLL_EN_DPLL_LOCK_MODE);
838 }
840 void pllcPcieConfigure(pllcPcieParam *pciePllcParam)
841 {
842 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =
843 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;
845 CSL_FINS(ckgenCmCoreReg->CM_CLKSEL_DPLL_PCIE_REF_REG,
846 CKGEN_CM_CORE_CM_CLKSEL_DPLL_PCIE_REF_REG_DPLL_DIV, pciePllcParam->div);
847 CSL_FINS(ckgenCmCoreReg->CM_CLKSEL_DPLL_PCIE_REF_REG,
848 CKGEN_CM_CORE_CM_CLKSEL_DPLL_PCIE_REF_REG_DPLL_MULT, pciePllcParam->mult);
849 CSL_FINS(ckgenCmCoreReg->CM_DIV_M2_DPLL_PCIE_REF_REG,
850 CKGEN_CM_CORE_CM_DIV_M2_DPLL_PCIE_REF_REG_DIVHS, pciePllcParam->divM2);
851 }
853 void pllcPerUnlock(void)
854 {
855 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =
856 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;
858 CSL_FINS(ckgenCmCoreReg->CM_CLKMODE_DPLL_PER_REG,
859 CKGEN_CM_CORE_CM_CLKMODE_DPLL_PER_REG_DPLL_EN,
860 CSL_CKGEN_CM_CORE_CM_CLKMODE_DPLL_PER_REG_DPLL_EN_DPLL_LP_BYP_MODE);
861 }
863 void pllcPerLock(void)
864 {
865 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =
866 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;
868 CSL_FINS(ckgenCmCoreReg->CM_CLKMODE_DPLL_PER_REG,
869 CKGEN_CM_CORE_CM_CLKMODE_DPLL_PER_REG_DPLL_EN,
870 CSL_CKGEN_CM_CORE_CM_CLKMODE_DPLL_PER_REG_DPLL_EN_DPLL_LOCK_MODE);
871 }
873 void pllcPerConfigure(pllcPerParam *perPllcParam)
874 {
875 CSL_ckgen_cm_coreRegs *ckgenCmCoreReg =
876 (CSL_ckgen_cm_coreRegs *) CSL_MPU_CKGEN_CM_CORE_REGS;
878 CSL_FINS(ckgenCmCoreReg->CM_CLKSEL_DPLL_PER_REG,
879 CKGEN_CM_CORE_CM_CLKSEL_DPLL_PER_REG_DPLL_DIV, perPllcParam->div);
880 CSL_FINS(ckgenCmCoreReg->CM_CLKSEL_DPLL_PER_REG,
881 CKGEN_CM_CORE_CM_CLKSEL_DPLL_PER_REG_DPLL_MULT, perPllcParam->mult);
882 CSL_FINS(ckgenCmCoreReg->CM_DIV_M2_DPLL_PER_REG,
883 CKGEN_CM_CORE_CM_DIV_M2_DPLL_PER_REG_DIVHS, perPllcParam->divM2);
884 CSL_FINS(ckgenCmCoreReg->CM_DIV_M3_DPLL_PER_REG,
885 CKGEN_CM_CORE_CM_DIV_M3_DPLL_PER_REG_DIVHS, perPllcParam->divM3);
886 CSL_FINS(ckgenCmCoreReg->CM_DIV_H11_DPLL_PER_REG,
887 CKGEN_CM_CORE_CM_DIV_H11_DPLL_PER_REG_DIVHS, perPllcParam->divH11);
888 CSL_FINS(ckgenCmCoreReg->CM_DIV_H12_DPLL_PER_REG,
889 CKGEN_CM_CORE_CM_DIV_H12_DPLL_PER_REG_DIVHS, perPllcParam->divH12);
890 CSL_FINS(ckgenCmCoreReg->CM_DIV_H13_DPLL_PER_REG,
891 CKGEN_CM_CORE_CM_DIV_H13_DPLL_PER_REG_DIVHS, perPllcParam->divH13);
892 CSL_FINS(ckgenCmCoreReg->CM_DIV_H14_DPLL_PER_REG,
893 CKGEN_CM_CORE_CM_DIV_H14_DPLL_PER_REG_DIVHS, perPllcParam->divH14);
894 }