[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / board / src / evmKeystone / board_utils.c
1 /**
2 * @file board_utils.c
3 *
4 * @brief This file includes the Keystone board level functions
5 */
6 /*
7 * Copyright (c) 2015, Texas Instruments Incorporated
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
35 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
38 #include <ti/csl/csl_bootcfg.h>
39 #include <ti/csl/csl_bootcfgAux.h>
40 #if defined (_TMS320C6X)
41 #include <ti/csl/csl_chipAux.h>
42 #endif
44 #include "board_utils.h"
46 /**
47 * \brief This API gets the input clock frequency.
48 *
49 * \param pll PLL controller type.
50 *
51 * \return input clock to the PLL controller.
52 *
53 * \note This API gets the input clock frequency based on the
54 * PLL controller type.\n
55 */
56 /** ============================================================================
57 * @n@b BOARD_getExternalClk
58 *
59 * @b Description
60 * @n This function is used to get the exteranl clock frequency.
61 *
62 *
63 * @b Arguments
64 * @verbatim
65 pll Specifies the PLL controller type.
66 @endverbatim
67 *
68 * <b> Return Value </b>
69 * @n external clock frequency to the PLL controller, if 0, means failure
70 *
71 * <b> Pre Condition </b>
72 * @n None
73 *
74 * <b> Post Condition </b>
75 * @n None
76 *
77 * @b Affects
78 * @n None.
79 *
80 * @b Example
81 * @verbatim
82 uint32_t ext_clk;
84 ext_clk = BOARD_getExternalClk(CSL_PLL_SYS);
86 @endverbatim
87 * ===========================================================================
88 */
89 uint32_t BOARD_getExternalClk(CSL_PllcType pll)
90 {
91 return Board_ext_clk[pll];
92 }
94 /** ============================================================================
95 * @n@b BOARD_initPerfCounters
96 *
97 * @b Description
98 * @n This function enables the A15 performance counters.
99 *
100 *
101 * @b Arguments
103 * <b> Return Value </b>
104 * @n None
105 *
106 * <b> Pre Condition </b>
107 * @n None
108 *
109 * <b> Post Condition </b>
110 * @n None
111 *
112 * @b Affects
113 * @n None.
114 *
115 * @b Example
116 * @verbatim
117 BOARD_initPerfCounters();
118 @endverbatim
119 * ===========================================================================
120 */
121 void BOARD_initPerfCounters()
122 {
123 #if defined (_TMS320C6X) || defined(__TI_ARM_V7M4__)
124 // Do nothing for C6x and M4 cores
125 #else
126 /* PMCR
127 31......24 23......16 15....11 10.....6 5 4 3 2 1 0
128 IMP IDCODE N Res DP X D C P E
129 [31:24] IMP: Implementer code; read-only
130 [23:16] IDCODE: Identification code; read-only
131 [15:11] N: Number of event counters; read-only
132 [10:6] Reserved
133 [5] DP: Disable cycle counter in prohibited regions; r/w
134 [4] X: Export enable; r/w
135 [3] D: Clock divider - PMCCNTR counts every 64 clock cycles when enabled; r/w
136 [2] C: Clock counter reset; write-only
137 [1] P: Event counter reset; write-only
138 [0] E: Enable all counters; r/w
139 */
140 __asm__ __volatile__ ("MCR p15, 0, %0, c9, c12, 0\t\n" :: "r"(0x17));
142 /* PMCNTENSET - Count Enable Set Register */
143 __asm__ __volatile__ ("MCR p15, 0, %0, c9, c12, 1\t\n" :: "r"(0x8000000f));
145 /* PMOVSR - Overflow Flag Status Register */
146 __asm__ __volatile__ ("MCR p15, 0, %0, c9, c12, 3\t\n" :: "r"(0x8000000f));
147 #endif
148 }
150 static uint32_t readTime32(void)
151 {
152 uint32_t timeVal;
154 #if defined (_TMS320C6X)
155 timeVal = TSCL;
156 #else
157 __asm__ __volatile__ ("MRC p15, 0, %0, c9, c13, 0\t\n": "=r"(timeVal));
158 #endif
159 return timeVal;
160 }
162 /** ============================================================================
163 * @n@b BOARD_delay
164 *
165 * @b Description
166 * @n This function delays a certain period of time in micro seconds.
167 *
168 *
169 * @b Arguments
170 * @verbatim
171 usecs Specifies the time to delay in micro second.
172 @endverbatim
173 * @n To prevent 32-bit counter roll over, the delay time should be less than 2^32/freq_in_mhz (usec)
174 * e.g. for 1000Mhz PLL clock, delay time should be less than ~4.2 seconds.
175 *
176 * <b> Return Value </b>
177 * @n None
178 *
179 * <b> Pre Condition </b>
180 * @n None
181 *
182 * <b> Post Condition </b>
183 * @n None
184 *
185 * @b Affects
186 * @n None.
187 *
188 * @b Example
189 * @verbatim
190 uint32_t delay = 5;
192 BOARD_delay(delay);
194 @endverbatim
195 * ===========================================================================
196 */
197 void BOARD_delay(uint32_t usecs)
198 {
199 uint32_t ext_clk, freq, start, delayCount;
200 CSL_PllcType pllType;
202 #if defined (_TMS320C6X)
203 pllType = CSL_PLL_SYS;
204 CSL_chipWriteTSCL(0);
205 #else
206 pllType = CSL_PLL_ARM;
207 #endif
208 start = readTime32();
209 ext_clk = BOARD_getExternalClk(pllType);
210 freq = CSL_BootCfgGetPllFreq(pllType, ext_clk);
212 delayCount = usecs * (freq / 1000000);
213 while ((readTime32() - start) < delayCount);
214 }