[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / board / src / flash / platform_flash / platform_internal.h
1 /*
2 * Copyright (c) 2011-2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 * @file platform_internal.h
36 *
37 * @brief Private definitions for the Platform Library.
38 *
39 * ============================================================================
40 */
42 #ifndef _PLATFORM_INTERNAL_H_
43 #define _PLATFORM_INTERNAL_H_
45 /********************************************************************************************
46 * BUILD OPTIONS FOR THE LIBRARY *
47 *******************************************************************************************/
49 /***
50 * @brief The following flags are used for controlling the build of Platform Library
51 */
53 /* brief Platform Library version number */
54 #define PLATFORM_LIB_VERSION "3.02.00.00"
56 /* Turn on and off debug statements (may not be safe in certain contexts) */
57 #define PLATFORM_DEBUG 0
59 #define PLATFORM_VERSTRING_IN 0
60 #define PLATFORM_INIT_IN 1
61 #define PLATFORM_GETINFO_IN 0
62 #define PLATFORM_GETCOREID_IN 0
63 #define PLATFORM_GETSWITCHSTATE_IN 0
64 #define PLATFORM_GETMACADDR_IN 0
65 #define PLATFORM_GETPHYADDR_IN 0
66 #define PLATFORM_PHYLINKSTATUS_IN 0
67 #define PLATFORM_DELAY_IN 1
68 #define PLATFORM_LED_IN 0
69 #define PLATFORM_WRITE_IN 1
70 #define PLATFORM_READ_IN 0
71 #define PLATFORM_EXTMEMTEST_IN 0
72 #define PLATFORM_I2C_EEPROM_WRITE_IN 1
73 #define PLATFORM_I2C_EEPROM_IN 1
74 #define PLATFORM_UART_IN 0
75 #define PLATFORM_NOR_IN 1
76 #define PLATFORM_NOR_READ_IN 1
77 #define PLATFORM_NOR_WRITE_IN 1
78 #define PLATFORM_NAND_IN 1
79 #define PLATFORM_NAND_READ_IN 1
80 #define PLATFORM_NAND_WRITE_IN 1
81 #define PLATFORM_NAND_ECC_IN 1
82 #define PLATFORM_SEMLOCK_IN 0
83 #define PLATFORM_CACHE_IN 0
84 #define PLATFORM_GPIO_IN 1
85 #define PLATFORM_I2C_IN 1
86 #define PLATFORM_I2C_IO_EXP_IN 0
87 #define PLATFORM_AUDIO 0
88 #define PLATFORM_AUDIO_ADC 0
89 #define PLATFORM_AUDIO_DAC 0
90 #define PLATFORM_AUDIO_DIR 0
91 #define PLATFORM_MMCHS_IN 0
92 #define PLATFORM_DSS_IN 0
93 #define PLATFORM_DCAN_IN 0
94 #define PLATFORM_QSPI_FLASH_IN 1
95 #define PLATFORM_QSPI_FLASH_READ_IN 1
96 #define PLATFORM_QSPI_FLASH_WRITE_IN 1
98 #if 0
99 /* These flags compile in and out functionality offered by the library allowing you to control
100 * the size of the code that is included.
101 */
102 #ifdef _PLATFORM_LITE_
103 /*
104 * Build a version of Platform Library suitable for use in an EEPROM or other small application.
105 * (likely needs tailoring to the specific application if size matters)
106 */
107 #define PLATFORM_VERSTRING_IN 1
108 #define PLATFORM_INIT_IN 1
109 #define PLATFORM_GETINFO_IN 1
110 #define PLATFORM_GETCOREID_IN 1
111 #define PLATFORM_GETSWITCHSTATE_IN 0
112 #define PLATFORM_GETMACADDR_IN 1
113 #define PLATFORM_GETPHYADDR_IN 0
114 #define PLATFORM_PHYLINKSTATUS_IN 0
115 #define PLATFORM_DELAY_IN 1
116 #define PLATFORM_LED_IN 1
117 #define PLATFORM_WRITE_IN 0
118 #define PLATFORM_READ_IN 0
119 #define PLATFORM_EXTMEMTEST_IN 1
120 #define PLATFORM_I2C_EEPROM_IN 1
121 #define PLATFORM_I2C_EEPROM_WRITE_IN 1
122 #define PLATFORM_UART_IN 1
123 #define PLATFORM_NOR_IN 1
124 #define PLATFORM_NOR_READ_IN 1
125 #define PLATFORM_NOR_WRITE_IN 0
126 #define PLATFORM_NAND_IN 1
127 #define PLATFORM_NAND_READ_IN 1
128 #define PLATFORM_NAND_WRITE_IN 0
129 #define PLATFORM_NAND_ECC_IN 0
130 #define PLATFORM_SEMLOCK_IN 0
131 #define PLATFORM_CACHE_IN 0
132 #define PLATFORM_GPIO_IN 1
133 #define PLATFORM_I2C_IN 1
134 #define PLATFORM_I2C_IO_EXP_IN 1
135 #define PLATFORM_AUDIO 1
136 #define PLATFORM_AUDIO_ADC 1
137 #define PLATFORM_AUDIO_DAC 1
138 #define PLATFORM_AUDIO_DIR 1
139 #define PLATFORM_MMCHS_IN 1
140 #define PLATFORM_DSS_IN 0
141 #define PLATFORM_DCAN_IN 0
142 #define PLATFORM_QSPI_FLASH_IN 1
143 #define PLATFORM_QSPI_FLASH_READ_IN 1
144 #define PLATFORM_QSPI_FLASH_WRITE_IN 1
145 #else
146 /*
147 * Build the FULL version of Platform Library
148 */
149 #define PLATFORM_VERSTRING_IN 1
150 #define PLATFORM_INIT_IN 1
151 #define PLATFORM_GETINFO_IN 1
152 #define PLATFORM_GETCOREID_IN 1
153 #define PLATFORM_GETSWITCHSTATE_IN 1
154 #define PLATFORM_GETMACADDR_IN 1
155 #define PLATFORM_GETPHYADDR_IN 1
156 #define PLATFORM_PHYLINKSTATUS_IN 1
157 #define PLATFORM_DELAY_IN 1
158 #define PLATFORM_LED_IN 1
159 #define PLATFORM_WRITE_IN 1
160 #define PLATFORM_READ_IN 1
161 #define PLATFORM_EXTMEMTEST_IN 1
162 #define PLATFORM_I2C_EEPROM_WRITE_IN 1
163 #define PLATFORM_I2C_EEPROM_IN 1
164 #define PLATFORM_UART_IN 1
165 #define PLATFORM_NOR_IN 1
166 #define PLATFORM_NOR_READ_IN 1
167 #define PLATFORM_NOR_WRITE_IN 1
168 #define PLATFORM_NAND_IN 1
169 #define PLATFORM_NAND_READ_IN 1
170 #define PLATFORM_NAND_WRITE_IN 1
171 #define PLATFORM_NAND_ECC_IN 0
172 #define PLATFORM_SEMLOCK_IN 1
173 #define PLATFORM_CACHE_IN 1
174 #define PLATFORM_GPIO_IN 1
175 #define PLATFORM_I2C_IN 1
176 #define PLATFORM_I2C_IO_EXP_IN 1
177 #define PLATFORM_AUDIO 1
178 #define PLATFORM_AUDIO_ADC 1
179 #define PLATFORM_AUDIO_DAC 1
180 #define PLATFORM_AUDIO_DIR 1
181 #define PLATFORM_MMCHS_IN 1
182 #define PLATFORM_DSS_IN 1
183 #define PLATFORM_DCAN_IN 1
184 #define PLATFORM_QSPI_FLASH_IN 1
185 #define PLATFORM_QSPI_FLASH_READ_IN 1
186 #define PLATFORM_QSPI_FLASH_WRITE_IN 1
187 #endif
188 #endif
190 #if (PLATFORM_DEBUG && !PLATFORM_WRITE_IN)
191 #error You must enable PLATFORM_WRITE to turn on DEBUG
192 #endif
194 #if (PLATFORM_DEBUG)
195 #define IFPRINT(x) (x)
196 #else
197 #define IFPRINT(x)
198 #endif
200 /* This flag implements a workaround to re-initialize PLL and DDR
201 if DDR test after DDR initialization */
202 #undef PLATFORM_PLL_REINIT
203 #define PLL_REINIT_DDR3_TEST_START_ADDR (0x80000000)
204 #define PLL_REINIT_DDR3_TEST_END_ADDR (PLL_REINIT_DDR3_TEST_START_ADDR + (128 *1024))
206 /********************************************************************************************
207 * Includes for the Library Routines *
208 *******************************************************************************************/
210 #include "types.h"
211 #include "csl_types.h"
212 #include "soc.h"
214 #include "platform.h"
216 #include <stdio.h>
217 #include <stdlib.h>
218 #include <string.h>
220 #include "csl_chip.h"
221 #include "csl_chipAux.h"
222 #include "csl_semAux.h"
223 #include "cslr_device.h"
224 #include "cslr_psc.h"
225 #include "csl_psc.h"
226 #include "cslr_gpmc.h"
227 #include "cslr_elm.h"
228 #include "cslr_i2c.h"
229 #include "csl_cpsw.h"
230 #include "csl_cpsgmii.h"
231 #include "csl_cpsgmiiAux.h"
232 #include "csl_mdio.h"
233 #include "csl_mdioAux.h"
234 #include "cslr_uart.h"
235 #include "csl_gpioAux.h"
236 #include "csl_pscAux.h"
237 #include "csl_bootcfg.h"
238 #include "csl_bootcfgAux.h"
239 #include "cslr_spi.h"
240 #include "csl_xmcAux.h"
241 #include "csl_serdes_ethernet.h"
242 #include "cslr_mmchs.h"
243 #include "cslr_dss.h"
244 #include "cslr_qspi.h"
245 #include "cslr_ecap.h"
246 #include "cslr_pwmss.h"
247 #include "cslr_mlb.h"
249 #include "evmc66x_gpio.h"
250 #include "evmc66x_i2c.h"
251 #include "evmc66x_i2c_eeprom.h"
252 #include "evmc66x_elm.h"
253 #include "evmc66x_spi.h"
254 #include "evmc66x_pllc.h"
255 #include "evmc66x_gpmc.h"
256 #include "evmc66x_nand_gpmc.h"
257 #include "evmc66x_nand.h"
258 #include "evmc66x_nor.h"
259 #include "evmc66x_qspi.h"
260 #include "evmc66x_pinmux.h"
261 #include "evmc66x_qspi_norflash.h"
262 #if 0
263 #include "evmc66x_uart.h"
264 #include "evmc66x_gpio.h"
265 #include "evmc66x_bmc.h"
266 #include "evmc66x_gpmc.h"
267 #include "evmc66x_elm.h"
268 #include "evmc66x_spi.h"
269 #include "evmc66x_pllc.h"
270 #include "evmc66x_i2c_eeprom.h"
271 #include "evmc66x_i2c_ioexpander.h"
272 #include "evmc66x_nand_gpmc.h"
273 #include "evmc66x_nand.h"
274 #include "evmc66x_nor.h"
275 #include "evmc66x_audio_dc_dac.h"
276 #include "evmc66x_audio_dc_adc.h"
277 #include "evmc66x_mmchs.h"
278 #include "evmc66x_mmchs_card.h"
279 #include "evmc66x_dcan.h"
280 #include "evmc66x_dss.h"
281 #include "evmc66x_dss_panel.h"
282 #include "evmc66x_hdmi_panel.h"
283 #include "evmc66x_qspi.h"
284 #include "evmc66x_hdmi.h"
285 #include "evmc66x_touch.h"
286 #include "evmc66x_pinmux.h"
287 #include "platform_audio.h"
288 #include "evmc66x_qspi_norflash.h"
289 #include "evmc66x_pwm.h"
290 #endif
292 /********************************************************************************************
293 * Platform Specific Declarations *
294 *******************************************************************************************/
296 #define PLATFORM_INFO_CPU_NAME "TCI66AK2G02"
297 #define PLATFORM_INFO_BOARD_NAME "TMDXEVM66AK2G02"
299 #define MEGM_REV_ID_REGISTER (0x01812000)
300 #define MEGM_REV_ID_MAJ_MASK (0xFFFF0000)
301 #define MEGM_REV_ID_MAJ_SHIFT (16)
302 #define MEGM_REV_ID_MIN_MASK (0x0000FFFF)
303 #define MEGM_REV_ID_MIN_SHIFT (0)
305 /* Default UART baudrate value */
306 #define PLATFORM_UART_BAUDRATE_val (19200)
308 /* LED Definitions */
309 #define PLATFORM_BMC_LED_COUNT (4)
310 #define PLATFORM_SOC_LED_COUNT (5)
311 #define PLATFORM_I2C_LED_COUNT (0)
312 #define PLATFORM_TOTAL_LED_COUNT (PLATFORM_BMC_LED_COUNT + \
313 PLATFORM_I2C_LED_COUNT + \
314 PLATFORM_SOC_LED_COUNT)
316 #define PLATFORM_SOC_LED0 (0)
317 #define PLATFORM_SOC_LED1 (1)
318 #define PLATFORM_SOC_LED2 (2)
319 #define PLATFORM_SOC_LED3 (3)
320 #define PLATFORM_SOC_LED4 (4)
322 #define SOC_LED0_GPIO (GPIO_PIN_108)
323 #define SOC_LED1_GPIO (GPIO_PIN_11)
324 #define SOC_LED0_PADCONFIG (139)
325 #define SOC_LED1_PADCONFIG (186)
327 /* Number of cores on the platform */
328 #define PLATFORM_CORE_COUNT (1)
330 /* Memory Sections */
331 #define PLATFORM_L1P_BASE_ADDRESS (CSL_C66X_COREPAC_0_L1P_SRAM_REGS)
332 #define PLATFORM_L1P_SIZE (CSL_C66X_COREPAC_0_L1P_SRAM_REGS_SIZE) /* 32K bytes */
333 #define PLATFORM_L1D_BASE_ADDRESS (CSL_GEM_INTERNAL_DSP0_L1D_SRAM_RAM_REGS)
334 #define PLATFORM_L1D_SIZE (CSL_GEM_INTERNAL_DSP0_L1D_SRAM_RAM_REGS_SIZE) /* 32K bytes */
335 #define PLATFORM_DDR3_SDRAM_START 0x80000000
336 #define PLATFORM_DDR3_SDRAM_END 0x9FFFFFFF /* DDR3A 1024 MB*/
338 /* AT24CM01 EEPROM */
339 #define PLATFORM_I2C_EEPROM_MANUFACTURER_ID (0x01)
340 #define PLATFORM_I2C_EEPROM_DEVICE_ID_1 (0x50)
341 #define PLATFORM_I2C_EEPROM_DEVICE_ID_2 (0x51)
343 /* UART port number for sending debug messages */
344 /* Set to UART_PORT_0 for DB9 connector and UART_PORT_2 for console header */
345 #define PLATFORM_UART_DBG_PORT (UART_PORT_0)
347 /********************************************************************************************
348 * General Declarations *
349 *******************************************************************************************/
351 /* Macro to calclate the size of default register Array */
352 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
354 /* Size of a string we can output with platform_write */
355 #define MAX_WRITE_LEN 200
357 /* Device Tables */
358 #if (PLATFORM_NAND_IN)
359 extern PLATFORM_DEVICE_info gDeviceNand;
360 #endif
362 #if (PLATFORM_NOR_IN)
363 extern PLATFORM_DEVICE_info gDeviceNor;
364 #endif
366 #if (PLATFORM_I2C_EEPROM_IN)
367 extern PLATFORM_DEVICE_info gDeviceEeprom0;
368 extern PLATFORM_DEVICE_info gDeviceEeprom1;
369 #endif
371 #define PLATFORM_READ_DELAY (30000000)
373 /**
374 * Handle to access PSC registers.
375 */
376 #define hPscCfg ((CSL_PscRegs*)CSL_PSC_REGS)
378 /* Boot Cfg Registers */
379 #define DEVSTAT_REG (*((volatile uint32_t *) 0x02620020))
381 #define MAX_SN_SIZE (10) /* Maximum number of the chars of Serial Number for the EVM */
382 #define MAX_SN_STORE_SIZE (128) /* Maximum size in bytes to store the serial number info */
384 /* Size of MAC address in EEPROM at slave address 0x51 */
385 #define MACADDRESS_SIZE (12)
386 /* Offset of MAC address in EEPROM at slave address 0x51 */
387 #define MAC_OFFSET (0xF400)
389 /* Registers to enable or disable memory ECC for L1, L2 and MSMC memories */
390 #define L1PEDSTAT (0x01846404)
391 #define L1PEDCMD (0x01846408)
392 #define L1PEDADDR (0x0184640C)
393 #define L2EDSTAT (0x01846004)
394 #define L2EDCMD (0x01846008)
395 #define L2EDADDR (0x0184600C)
396 #define L2EDCPEC (0x01846018)
397 #define L2EDCNEC (0x0184601C)
398 #define L2EDCEN (0x01846030)
399 #define SMCERRAR (0x0BC00008)
400 #define SMCERRXR (0x0BC0000C)
401 #define SMEDCC (0x0BC00010)
402 #define SMCEA (0x0BC00014)
403 #define SMSECC (0x0BC00018)
405 #define DDR_CFG_DELAY (200)
407 /* DDR3A definitions */
408 #define DDR3A_EMIF_CTRL_BASE (0x21010000)
409 #define DDR3A_EMIF_DATA_BASE (0x80000000)
410 #define DDR3A_DDRPHYC (0x02329000)
413 #define DDRPHY_PIR_OFFSET (0x04)
414 #define DDRPHY_PGCR0_OFFSET (0x08)
415 #define DDRPHY_PGCR1_OFFSET (0x0C)
416 #define DDRPHY_PGSR0_OFFSET (0x10)
417 #define DDRPHY_PGSR1_OFFSET (0x14)
418 #define DDRPHY_PLLCR_OFFSET (0x18)
419 #define DDRPHY_PTR0_OFFSET (0x1C)
420 #define DDRPHY_PTR1_OFFSET (0x20)
421 #define DDRPHY_PTR2_OFFSET (0x24)
422 #define DDRPHY_PTR3_OFFSET (0x28)
423 #define DDRPHY_PTR4_OFFSET (0x2C)
424 #define DDRPHY_DCR_OFFSET (0x44)
426 #define DDRPHY_DTPR0_OFFSET (0x48)
427 #define DDRPHY_DTPR1_OFFSET (0x4C)
428 #define DDRPHY_DTPR2_OFFSET (0x50)
430 #define DDRPHY_MR0_OFFSET (0x54)
431 #define DDRPHY_MR1_OFFSET (0x58)
432 #define DDRPHY_MR2_OFFSET (0x5C)
433 #define DDRPHY_DTCR_OFFSET (0x68)
434 #define DDRPHY_PGCR2_OFFSET (0x8C)
436 #define DDRPHY_ZQ0CR1_OFFSET (0x184)
437 #define DDRPHY_ZQ1CR1_OFFSET (0x194)
438 #define DDRPHY_ZQ2CR1_OFFSET (0x1A4)
439 #define DDRPHY_ZQ3CR1_OFFSET (0x1B4)
441 #define DDRPHY_DATX8_4_OFFSET (0x2C0)
442 #define DDRPHY_DATX8_5_OFFSET (0x300)
443 #define DDRPHY_DATX8_6_OFFSET (0x340)
444 #define DDRPHY_DATX8_7_OFFSET (0x380)
445 #define DDRPHY_DATX8_8_OFFSET (0x3C0)
447 #define DDR3_MIDR_OFFSET (0x00)
448 #define DDR3_STATUS_OFFSET (0x04)
449 #define DDR3_SDCFG_OFFSET (0x08)
450 #define DDR3_SDRFC_OFFSET (0x10)
451 #define DDR3_SDTIM1_OFFSET (0x18)
452 #define DDR3_SDTIM2_OFFSET (0x1C)
453 #define DDR3_SDTIM3_OFFSET (0x20)
454 #define DDR3_SDTIM4_OFFSET (0x28)
455 #define DDR3_PMCTL_OFFSET (0x38)
456 #define DDR3_ZQCFG_OFFSET (0xC8)
457 #define DDR3_TMPALRT_OFFSET (0xCC)
458 #define DDR3_DDRPHYC_OFFSET (0xE4)
459 #define DDR3_ECC_CTRL_OFFSET (0x110)
462 #define IODDRM_MASK (0x00000180)
463 #define ZCKSEL_MASK (0x01800000)
464 #define CL_MASK (0x00000072)
465 #define WR_MASK (0x00000E00)
466 #define BL_MASK (0x00000003)
467 #define RRMODE_MASK (0x00040000)
468 #define UDIMM_MASK (0x20000000)
469 #define BYTEMASK_MASK (0x0000FC00)
470 #define MPRDQ_MASK (0x00000080)
471 #define PDQ_MASK (0x00000070)
472 #define NOSRA_MASK (0x08000000)
473 #define ECC_MASK (0x00000001)
475 typedef struct ddr3_phy_config {
476 uint32_t pllcr;
477 uint32_t pgcr1_mask;
478 uint32_t pgcr1_val;
479 uint32_t ptr0;
480 uint32_t ptr1;
481 uint32_t ptr2;
482 uint32_t ptr3;
483 uint32_t ptr4;
484 uint32_t dcr_mask;
485 uint32_t dcr_val;
486 uint32_t dtpr0;
487 uint32_t dtpr1;
488 uint32_t dtpr2;
489 uint32_t mr0;
490 uint32_t mr1;
491 uint32_t mr2;
492 uint32_t dtcr;
493 uint32_t pgcr2;
494 uint32_t zq0cr1;
495 uint32_t zq1cr1;
496 uint32_t zq2cr1;
497 uint32_t pir_v1;
498 uint32_t pir_v2;
499 uint32_t ecc_ctl;
500 } ddr3_phy_config;
502 typedef struct ddr3_emif_config {
503 uint32_t sdcfg;
504 uint32_t sdtim1;
505 uint32_t sdtim2;
506 uint32_t sdtim3;
507 uint32_t sdtim4;
508 uint32_t zqcfg;
509 uint32_t sdrfc;
510 } ddr3_emif_config;
512 #define read_reg(a) (*(volatile uint32_t *)(a))
513 #define write_reg(v,a) (*(volatile uint32_t *)(a) = (v))
516 /********************************************************************************************
517 * Function Prototypes *
518 *******************************************************************************************/
519 #if (PLATFORM_SEMLOCK_IN)
520 #define PLIBSPILOCK() Osal_platformSpiCsEnter();
521 #define PLIBSPIRELEASE() Osal_platformSpiCsExit ();
522 #else
523 #define PLIBSPILOCK()
524 #define PLIBSPIRELEASE()
525 #endif
527 /* Function prototypes that don't live anywhere else */
528 extern void configSerdes();
529 extern void Init_SGMII(uint32_t macport);
530 extern void PowerUpDomains (void);
531 extern void xmc_setup();
533 CSL_Status DDR3Init(void);
534 int32_t readSPD(uint8_t uchEepromI2cAddress,uint8_t buf[],uint8_t i2cportnumber);
535 int32_t init_ddr3param(uint8_t*);
537 #endif /* _PLATFORM_INTERNAL_H_ */