[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / board / src / idkAM571x / device / enet_phy.h
1 /**
2 * cpsw_miimdio.h
3 *
4 *
5 * Copyright (c) 2012 Texas Instruments Incorporated ALL RIGHTS RESERVED
6 *
7 */
8 #ifndef _ENETPHY_H
9 #define _ENETPHY_H
11 //#include "cpsw_nimu_eth.h"
13 #ifdef __cplusplus
14 extern "C" {
15 #endif
17 /***************************************************************************
18 **
19 ** M D I O R E G I S T E R A C C E S S M A C R O S
20 **
21 ***************************************************************************/
23 #define MDIO_USERACCESS_DATA (0xFFFF)
24 #define MDIO_USERPHYSEL_LINKSEL (1 << 7)
26 /****************************************************************************/
27 /* */
28 /* P H Y R E G I S T E R D E F I N I T I O N S */
29 /* */
30 /****************************************************************************/
32 /* PHY register offset definitions */
33 #define ENETPHY_BCR (0u)
34 #define ENETPHY_BSR (1u)
35 #define ENETPHY_ID1 (2u)
36 #define ENETPHY_ID2 (3u)
37 #define ENETPHY_AUTONEG_ADV (4u)
38 #define ENETPHY_LINK_PARTNER_ABLTY (5u)
39 #define ENETPHY_1000BT_CONTROL (9u)
40 #define ENETPHY_1000BT_STATUS (0x0A)
42 /* PHY status definitions */
43 #define ENETPHY_ID_SHIFT (16u)
44 #define ENETPHY_SOFTRESET (0x8000)
45 #define ENETPHY_AUTONEG_ENABLE (0x1000u)
46 #define ENETPHY_AUTONEG_RESTART (0x0200u)
47 #define ENETPHY_AUTONEG_COMPLETE (0x0020u)
48 #define ENETPHY_AUTONEG_INCOMPLETE (0x0000u)
49 #define ENETPHY_AUTONEG_STATUS (0x0020u)
50 #define ENETPHY_AUTONEG_ABLE (0x0008u)
51 #define ENETPHY_LPBK_ENABLE (0x4000u)
52 #define ENETPHY_LINK_STATUS (0x0004u)
54 /* PHY ID. The LSB nibble will vary between different phy revisions */
55 #define ENETPHY_ID_REV_MASK (0x0000000Fu)
57 /* Pause operations */
58 #define ENETPHY_PAUSE_NIL (0x0000u)
59 #define ENETPHY_PAUSE_SYM (0x0400u)
60 #define ENETPHY_PAUSE_ASYM (0x0800u)
61 #define ENETPHY_PAUSE_BOTH_SYM_ASYM (0x0C00u)
63 /* 1000 Base-T capabilities */
64 #define ENETPHY_NO_1000BT (0x0000u)
65 #define ENETPHY_1000BT_HD (0x0100u)
66 #define ENETPHY_1000BT_FD (0x0200u)
68 /* 100 Base TX Full Duplex capablity */
69 #define ENETPHY_100BTX_HD (0x0000u)
70 #define ENETPHY_100BTX_FD (0x0100u)
72 /* 100 Base TX capability */
73 #define ENETPHY_NO_100BTX (0x0000u)
74 #define ENETPHY_100BTX (0x0080u)
76 /* 10 BaseT duplex capabilities */
77 #define ENETPHY_10BT_HD (0x0000u)
78 #define ENETPHY_10BT_FD (0x0040u)
80 /* 10 BaseT ability*/
81 #define ENETPHY_NO_10BT (0x0000u)
82 #define ENETPHY_10BT (0x0020u)
84 #define ENETPHY_LINK_PARTNER_1000BT_FD (0x0800u)
85 #define ENETPHY_LINK_PARTNER_1000BT_HD (0x0400u)
87 /* Speed settings for BCR register */
88 #define ENETPHY_SPEED_MASK (0xDFBF)
89 #define ENETPHY_SPEED_10MBPS (0x0000u)
90 #define ENETPHY_SPEED_100MBPS (0x2000u)
91 #define ENETPHY_SPEED_1000MBPS (0x0040)
93 /* Duplex settings for BCR register */
94 #define ENETPHY_FULL_DUPLEX (0x0100)
96 #define ENETPHY_CONTROL_REG 0
97 #define MII_ENETPHY_RESET (1<<15)
98 #define MII_ENETPHY_LOOP (1<<14)
99 #define MII_ENETPHY_100 (1<<13)
100 #define MII_AUTO_NEGOTIATE_EN (1<<12)
101 #define MII_ENETPHY_PDOWN (1<<11)
102 #define MII_ENETPHY_ISOLATE (1<<10)
103 #define MII_RENEGOTIATE (1<<9)
104 #define MII_ENETPHY_FD (1<<8)
105 #define MII_ENETPHY_1000 (1<<6)
107 #define ENETPHY_STATUS_REG 1
108 #define MII_NWAY_COMPLETE (1<<5)
109 #define MII_NWAY_CAPABLE (1<<3)
110 #define MII_ENETPHY_LINKED (1<<2)
112 #define ENETPHY_IDENT_REG 2
113 #define NWAY_ADVERTIZE_REG 4
114 #define NWAY_REMADVERTISE_REG 5
115 #define MII_NWAY_FD100 (1<<8)
116 #define MII_NWAY_HD100 (1<<7)
117 #define MII_NWAY_FD10 (1<<6)
118 #define MII_NWAY_HD10 (1<<5)
119 #define MII_NWAY_SEL (1<<0)
121 #define NWAY_1000BT_ADVERTISE_REG 9
122 #define MII_NWAY_MY_FD1000 (1<<9)
123 #define MII_NWAY_MY_HD1000 (1<<8)
124 #define NWAY_1000BT_REMADVERTISE_REG 10
125 #define MII_NWAY_REM_FD1000 (1<<11)
126 #define MII_NWAY_REM_HD1000 (1<<10)
128 #define ENETPHY_CNTRL_REG 0x0019
130 #define ENETPHY_CONFIG_REG 22
131 #define SYSTEM_CLOCK_ENABLE_125MHZ (1<<4)
132 #define TRANSMIT_CLOCK_ENABLE_1000BASET (1<<5)
133 #define GMII_CLOCKED_BY_GTX_CLK (1<<1)
135 #define ENETPHY_LED_CONTROL_REG 28
137 /* Phy Mode Values */
138 #define NWAY_AUTOMDIX (1u << 16u)
139 #define NWAY_FD1000 (1u<<13u)
140 #define NWAY_HD1000 (1u<<12u)
141 #define NWAY_NOPHY (1u<<10u)
142 #define NWAY_LPBK (1u<<9u)
143 #define NWAY_FD100 (1u<<8u)
144 #define NWAY_HD100 (1u<<7u)
145 #define NWAY_FD10 (1u<<6u)
146 #define NWAY_HD10 (1u<<5u)
147 #define NWAY_AUTO (1u<<0u)
149 #define NWAY_AUTOMDIX_ENABLE (1u<<15)
151 /* Tic() return values */
152 #define _MIIMDIO_MDIXFLIP (1u<<28u)
153 #define _AUTOMDIX_DELAY_MIN 80u /* milli-seconds*/
154 #define _AUTOMDIX_DELAY_MAX 200u /* milli-seconds*/
156 /*-----------------------------------------------------------------------
157 * MDIO Events
158 *
159 * These events are returned as result param by ENETPHY_Tic() to allow the application
160 * (or EMAC) to track MDIO status.
161 *-----------------------------------------------------------------------*/
162 #define MDIO_EVENT_NOCHANGE 0u /* No change from previous status */
163 #define MDIO_EVENT_LINKDOWN 1u /* Link down event */
164 #define MDIO_EVENT_LINKUP 2u /* Link (or re-link) event */
165 #define MDIO_EVENT_PHYERROR 3u /* No PHY connected */
167 /*-----------------------------------------------------------------------
168 * MDIO Link Status Values
169 *
170 * These values indicate current PHY link status.
171 * Codes are constructed as follows
172 * Bit0: 0 for HD, 1 for FullDuplex
173 * Bit[2:1]: 10Mbps- 1, 100Mbps - 2, 1000Mbps - 3
174 *
175 *-----------------------------------------------------------------------*/
176 #define MDIO_LINKSTATUS_NOLINK 0u
177 #define MDIO_LINKSTATUS_HD10 2u
178 #define MDIO_LINKSTATUS_FD10 3u
179 #define MDIO_LINKSTATUS_HD100 4u
180 #define MDIO_LINKSTATUS_FD100 5u
181 #define MDIO_LINKSTATUS_FD1000 7u
183 typedef void *ENETPHY_Handle;
185 typedef struct _cpsw_phy_device
186 {
187 Uint32 miibase;
188 Uint32 inst;
189 Uint32 PhyState;
190 Uint32 MdixMask;
191 Uint32 PhyMask;
192 Uint32 MLinkMask;
193 Uint32 PhyMode;
194 Uint32 SPEED_1000; /* set to 1 for gig capable phys */
195 } ENETPHY_DEVICE;
197 /*Version Information */
198 void ENETPHY_GetVer(Uint32 miiBase, Uint32 *ModID, Uint32 *RevMaj, Uint32 *RevMin);
200 /*Called once at the begining of time */
201 int ENETPHY_GetPhyDevSize(void); /*Called first to get size of storage needed!*/
203 int ENETPHY_Init(ENETPHY_Handle hPhyDev, Uint32 miibase, Uint32 inst, Uint32 PhyMask,
204 Uint32 MLinkMask, Uint32 MdixMask, Uint32 PhyAddr, Uint32 ResetBit, Uint32 MdioBusFreq,
205 Uint32 MdioClockFreq,int verbose);
207 /*Called every 100 milli Seconds, returns TRUE if there has been a mode change */
208 int ENETPHY_Tic(ENETPHY_Handle hPhyDev, Uint32* mdioStatus);
210 /*Called to set Phy mode */
211 void ENETPHY_SetPhyMode(ENETPHY_Handle hPhyDev,Uint32 PhyMode);
213 /*Called to Get Phy mode */
214 Uint32 ENETPHY_GetPhyMode(ENETPHY_Handle hPhyDev);
216 /*Calls to retreive info after a mode change! */
217 int ENETPHY_GetDuplex(ENETPHY_Handle hPhyDev);
218 int ENETPHY_GetSpeed(ENETPHY_Handle hPhyDev);
219 int ENETPHY_GetPhyNum(ENETPHY_Handle hPhyDev);
220 int ENETPHY_GetLinked(ENETPHY_Handle hPhyDev);
221 void ENETPHY_LinkChange(ENETPHY_Handle hPhyDev);
222 int ENETPHY_GetLoopback(ENETPHY_Handle hPhyDev);
224 /* Shut Down */
225 void ENETPHY_Close(ENETPHY_Handle hPhyDev, int Full);
227 /* Expert Use Functions (exported) */
228 Uint32 _ENETPHY_UserAccessRead (ENETPHY_Handle hPhyDev, Uint32 regadr, Uint32 phyadr, Uint32 *data);
229 void _ENETPHY_UserAccessWrite(ENETPHY_Handle hPhyDev, Uint32 regadr, Uint32 phyadr, Uint32 data);
231 #ifdef __cplusplus
232 }
233 #endif
235 #endif /*_CPSW_MIIMDIO_H*/