[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / board / src / idkAM571x / idkAM571x_clock.c
1 /******************************************************************************
2 * Copyright (c) 2010-2015 Texas Instruments Incorporated - http://www.ti.com
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 *****************************************************************************/
34 #include "board_internal.h"
36 /* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
37 Board_STATUS Board_moduleClockInit()
38 {
39 CSL_cam_cm_coreRegs *camCmReg =
40 (CSL_cam_cm_coreRegs *) CSL_MPU_CAM_CM_CORE_REGS;
41 CSL_l4per_cm_core_componentRegs *l4PerCmReg =
42 (CSL_l4per_cm_core_componentRegs *) CSL_MPU_L4PER_CM_CORE_REGS;
43 CSL_l3init_cm_coreRegs *l3InitCmReg =
44 (CSL_l3init_cm_coreRegs *) CSL_MPU_L3INIT_CM_CORE_REGS;
45 CSL_core_cm_coreRegs *coreCmReg =
46 (CSL_core_cm_coreRegs *) CSL_MPU_CORE_CM_CORE_REGS;
47 CSL_coreaon_cm_coreRegs *coreAonCmReg =
48 (CSL_coreaon_cm_coreRegs *) CSL_MPU_COREAON_CM_CORE_REGS;
49 CSL_dss_cm_coreRegs *dssCmReg =
50 (CSL_dss_cm_coreRegs *) CSL_MPU_DSS_CM_CORE_REGS;
51 CSL_ipu_cm_core_aonRegs *ipuCmReg =
52 (CSL_ipu_cm_core_aonRegs *) CSL_MPU_IPU_CM_CORE_AON_REGS;
53 CSL_rtc_cm_core_aonRegs *rtcCmReg =
54 (CSL_rtc_cm_core_aonRegs *) CSL_MPU_RTC_CM_CORE_AON_REGS;
55 CSL_vpe_cm_core_aonRegs *vpeCmReg =
56 (CSL_vpe_cm_core_aonRegs *) CSL_MPU_VPE_CM_CORE_AON_REGS;
57 CSL_wkupaon_cmRegs *wkupAonCmReg =
58 (CSL_wkupaon_cmRegs *) CSL_MPU_WKUPAON_CM_REGS;
59 CSL_mpu_cm_core_aonRegs *mpuCmReg =
60 (CSL_mpu_cm_core_aonRegs *) CSL_MPU_MPU_CM_CORE_AON_REGS;
61 CSL_dsp1_cm_core_aonRegs *dsp1CmReg =
62 (CSL_dsp1_cm_core_aonRegs *) CSL_MPU_DSP1_CM_CORE_AON_REGS;
63 CSL_dsp2_cm_core_aonRegs *dsp2CmReg =
64 (CSL_dsp2_cm_core_aonRegs *) CSL_MPU_DSP2_CM_CORE_AON_REGS;
65 CSL_iva_cm_coreRegs *ivaCmReg =
66 (CSL_iva_cm_coreRegs *) CSL_MPU_IVA_CM_CORE_REGS;
68 /* PRCM clock domain state setting functions */
69 CSL_FINST(camCmReg->CM_CAM_CLKSTCTRL_REG,
70 CAM_CM_CORE_CM_CAM_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
71 /*
72 while(CSL_CAM_CM_CORE_CM_CAM_CLKSTCTRL_REG_CLKACTIVITY_VIP1_GCLK_ACT !=
73 CSL_FEXT(camCmReg->CM_CAM_CLKSTCTRL_REG,
74 CAM_CM_CORE_CM_CAM_CLKSTCTRL_REG_CLKACTIVITY_VIP1_GCLK));
75 */
77 CSL_FINST(l4PerCmReg->CM_L4PER_CLKSTCTRL_REG,
78 L4PER_CM_CORE_COMPONENT_CM_L4PER_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
80 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_CLKSTCTRL_REG_CLKACTIVITY_L4PER_L3_GICLK_ACT !=
81 CSL_FEXT(l4PerCmReg->CM_L4PER_CLKSTCTRL_REG,
82 L4PER_CM_CORE_COMPONENT_CM_L4PER_CLKSTCTRL_REG_CLKACTIVITY_L4PER_L3_GICLK));
84 CSL_FINST(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
85 L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
86 /*
87 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_CLK_ACT !=
88 CSL_FEXT(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
89 L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_CLK));
90 */
92 CSL_FINST(l4PerCmReg->CM_L4PER3_CLKSTCTRL_REG,
93 L4PER_CM_CORE_COMPONENT_CM_L4PER3_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
95 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER3_CLKSTCTRL_REG_CLKACTIVITY_L4PER3_L3_GICLK_ACT !=
96 CSL_FEXT(l4PerCmReg->CM_L4PER3_CLKSTCTRL_REG,
97 L4PER_CM_CORE_COMPONENT_CM_L4PER3_CLKSTCTRL_REG_CLKACTIVITY_L4PER3_L3_GICLK));
99 CSL_FINST(l3InitCmReg->CM_L3INIT_CLKSTCTRL_REG,
100 L3INIT_CM_CORE_CM_L3INIT_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
102 while(CSL_L3INIT_CM_CORE_CM_L3INIT_CLKSTCTRL_REG_CLKACTIVITY_L3INIT_L3_GICLK_ACT !=
103 CSL_FEXT(l3InitCmReg->CM_L3INIT_CLKSTCTRL_REG,
104 L3INIT_CM_CORE_CM_L3INIT_CLKSTCTRL_REG_CLKACTIVITY_L3INIT_L3_GICLK));
106 CSL_FINST(l3InitCmReg->CM_GMAC_CLKSTCTRL_REG,
107 L3INIT_CM_CORE_CM_GMAC_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
108 /*
109 while(CSL_L3INIT_CM_CORE_CM_GMAC_CLKSTCTRL_REG_CLKACTIVITY_GMII_250MHZ_CLK_ACT !=
110 CSL_FEXT(l3InitCmReg->CM_GMAC_CLKSTCTRL_REG,
111 L3INIT_CM_CORE_CM_GMAC_CLKSTCTRL_REG_CLKACTIVITY_GMII_250MHZ_CLK));
112 */
114 CSL_FINST(coreCmReg->CM_EMIF_CLKSTCTRL_REG,
115 CORE_CM_CORE_CM_EMIF_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
117 while(CSL_CORE_CM_CORE_CM_EMIF_CLKSTCTRL_REG_CLKACTIVITY_EMIF_L3_GICLK_ACT !=
118 CSL_FEXT(coreCmReg->CM_EMIF_CLKSTCTRL_REG,
119 CORE_CM_CORE_CM_EMIF_CLKSTCTRL_REG_CLKACTIVITY_EMIF_L3_GICLK));
121 CSL_FINST(coreCmReg->CM_L4CFG_CLKSTCTRL_REG,
122 CORE_CM_CORE_CM_L4CFG_CLKSTCTRL_REG_CLKTRCTRL, RESERVED_2);
124 while(CSL_CORE_CM_CORE_CM_L4CFG_CLKSTCTRL_REG_CLKACTIVITY_L4CFG_L4_GICLK_ACT !=
125 CSL_FEXT(coreCmReg->CM_L4CFG_CLKSTCTRL_REG,
126 CORE_CM_CORE_CM_L4CFG_CLKSTCTRL_REG_CLKACTIVITY_L4CFG_L4_GICLK));
128 CSL_FINST(coreCmReg->CM_DMA_CLKSTCTRL_REG,
129 CORE_CM_CORE_CM_DMA_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
131 while(CSL_CORE_CM_CORE_CM_DMA_CLKSTCTRL_REG_CLKACTIVITY_DMA_L3_GICLK_ACT !=
132 CSL_FEXT(coreCmReg->CM_DMA_CLKSTCTRL_REG,
133 CORE_CM_CORE_CM_DMA_CLKSTCTRL_REG_CLKACTIVITY_DMA_L3_GICLK));
135 CSL_FINST(coreCmReg->CM_L3MAIN1_CLKSTCTRL_REG,
136 CORE_CM_CORE_CM_L3MAIN1_CLKSTCTRL_REG_CLKTRCTRL, RESERVED_2);
138 while(CSL_CORE_CM_CORE_CM_L3MAIN1_CLKSTCTRL_REG_CLKACTIVITY_L3MAIN1_L3_GICLK_ACT !=
139 CSL_FEXT(coreCmReg->CM_L3MAIN1_CLKSTCTRL_REG,
140 CORE_CM_CORE_CM_L3MAIN1_CLKSTCTRL_REG_CLKACTIVITY_L3MAIN1_L3_GICLK));
142 CSL_FINST(coreCmReg->CM_IPU2_CLKSTCTRL_REG,
143 CORE_CM_CORE_CM_IPU2_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
144 /*
145 while(CSL_CORE_CM_CORE_CM_IPU2_CLKSTCTRL_REG_CLKACTIVITY_IPU2_GFCLK_ACT !=
146 CSL_FEXT(coreCmReg->CM_IPU2_CLKSTCTRL_REG,
147 CORE_CM_CORE_CM_IPU2_CLKSTCTRL_REG_CLKACTIVITY_IPU2_GFCLK));
148 */
150 CSL_FINST(coreAonCmReg->CM_COREAON_CLKSTCTRL_REG,
151 COREAON_CM_CORE_CM_COREAON_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
152 /*
153 while(CSL_COREAON_CM_CORE_CM_COREAON_CLKSTCTRL_REG_CLKACTIVITY_COREAON_L4_GICLK_ACT !=
154 CSL_FEXT(coreAonCmReg->CM_COREAON_CLKSTCTRL_REG,
155 COREAON_CM_CORE_CM_COREAON_CLKSTCTRL_REG_CLKACTIVITY_COREAON_L4_GICLK));
156 */
158 CSL_FINST(dssCmReg->CM_DSS_CLKSTCTRL_REG,
159 DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
160 /*
161 while(CSL_DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK_ACT !=
162 CSL_FEXT(dssCmReg->CM_DSS_CLKSTCTRL_REG,
163 DSS_CM_CORE_CM_DSS_CLKSTCTRL_REG_CLKACTIVITY_DSS_L3_GICLK));
164 */
166 CSL_FINST(ipuCmReg->CM_IPU1_CLKSTCTRL_REG,
167 IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
168 /*
169 while(CSL_IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKACTIVITY_IPU1_GFCLK_ACT !=
170 CSL_FEXT(ipuCmReg->CM_IPU1_CLKSTCTRL_REG,
171 IPU_CM_CORE_AON_CM_IPU1_CLKSTCTRL_REG_CLKACTIVITY_IPU1_GFCLK));
172 */
174 CSL_FINST(ipuCmReg->CM_IPU_CLKSTCTRL_REG,
175 IPU_CM_CORE_AON_CM_IPU_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
176 /*
177 while(CSL_IPU_CM_CORE_AON_CM_IPU_CLKSTCTRL_REG_CLKACTIVITY_IPU_L3_GICLK_ACT !=
178 CSL_FEXT(ipuCmReg->CM_IPU_CLKSTCTRL_REG,
179 IPU_CM_CORE_AON_CM_IPU_CLKSTCTRL_REG_CLKACTIVITY_IPU_L3_GICLK));
180 */
182 CSL_FINST(rtcCmReg->CM_RTC_CLKSTCTRL_REG,
183 RTC_CM_CORE_AON_CM_RTC_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
184 /*
185 while(CSL_RTC_CM_CORE_AON_CM_RTC_CLKSTCTRL_REG_CLKACTIVITY_RTC_L4_GICLK_ACT !=
186 CSL_FEXT(rtcCmReg->CM_RTC_CLKSTCTRL_REG,
187 RTC_CM_CORE_AON_CM_RTC_CLKSTCTRL_REG_CLKACTIVITY_RTC_L4_GICLK));
188 */
190 CSL_FINST(vpeCmReg->CM_VPE_CLKSTCTRL_REG,
191 VPE_CM_CORE_AON_CM_VPE_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
192 /*
193 while(CSL_VPE_CM_CORE_AON_CM_VPE_CLKSTCTRL_REG_CLKACTIVITY_VPE_GCLK_ACT !=
194 CSL_FEXT(vpeCmReg->CM_VPE_CLKSTCTRL_REG,
195 VPE_CM_CORE_AON_CM_VPE_CLKSTCTRL_REG_CLKACTIVITY_VPE_GCLK));
196 */
198 CSL_FINST(wkupAonCmReg->CM_WKUPAON_CLKSTCTRL_REG,
199 WKUPAON_CM_CM_WKUPAON_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
200 /*
201 while(CSL_WKUPAON_CM_CM_WKUPAON_CLKSTCTRL_REG_CLKACTIVITY_SYS_CLK_ACT !=
202 CSL_FEXT(wkupAonCmReg->CM_WKUPAON_CLKSTCTRL_REG,
203 WKUPAON_CM_CM_WKUPAON_CLKSTCTRL_REG_CLKACTIVITY_SYS_CLK));
204 */
206 CSL_FINST(mpuCmReg->CM_MPU_CLKSTCTRL_REG,
207 MPU_CM_CORE_AON_CM_MPU_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
208 /*
209 while(CSL_MPU_CM_CORE_AON_CM_MPU_CLKSTCTRL_REG_CLKACTIVITY_MPU_GCLK_ACT !=
210 CSL_FEXT(mpuCmReg->CM_MPU_CLKSTCTRL_REG,
211 MPU_CM_CORE_AON_CM_MPU_CLKSTCTRL_REG_CLKACTIVITY_MPU_GCLK));
212 */
214 CSL_FINST(dsp1CmReg->CM_DSP1_CLKSTCTRL_REG,
215 DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
216 /*
217 while(CSL_DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKACTIVITY_DSP1_GFCLK_ACT !=
218 CSL_FEXT(dsp1CmReg->CM_DSP1_CLKSTCTRL_REG,
219 DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKACTIVITY_DSP1_GFCLK));
220 */
222 CSL_FINST(dsp2CmReg->CM_DSP2_CLKSTCTRL_REG,
223 DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
224 /*
225 while(CSL_DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKACTIVITY_DSP2_GFCLK_ACT !=
226 CSL_FEXT(dsp2CmReg->CM_DSP2_CLKSTCTRL_REG,
227 DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKACTIVITY_DSP2_GFCLK));
228 */
230 CSL_FINST(ivaCmReg->CM_IVA_CLKSTCTRL_REG,
231 IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
232 /*
233 while(CSL_IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKACTIVITY_IVA_GCLK_ACT !=
234 CSL_FEXT(ivaCmReg->CM_IVA_CLKSTCTRL_REG,
235 IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKACTIVITY_IVA_GCLK));
236 */
238 /* PRCM Generic module mode setting functions */
240 CSL_FINST(camCmReg->CM_CAM_VIP1_CLKCTRL_REG,
241 CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_MODULEMODE, AUTO);
243 while(CSL_CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_IDLEST_FUNC !=
244 CSL_FEXT(camCmReg->CM_CAM_VIP1_CLKCTRL_REG,
245 CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_IDLEST));
247 CSL_FINST(camCmReg->CM_CAM_VIP2_CLKCTRL_REG,
248 CAM_CM_CORE_CM_CAM_VIP2_CLKCTRL_REG_MODULEMODE, AUTO);
250 while(CSL_CAM_CM_CORE_CM_CAM_VIP2_CLKCTRL_REG_IDLEST_FUNC !=
251 CSL_FEXT(camCmReg->CM_CAM_VIP2_CLKCTRL_REG,
252 CAM_CM_CORE_CM_CAM_VIP2_CLKCTRL_REG_IDLEST));
254 CSL_FINST(camCmReg->CM_CAM_VIP3_CLKCTRL_REG,
255 CAM_CM_CORE_CM_CAM_VIP3_CLKCTRL_REG_MODULEMODE, AUTO);
257 while(CSL_CAM_CM_CORE_CM_CAM_VIP3_CLKCTRL_REG_IDLEST_FUNC !=
258 CSL_FEXT(camCmReg->CM_CAM_VIP3_CLKCTRL_REG,
259 CAM_CM_CORE_CM_CAM_VIP3_CLKCTRL_REG_IDLEST));
261 CSL_FINST(coreCmReg->CM_DMA_DMA_SYSTEM_CLKCTRL_REG,
262 CORE_CM_CORE_CM_DMA_DMA_SYSTEM_CLKCTRL_REG_MODULEMODE, AUTO);
264 while(CSL_CORE_CM_CORE_CM_DMA_DMA_SYSTEM_CLKCTRL_REG_IDLEST_FUNC !=
265 CSL_FEXT(coreCmReg->CM_DMA_DMA_SYSTEM_CLKCTRL_REG,
266 CORE_CM_CORE_CM_DMA_DMA_SYSTEM_CLKCTRL_REG_IDLEST));
268 CSL_FINST(coreCmReg->CM_EMIF_DMM_CLKCTRL_REG,
269 CORE_CM_CORE_CM_EMIF_DMM_CLKCTRL_REG_MODULEMODE, AUTO);
271 while(CSL_CORE_CM_CORE_CM_EMIF_DMM_CLKCTRL_REG_IDLEST_FUNC !=
272 CSL_FEXT(coreCmReg->CM_EMIF_DMM_CLKCTRL_REG,
273 CORE_CM_CORE_CM_EMIF_DMM_CLKCTRL_REG_IDLEST));
275 CSL_FINST(coreCmReg->CM_EMIF_EMIF1_CLKCTRL_REG,
276 CORE_CM_CORE_CM_EMIF_EMIF1_CLKCTRL_REG_MODULEMODE, AUTO);
278 while(CSL_CORE_CM_CORE_CM_EMIF_EMIF1_CLKCTRL_REG_IDLEST_FUNC !=
279 CSL_FEXT(coreCmReg->CM_EMIF_EMIF1_CLKCTRL_REG,
280 CORE_CM_CORE_CM_EMIF_EMIF1_CLKCTRL_REG_IDLEST));
282 CSL_FINST(coreCmReg->CM_EMIF_EMIF2_CLKCTRL_REG,
283 CORE_CM_CORE_CM_EMIF_EMIF2_CLKCTRL_REG_MODULEMODE, AUTO);
285 while(CSL_CORE_CM_CORE_CM_EMIF_EMIF2_CLKCTRL_REG_IDLEST_FUNC !=
286 CSL_FEXT(coreCmReg->CM_EMIF_EMIF2_CLKCTRL_REG,
287 CORE_CM_CORE_CM_EMIF_EMIF2_CLKCTRL_REG_IDLEST));
289 CSL_FINST(coreCmReg->CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG,
290 CORE_CM_CORE_CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG_MODULEMODE, AUTO);
292 while(CSL_CORE_CM_CORE_CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG_IDLEST_FUNC !=
293 CSL_FEXT(coreCmReg->CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG,
294 CORE_CM_CORE_CM_EMIF_EMIF_OCP_FW_CLKCTRL_REG_IDLEST));
296 CSL_FINST(coreCmReg->CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG,
297 CORE_CM_CORE_CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG_MODULEMODE, AUTO);
299 while(CSL_CORE_CM_CORE_CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG_IDLEST_FUNC !=
300 CSL_FEXT(coreCmReg->CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG,
301 CORE_CM_CORE_CM_L3INSTR_L3_MAIN_2_CLKCTRL_REG_IDLEST));
303 CSL_FINST(coreCmReg->CM_L3MAIN1_GPMC_CLKCTRL_REG,
304 CORE_CM_CORE_CM_L3MAIN1_GPMC_CLKCTRL_REG_MODULEMODE, AUTO);
306 while(CSL_CORE_CM_CORE_CM_L3MAIN1_GPMC_CLKCTRL_REG_IDLEST_FUNC !=
307 CSL_FEXT(coreCmReg->CM_L3MAIN1_GPMC_CLKCTRL_REG,
308 CORE_CM_CORE_CM_L3MAIN1_GPMC_CLKCTRL_REG_IDLEST));
310 CSL_FINST(coreCmReg->CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG,
311 CORE_CM_CORE_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG_MODULEMODE, AUTO);
313 while(CSL_CORE_CM_CORE_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG_IDLEST_FUNC !=
314 CSL_FEXT(coreCmReg->CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG,
315 CORE_CM_CORE_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG_IDLEST));
317 CSL_FINST(coreCmReg->CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG,
318 CORE_CM_CORE_CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG_MODULEMODE, AUTO);
320 while(CSL_CORE_CM_CORE_CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG_IDLEST_FUNC !=
321 CSL_FEXT(coreCmReg->CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG,
322 CORE_CM_CORE_CM_L3MAIN1_MMU_EDMA_CLKCTRL_REG_IDLEST));
324 CSL_FINST(coreCmReg->CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG,
325 CORE_CM_CORE_CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG_MODULEMODE, AUTO);
327 while(CSL_CORE_CM_CORE_CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG_IDLEST_FUNC !=
328 CSL_FEXT(coreCmReg->CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG,
329 CORE_CM_CORE_CM_L3MAIN1_MMU_PCIESS_CLKCTRL_REG_IDLEST));
331 CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG,
332 CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG_MODULEMODE, AUTO);
334 while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG_IDLEST_FUNC !=
335 CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG,
336 CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_REG_IDLEST));
338 CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG,
339 CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG_MODULEMODE, AUTO);
341 while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG_IDLEST_FUNC !=
342 CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG,
343 CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_REG_IDLEST));
345 CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG,
346 CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG_MODULEMODE, AUTO);
348 while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG_IDLEST_FUNC !=
349 CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG,
350 CORE_CM_CORE_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_REG_IDLEST));
352 CSL_FINST(coreCmReg->CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG,
353 CORE_CM_CORE_CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG_MODULEMODE, AUTO);
355 while(CSL_CORE_CM_CORE_CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG_IDLEST_FUNC !=
356 CSL_FEXT(coreCmReg->CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG,
357 CORE_CM_CORE_CM_L3MAIN1_OCMC_ROM_CLKCTRL_REG_IDLEST));
359 CSL_FINST(coreCmReg->CM_L3MAIN1_TPCC_CLKCTRL_REG,
360 CORE_CM_CORE_CM_L3MAIN1_TPCC_CLKCTRL_REG_MODULEMODE, AUTO);
362 while(CSL_CORE_CM_CORE_CM_L3MAIN1_TPCC_CLKCTRL_REG_IDLEST_FUNC !=
363 CSL_FEXT(coreCmReg->CM_L3MAIN1_TPCC_CLKCTRL_REG,
364 CORE_CM_CORE_CM_L3MAIN1_TPCC_CLKCTRL_REG_IDLEST));
366 CSL_FINST(coreCmReg->CM_L3MAIN1_TPTC1_CLKCTRL_REG,
367 CORE_CM_CORE_CM_L3MAIN1_TPTC1_CLKCTRL_REG_MODULEMODE, AUTO);
369 while(CSL_CORE_CM_CORE_CM_L3MAIN1_TPTC1_CLKCTRL_REG_IDLEST_FUNC !=
370 CSL_FEXT(coreCmReg->CM_L3MAIN1_TPTC1_CLKCTRL_REG,
371 CORE_CM_CORE_CM_L3MAIN1_TPTC1_CLKCTRL_REG_IDLEST));
373 CSL_FINST(coreCmReg->CM_L3MAIN1_TPTC2_CLKCTRL_REG,
374 CORE_CM_CORE_CM_L3MAIN1_TPTC2_CLKCTRL_REG_MODULEMODE, AUTO);
376 while(CSL_CORE_CM_CORE_CM_L3MAIN1_TPTC2_CLKCTRL_REG_IDLEST_FUNC !=
377 CSL_FEXT(coreCmReg->CM_L3MAIN1_TPTC2_CLKCTRL_REG,
378 CORE_CM_CORE_CM_L3MAIN1_TPTC2_CLKCTRL_REG_IDLEST));
380 // TODO: Check if enabled or AUTO
381 CSL_FINS(coreCmReg->CM_L3MAIN1_VCP1_CLKCTRL_REG,
382 CORE_CM_CORE_CM_L3MAIN1_VCP1_CLKCTRL_REG_MODULEMODE, 2U);
384 while(CSL_CORE_CM_CORE_CM_L3MAIN1_VCP1_CLKCTRL_REG_IDLEST_FUNC !=
385 CSL_FEXT(coreCmReg->CM_L3MAIN1_VCP1_CLKCTRL_REG,
386 CORE_CM_CORE_CM_L3MAIN1_VCP1_CLKCTRL_REG_IDLEST));
388 CSL_FINS(coreCmReg->CM_L3MAIN1_VCP2_CLKCTRL_REG,
389 CORE_CM_CORE_CM_L3MAIN1_VCP2_CLKCTRL_REG_MODULEMODE, 2U);
391 while(CSL_CORE_CM_CORE_CM_L3MAIN1_VCP2_CLKCTRL_REG_IDLEST_FUNC !=
392 CSL_FEXT(coreCmReg->CM_L3MAIN1_VCP2_CLKCTRL_REG,
393 CORE_CM_CORE_CM_L3MAIN1_VCP2_CLKCTRL_REG_IDLEST));
395 CSL_FINST(coreCmReg->CM_L4CFG_L4_CFG_CLKCTRL_REG,
396 CORE_CM_CORE_CM_L4CFG_L4_CFG_CLKCTRL_REG_MODULEMODE, AUTO);
398 while(CSL_CORE_CM_CORE_CM_L4CFG_L4_CFG_CLKCTRL_REG_IDLEST_FUNC !=
399 CSL_FEXT(coreCmReg->CM_L4CFG_L4_CFG_CLKCTRL_REG,
400 CORE_CM_CORE_CM_L4CFG_L4_CFG_CLKCTRL_REG_IDLEST));
402 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX1_CLKCTRL_REG,
403 CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_MODULEMODE, AUTO);
405 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST_FUNC !=
406 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX1_CLKCTRL_REG,
407 CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST));
409 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX10_CLKCTRL_REG,
410 CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_MODULEMODE, AUTO);
412 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST_FUNC !=
413 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX10_CLKCTRL_REG,
414 CORE_CM_CORE_CM_L4CFG_MAILBOX1_CLKCTRL_REG_IDLEST));
416 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX11_CLKCTRL_REG,
417 CORE_CM_CORE_CM_L4CFG_MAILBOX11_CLKCTRL_REG_MODULEMODE, AUTO);
419 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX11_CLKCTRL_REG_IDLEST_FUNC !=
420 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX11_CLKCTRL_REG,
421 CORE_CM_CORE_CM_L4CFG_MAILBOX11_CLKCTRL_REG_IDLEST));
423 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX12_CLKCTRL_REG,
424 CORE_CM_CORE_CM_L4CFG_MAILBOX12_CLKCTRL_REG_MODULEMODE, AUTO);
426 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX12_CLKCTRL_REG_IDLEST_FUNC !=
427 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX12_CLKCTRL_REG,
428 CORE_CM_CORE_CM_L4CFG_MAILBOX12_CLKCTRL_REG_IDLEST));
430 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX13_CLKCTRL_REG,
431 CORE_CM_CORE_CM_L4CFG_MAILBOX13_CLKCTRL_REG_MODULEMODE, AUTO);
433 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX13_CLKCTRL_REG_IDLEST_FUNC !=
434 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX13_CLKCTRL_REG,
435 CORE_CM_CORE_CM_L4CFG_MAILBOX13_CLKCTRL_REG_IDLEST));
437 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX2_CLKCTRL_REG,
438 CORE_CM_CORE_CM_L4CFG_MAILBOX2_CLKCTRL_REG_MODULEMODE, AUTO);
440 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX2_CLKCTRL_REG_IDLEST_FUNC !=
441 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX2_CLKCTRL_REG,
442 CORE_CM_CORE_CM_L4CFG_MAILBOX2_CLKCTRL_REG_IDLEST));
444 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX3_CLKCTRL_REG,
445 CORE_CM_CORE_CM_L4CFG_MAILBOX3_CLKCTRL_REG_MODULEMODE, AUTO);
447 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX3_CLKCTRL_REG_IDLEST_FUNC !=
448 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX3_CLKCTRL_REG,
449 CORE_CM_CORE_CM_L4CFG_MAILBOX3_CLKCTRL_REG_IDLEST));
451 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX4_CLKCTRL_REG,
452 CORE_CM_CORE_CM_L4CFG_MAILBOX4_CLKCTRL_REG_MODULEMODE, AUTO);
454 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX4_CLKCTRL_REG_IDLEST_FUNC !=
455 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX4_CLKCTRL_REG,
456 CORE_CM_CORE_CM_L4CFG_MAILBOX4_CLKCTRL_REG_IDLEST));
458 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX5_CLKCTRL_REG,
459 CORE_CM_CORE_CM_L4CFG_MAILBOX5_CLKCTRL_REG_MODULEMODE, AUTO);
461 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX5_CLKCTRL_REG_IDLEST_FUNC !=
462 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX5_CLKCTRL_REG,
463 CORE_CM_CORE_CM_L4CFG_MAILBOX5_CLKCTRL_REG_IDLEST));
465 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX6_CLKCTRL_REG,
466 CORE_CM_CORE_CM_L4CFG_MAILBOX6_CLKCTRL_REG_MODULEMODE, AUTO);
468 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX6_CLKCTRL_REG_IDLEST_FUNC !=
469 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX6_CLKCTRL_REG,
470 CORE_CM_CORE_CM_L4CFG_MAILBOX6_CLKCTRL_REG_IDLEST));
472 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX7_CLKCTRL_REG,
473 CORE_CM_CORE_CM_L4CFG_MAILBOX7_CLKCTRL_REG_MODULEMODE, AUTO);
475 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX7_CLKCTRL_REG_IDLEST_FUNC !=
476 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX7_CLKCTRL_REG,
477 CORE_CM_CORE_CM_L4CFG_MAILBOX7_CLKCTRL_REG_IDLEST));
479 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX8_CLKCTRL_REG,
480 CORE_CM_CORE_CM_L4CFG_MAILBOX8_CLKCTRL_REG_MODULEMODE, AUTO);
482 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX8_CLKCTRL_REG_IDLEST_FUNC !=
483 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX8_CLKCTRL_REG,
484 CORE_CM_CORE_CM_L4CFG_MAILBOX8_CLKCTRL_REG_IDLEST));
486 CSL_FINST(coreCmReg->CM_L4CFG_MAILBOX9_CLKCTRL_REG,
487 CORE_CM_CORE_CM_L4CFG_MAILBOX9_CLKCTRL_REG_MODULEMODE, AUTO);
489 while(CSL_CORE_CM_CORE_CM_L4CFG_MAILBOX9_CLKCTRL_REG_IDLEST_FUNC !=
490 CSL_FEXT(coreCmReg->CM_L4CFG_MAILBOX9_CLKCTRL_REG,
491 CORE_CM_CORE_CM_L4CFG_MAILBOX9_CLKCTRL_REG_IDLEST));
493 CSL_FINST(coreCmReg->CM_L4CFG_SPINLOCK_CLKCTRL_REG,
494 CORE_CM_CORE_CM_L4CFG_SPINLOCK_CLKCTRL_REG_MODULEMODE, AUTO);
496 while(CSL_CORE_CM_CORE_CM_L4CFG_SPINLOCK_CLKCTRL_REG_IDLEST_FUNC !=
497 CSL_FEXT(coreCmReg->CM_L4CFG_SPINLOCK_CLKCTRL_REG,
498 CORE_CM_CORE_CM_L4CFG_SPINLOCK_CLKCTRL_REG_IDLEST));
500 CSL_FINST(ipuCmReg->CM_IPU_TIMER5_CLKCTRL_REG,
501 IPU_CM_CORE_AON_CM_IPU_TIMER5_CLKCTRL_REG_MODULEMODE, ENABLE);
503 while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER5_CLKCTRL_REG_IDLEST_FUNC !=
504 CSL_FEXT(ipuCmReg->CM_IPU_TIMER5_CLKCTRL_REG,
505 IPU_CM_CORE_AON_CM_IPU_TIMER5_CLKCTRL_REG_IDLEST));
507 CSL_FINST(ipuCmReg->CM_IPU_TIMER6_CLKCTRL_REG,
508 IPU_CM_CORE_AON_CM_IPU_TIMER6_CLKCTRL_REG_MODULEMODE, ENABLE);
510 while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER6_CLKCTRL_REG_IDLEST_FUNC !=
511 CSL_FEXT(ipuCmReg->CM_IPU_TIMER6_CLKCTRL_REG,
512 IPU_CM_CORE_AON_CM_IPU_TIMER6_CLKCTRL_REG_IDLEST));
514 CSL_FINST(ipuCmReg->CM_IPU_TIMER7_CLKCTRL_REG,
515 IPU_CM_CORE_AON_CM_IPU_TIMER7_CLKCTRL_REG_MODULEMODE, ENABLE);
517 while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER7_CLKCTRL_REG_IDLEST_FUNC !=
518 CSL_FEXT(ipuCmReg->CM_IPU_TIMER7_CLKCTRL_REG,
519 IPU_CM_CORE_AON_CM_IPU_TIMER7_CLKCTRL_REG_IDLEST));
521 CSL_FINST(ipuCmReg->CM_IPU_TIMER8_CLKCTRL_REG,
522 IPU_CM_CORE_AON_CM_IPU_TIMER8_CLKCTRL_REG_MODULEMODE, ENABLE);
524 while(CSL_IPU_CM_CORE_AON_CM_IPU_TIMER8_CLKCTRL_REG_IDLEST_FUNC !=
525 CSL_FEXT(ipuCmReg->CM_IPU_TIMER8_CLKCTRL_REG,
526 IPU_CM_CORE_AON_CM_IPU_TIMER8_CLKCTRL_REG_IDLEST));
528 CSL_FINST(l3InitCmReg->CM_L3INIT_MMC1_CLKCTRL_REG,
529 L3INIT_CM_CORE_CM_L3INIT_MMC1_CLKCTRL_REG_MODULEMODE, ENABLED);
531 while(CSL_L3INIT_CM_CORE_CM_L3INIT_MMC1_CLKCTRL_REG_IDLEST_FUNC !=
532 CSL_FEXT(l3InitCmReg->CM_L3INIT_MMC1_CLKCTRL_REG,
533 L3INIT_CM_CORE_CM_L3INIT_MMC1_CLKCTRL_REG_IDLEST));
535 CSL_FINST(l3InitCmReg->CM_L3INIT_MMC2_CLKCTRL_REG,
536 L3INIT_CM_CORE_CM_L3INIT_MMC2_CLKCTRL_REG_MODULEMODE, ENABLED);
538 while(CSL_L3INIT_CM_CORE_CM_L3INIT_MMC2_CLKCTRL_REG_IDLEST_FUNC !=
539 CSL_FEXT(l3InitCmReg->CM_L3INIT_MMC2_CLKCTRL_REG,
540 L3INIT_CM_CORE_CM_L3INIT_MMC2_CLKCTRL_REG_IDLEST));
542 CSL_FINST(l3InitCmReg->CM_GMAC_GMAC_CLKCTRL_REG,
543 L3INIT_CM_CORE_CM_GMAC_GMAC_CLKCTRL_REG_MODULEMODE, ENABLED);
545 while(CSL_L3INIT_CM_CORE_CM_GMAC_GMAC_CLKCTRL_REG_IDLEST_FUNC !=
546 CSL_FEXT(l3InitCmReg->CM_GMAC_GMAC_CLKCTRL_REG,
547 L3INIT_CM_CORE_CM_GMAC_GMAC_CLKCTRL_REG_IDLEST));
549 CSL_FINST(l4PerCmReg->CM_L4PER2_L4_PER2_CLKCTRL_REG,
550 L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_MODULEMODE, AUTO);
552 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_IDLEST_FUNC !=
553 CSL_FEXT(l4PerCmReg->CM_L4PER2_L4_PER2_CLKCTRL_REG,
554 L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_IDLEST));
556 CSL_FINST(l4PerCmReg->CM_L4PER3_L4_PER3_CLKCTRL_REG,
557 L4PER_CM_CORE_COMPONENT_CM_L4PER3_L4_PER3_CLKCTRL_REG_MODULEMODE, AUTO);
559 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER3_L4_PER3_CLKCTRL_REG_IDLEST_FUNC !=
560 CSL_FEXT(l4PerCmReg->CM_L4PER3_L4_PER3_CLKCTRL_REG,
561 L4PER_CM_CORE_COMPONENT_CM_L4PER3_L4_PER3_CLKCTRL_REG_IDLEST));
563 CSL_FINST(l4PerCmReg->CM_L4PER_GPIO2_CLKCTRL_REG,
564 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG_MODULEMODE, AUTO);
566 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG_IDLEST_FUNC !=
567 CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO2_CLKCTRL_REG,
568 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG_IDLEST));
570 CSL_FINST(l4PerCmReg->CM_L4PER_GPIO3_CLKCTRL_REG,
571 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG_MODULEMODE, AUTO);
573 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG_IDLEST_FUNC !=
574 CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO3_CLKCTRL_REG,
575 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG_IDLEST));
577 CSL_FINST(l4PerCmReg->CM_L4PER_GPIO4_CLKCTRL_REG,
578 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG_MODULEMODE, AUTO);
580 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG_IDLEST_FUNC !=
581 CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO4_CLKCTRL_REG,
582 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG_IDLEST));
584 CSL_FINST(l4PerCmReg->CM_L4PER_GPIO5_CLKCTRL_REG,
585 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO5_CLKCTRL_REG_MODULEMODE, AUTO);
587 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO5_CLKCTRL_REG_IDLEST_FUNC !=
588 CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO5_CLKCTRL_REG,
589 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO5_CLKCTRL_REG_IDLEST));
591 CSL_FINST(l4PerCmReg->CM_L4PER_GPIO6_CLKCTRL_REG,
592 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO6_CLKCTRL_REG_MODULEMODE, AUTO);
594 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO6_CLKCTRL_REG_IDLEST_FUNC !=
595 CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO6_CLKCTRL_REG,
596 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO6_CLKCTRL_REG_IDLEST));
598 CSL_FINST(l4PerCmReg->CM_L4PER_GPIO7_CLKCTRL_REG,
599 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO7_CLKCTRL_REG_MODULEMODE, AUTO);
601 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO7_CLKCTRL_REG_IDLEST_FUNC !=
602 CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO7_CLKCTRL_REG,
603 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO7_CLKCTRL_REG_IDLEST));
605 CSL_FINST(l4PerCmReg->CM_L4PER_GPIO8_CLKCTRL_REG,
606 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO8_CLKCTRL_REG_MODULEMODE, AUTO);
608 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO8_CLKCTRL_REG_IDLEST_FUNC !=
609 CSL_FEXT(l4PerCmReg->CM_L4PER_GPIO8_CLKCTRL_REG,
610 L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO8_CLKCTRL_REG_IDLEST));
612 CSL_FINST(l4PerCmReg->CM_L4PER_I2C1_CLKCTRL_REG,
613 L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C1_CLKCTRL_REG_MODULEMODE, ENABLE);
615 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C1_CLKCTRL_REG_IDLEST_FUNC !=
616 CSL_FEXT(l4PerCmReg->CM_L4PER_I2C1_CLKCTRL_REG,
617 L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C1_CLKCTRL_REG_IDLEST));
619 CSL_FINST(l4PerCmReg->CM_L4PER_I2C2_CLKCTRL_REG,
620 L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C2_CLKCTRL_REG_MODULEMODE, ENABLE);
622 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C2_CLKCTRL_REG_IDLEST_FUNC !=
623 CSL_FEXT(l4PerCmReg->CM_L4PER_I2C2_CLKCTRL_REG,
624 L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C2_CLKCTRL_REG_IDLEST));
626 CSL_FINST(l4PerCmReg->CM_L4PER_I2C3_CLKCTRL_REG,
627 L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_MODULEMODE, ENABLE);
629 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_IDLEST_FUNC !=
630 CSL_FEXT(l4PerCmReg->CM_L4PER_I2C3_CLKCTRL_REG,
631 L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C3_CLKCTRL_REG_IDLEST));
633 CSL_FINST(l4PerCmReg->CM_L4PER_I2C4_CLKCTRL_REG,
634 L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C4_CLKCTRL_REG_MODULEMODE, ENABLE);
636 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C4_CLKCTRL_REG_IDLEST_FUNC !=
637 CSL_FEXT(l4PerCmReg->CM_L4PER_I2C4_CLKCTRL_REG,
638 L4PER_CM_CORE_COMPONENT_CM_L4PER_I2C4_CLKCTRL_REG_IDLEST));
640 CSL_FINST(l4PerCmReg->CM_L4PER_L4_PER1_CLKCTRL_REG,
641 L4PER_CM_CORE_COMPONENT_CM_L4PER_L4_PER1_CLKCTRL_REG_MODULEMODE, AUTO);
643 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_L4_PER1_CLKCTRL_REG_IDLEST_FUNC !=
644 CSL_FEXT(l4PerCmReg->CM_L4PER_L4_PER1_CLKCTRL_REG,
645 L4PER_CM_CORE_COMPONENT_CM_L4PER_L4_PER1_CLKCTRL_REG_IDLEST));
647 CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI1_CLKCTRL_REG,
648 L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_MODULEMODE, ENABLE);
650 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_IDLEST_FUNC !=
651 CSL_FEXT(l4PerCmReg->CM_L4PER_MCSPI1_CLKCTRL_REG,
652 L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_IDLEST));
654 CSL_FINST(l4PerCmReg->CM_L4PER_MMC3_CLKCTRL_REG,
655 L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC3_CLKCTRL_REG_MODULEMODE, ENABLE);
657 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC3_CLKCTRL_REG_IDLEST_FUNC !=
658 CSL_FEXT(l4PerCmReg->CM_L4PER_MMC3_CLKCTRL_REG,
659 L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC3_CLKCTRL_REG_IDLEST));
661 CSL_FINST(l4PerCmReg->CM_L4PER_MMC4_CLKCTRL_REG,
662 L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC4_CLKCTRL_REG_MODULEMODE, ENABLE);
664 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC4_CLKCTRL_REG_IDLEST_FUNC !=
665 CSL_FEXT(l4PerCmReg->CM_L4PER_MMC4_CLKCTRL_REG,
666 L4PER_CM_CORE_COMPONENT_CM_L4PER_MMC4_CLKCTRL_REG_IDLEST));
668 CSL_FINST(l4PerCmReg->CM_L4PER_TIMER10_CLKCTRL_REG,
669 L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER10_CLKCTRL_REG_MODULEMODE, ENABLE);
671 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER10_CLKCTRL_REG_IDLEST_FUNC !=
672 CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER10_CLKCTRL_REG,
673 L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER10_CLKCTRL_REG_IDLEST));
675 CSL_FINST(l4PerCmReg->CM_L4PER_TIMER11_CLKCTRL_REG,
676 L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_MODULEMODE, ENABLE);
678 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST_FUNC !=
679 CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER11_CLKCTRL_REG,
680 L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST));
682 CSL_FINST(l4PerCmReg->CM_L4PER_TIMER2_CLKCTRL_REG,
683 L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_MODULEMODE, ENABLE);
685 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST_FUNC !=
686 CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER2_CLKCTRL_REG,
687 L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER11_CLKCTRL_REG_IDLEST));
689 CSL_FINST(l4PerCmReg->CM_L4PER_TIMER3_CLKCTRL_REG,
690 L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER3_CLKCTRL_REG_MODULEMODE, ENABLE);
692 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER3_CLKCTRL_REG_IDLEST_FUNC !=
693 CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER3_CLKCTRL_REG,
694 L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER3_CLKCTRL_REG_IDLEST));
696 CSL_FINST(l4PerCmReg->CM_L4PER_TIMER4_CLKCTRL_REG,
697 L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_MODULEMODE, ENABLE);
699 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_IDLEST_FUNC !=
700 CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER4_CLKCTRL_REG,
701 RTC_CM_CORE_AON_CM_RTC_RTCSS_CLKCTRL_REG_IDLEST));
703 CSL_FINST(l4PerCmReg->CM_L4PER_TIMER9_CLKCTRL_REG,
704 L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_MODULEMODE, ENABLE);
706 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_IDLEST_FUNC !=
707 CSL_FEXT(l4PerCmReg->CM_L4PER_TIMER9_CLKCTRL_REG,
708 L4PER_CM_CORE_COMPONENT_CM_L4PER_TIMER4_CLKCTRL_REG_IDLEST));
710 CSL_FINST(l4PerCmReg->CM_L4PER2_QSPI_CLKCTRL_REG,
711 L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_MODULEMODE, ENABLED);
713 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_IDLEST_FUNC !=
714 CSL_FEXT(l4PerCmReg->CM_L4PER2_QSPI_CLKCTRL_REG,
715 L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_IDLEST));
717 CSL_FINST(l4PerCmReg->CM_L4PER2_QSPI_CLKCTRL_REG,
718 L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_CLKSEL_DIV, DIV4);
720 CSL_FINST(l4PerCmReg->CM_L4PER2_QSPI_CLKCTRL_REG,
721 L4PER_CM_CORE_COMPONENT_CM_L4PER2_QSPI_CLKCTRL_REG_CLKSEL_SOURCE, SEL_PER_QSPI_CLK);
723 CSL_FINST(l4PerCmReg->CM_L4PER_UART1_CLKCTRL_REG,
724 L4PER_CM_CORE_COMPONENT_CM_L4PER_UART1_CLKCTRL_REG_MODULEMODE, ENABLE);
726 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART1_CLKCTRL_REG_IDLEST_FUNC !=
727 CSL_FEXT(l4PerCmReg->CM_L4PER_UART1_CLKCTRL_REG,
728 L4PER_CM_CORE_COMPONENT_CM_L4PER_UART1_CLKCTRL_REG_IDLEST));
730 CSL_FINST(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,
731 L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_MODULEMODE, ENABLE);
733 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST_FUNC !=
734 CSL_FEXT(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,
735 L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST));
737 CSL_FINS(mpuCmReg->CM_MPU_MPU_CLKCTRL_REG,
738 MPU_CM_CORE_AON_CM_MPU_MPU_CLKCTRL_REG_MODULEMODE, 2U);
740 while(CSL_MPU_CM_CORE_AON_CM_MPU_MPU_CLKCTRL_REG_IDLEST_FUNC !=
741 CSL_FEXT(mpuCmReg->CM_MPU_MPU_CLKCTRL_REG,
742 MPU_CM_CORE_AON_CM_MPU_MPU_CLKCTRL_REG_IDLEST));
744 CSL_FINST(vpeCmReg->CM_VPE_VPE_CLKCTRL_REG,
745 VPE_CM_CORE_AON_CM_VPE_VPE_CLKCTRL_REG_MODULEMODE, AUTO);
747 while(CSL_VPE_CM_CORE_AON_CM_VPE_VPE_CLKCTRL_REG_IDLEST_FUNC !=
748 CSL_FEXT(vpeCmReg->CM_VPE_VPE_CLKCTRL_REG,
749 VPE_CM_CORE_AON_CM_VPE_VPE_CLKCTRL_REG_IDLEST));
751 CSL_FINST(wkupAonCmReg->CM_WKUPAON_GPIO1_CLKCTRL_REG,
752 WKUPAON_CM_CM_WKUPAON_GPIO1_CLKCTRL_REG_MODULEMODE, AUTO);
754 while(CSL_WKUPAON_CM_CM_WKUPAON_GPIO1_CLKCTRL_REG_IDLEST_FUNC !=
755 CSL_FEXT(wkupAonCmReg->CM_WKUPAON_GPIO1_CLKCTRL_REG,
756 WKUPAON_CM_CM_WKUPAON_GPIO1_CLKCTRL_REG_IDLEST));
758 CSL_FINST(wkupAonCmReg->CM_WKUPAON_TIMER1_CLKCTRL_REG,
759 WKUPAON_CM_CM_WKUPAON_TIMER1_CLKCTRL_REG_MODULEMODE, ENABLE);
761 while(CSL_WKUPAON_CM_CM_WKUPAON_TIMER1_CLKCTRL_REG_IDLEST_FUNC !=
762 CSL_FEXT(wkupAonCmReg->CM_WKUPAON_TIMER1_CLKCTRL_REG,
763 WKUPAON_CM_CM_WKUPAON_TIMER1_CLKCTRL_REG_IDLEST));
765 CSL_FINS(wkupAonCmReg->CM_WKUPAON_TIMER12_CLKCTRL_REG,
766 WKUPAON_CM_CM_WKUPAON_TIMER12_CLKCTRL_REG_MODULEMODE, 2U);
768 while(CSL_WKUPAON_CM_CM_WKUPAON_TIMER12_CLKCTRL_REG_IDLEST_FUNC !=
769 CSL_FEXT(wkupAonCmReg->CM_WKUPAON_TIMER12_CLKCTRL_REG,
770 WKUPAON_CM_CM_WKUPAON_TIMER12_CLKCTRL_REG_IDLEST));
772 CSL_FINS(wkupAonCmReg->CM_WKUPAON_WD_TIMER1_CLKCTRL_REG,
773 WKUPAON_CM_CM_WKUPAON_WD_TIMER1_CLKCTRL_REG_MODULEMODE, 2U);
775 while(CSL_WKUPAON_CM_CM_WKUPAON_WD_TIMER1_CLKCTRL_REG_IDLEST_FUNC !=
776 CSL_FEXT(wkupAonCmReg->CM_WKUPAON_WD_TIMER1_CLKCTRL_REG,
777 WKUPAON_CM_CM_WKUPAON_WD_TIMER1_CLKCTRL_REG_IDLEST));
779 CSL_FINST(wkupAonCmReg->CM_WKUPAON_WD_TIMER2_CLKCTRL_REG,
780 WKUPAON_CM_CM_WKUPAON_WD_TIMER2_CLKCTRL_REG_MODULEMODE, ENABLE);
782 while(CSL_WKUPAON_CM_CM_WKUPAON_WD_TIMER2_CLKCTRL_REG_IDLEST_FUNC !=
783 CSL_FEXT(wkupAonCmReg->CM_WKUPAON_WD_TIMER2_CLKCTRL_REG,
784 WKUPAON_CM_CM_WKUPAON_WD_TIMER2_CLKCTRL_REG_IDLEST));
786 /* PRCM Specialized module mode setting functions */
787 CSL_FINST(ivaCmReg->CM_IVA_SL2_CLKCTRL_REG,
788 IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_MODULEMODE, AUTO);
790 while(CSL_IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_IDLEST_DISABLE ==
791 CSL_FEXT(ivaCmReg->CM_IVA_SL2_CLKCTRL_REG,
792 IVA_CM_CORE_CM_IVA_SL2_CLKCTRL_REG_IDLEST));
794 CSL_FINST(ivaCmReg->CM_IVA_IVA_CLKCTRL_REG,
795 IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_MODULEMODE, AUTO);
797 while(CSL_IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_IDLEST_DISABLE ==
798 CSL_FEXT(ivaCmReg->CM_IVA_IVA_CLKCTRL_REG,
799 IVA_CM_CORE_CM_IVA_IVA_CLKCTRL_REG_IDLEST));
801 CSL_FINST(coreCmReg->CM_IPU2_IPU2_CLKCTRL_REG,
802 CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_MODULEMODE, AUTO);
804 while(CSL_CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_IDLEST_DISABLE ==
805 CSL_FEXT(coreCmReg->CM_IPU2_IPU2_CLKCTRL_REG,
806 CORE_CM_CORE_CM_IPU2_IPU2_CLKCTRL_REG_IDLEST));
808 CSL_FINST(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,
809 DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_MODULEMODE, ENABLED);
810 /*
811 while(CSL_DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST_FUNC !=
812 CSL_FEXT(dssCmReg->CM_DSS_DSS_CLKCTRL_REG,
813 DSS_CM_CORE_CM_DSS_DSS_CLKCTRL_REG_IDLEST));
814 */
816 CSL_FINST(ipuCmReg->CM_IPU1_IPU1_CLKCTRL_REG,
817 IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_MODULEMODE, AUTO);
818 /*
819 while(CSL_IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_IDLEST_FUNC !=
820 CSL_FEXT(ipuCmReg->CM_IPU1_IPU1_CLKCTRL_REG,
821 IPU_CM_CORE_AON_CM_IPU1_IPU1_CLKCTRL_REG_IDLEST));
822 */
823 l4PerCmReg->CM_L4PER_GPIO2_CLKCTRL_REG |= (
824 (CM_L4PER_GPIO2_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO2_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
825 (CM_L4PER_GPIO2_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO2_CLKCTRL_MODULEMODE_SHIFT));
827 l4PerCmReg->CM_L4PER_GPIO3_CLKCTRL_REG |= (
828 (CM_L4PER_GPIO3_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO3_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
829 (CM_L4PER_GPIO3_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO3_CLKCTRL_MODULEMODE_SHIFT));
831 l4PerCmReg->CM_L4PER_GPIO4_CLKCTRL_REG |= (
832 (CM_L4PER_GPIO4_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO4_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
833 (CM_L4PER_GPIO4_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO4_CLKCTRL_MODULEMODE_SHIFT));
835 l4PerCmReg->CM_L4PER_GPIO5_CLKCTRL_REG |= (
836 (CM_L4PER_GPIO5_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO5_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
837 (CM_L4PER_GPIO5_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO5_CLKCTRL_MODULEMODE_SHIFT));
839 l4PerCmReg->CM_L4PER_GPIO6_CLKCTRL_REG |= (
840 (CM_L4PER_GPIO6_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO6_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
841 (CM_L4PER_GPIO6_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO6_CLKCTRL_MODULEMODE_SHIFT));
843 l4PerCmReg->CM_L4PER_GPIO7_CLKCTRL_REG |= (
844 (CM_L4PER_GPIO7_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO7_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
845 (CM_L4PER_GPIO7_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO7_CLKCTRL_MODULEMODE_SHIFT));
847 l4PerCmReg->CM_L4PER_GPIO8_CLKCTRL_REG |= (
848 (CM_L4PER_GPIO8_CLKCTRL_OPTFCLKEN_DBCLK_FCLK_EN << CM_L4PER_GPIO8_CLKCTRL_OPTFCLKEN_DBCLK_SHIFT) |
849 (CM_L4PER_GPIO8_CLKCTRL_MODULEMODE_AUTO << CM_L4PER_GPIO8_CLKCTRL_MODULEMODE_SHIFT));
851 CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI2_CLKCTRL_REG,
852 L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI2_CLKCTRL_REG_MODULEMODE, ENABLE);
854 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI2_CLKCTRL_REG_IDLEST_FUNC !=
855 CSL_FEXT(l4PerCmReg->CM_L4PER_MCSPI2_CLKCTRL_REG,
856 L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI2_CLKCTRL_REG_IDLEST));
858 CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI3_CLKCTRL_REG,
859 L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI3_CLKCTRL_REG_MODULEMODE, ENABLE);
861 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI3_CLKCTRL_REG_IDLEST_FUNC !=
862 CSL_FEXT(l4PerCmReg->CM_L4PER_MCSPI3_CLKCTRL_REG,
863 L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI3_CLKCTRL_REG_IDLEST));
865 CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG,
866 L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_MODULEMODE, DISABLED);
868 CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG,
869 L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_MODULEMODE, ENABLE);
871 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_IDLEST_FUNC !=
872 CSL_FEXT(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG,
873 L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_IDLEST));
875 CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS2_CLKCTRL_REG,
876 L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS2_CLKCTRL_REG_MODULEMODE, DISABLED);
878 CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS2_CLKCTRL_REG,
879 L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS2_CLKCTRL_REG_MODULEMODE, ENABLE);
881 while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_L4_PER2_CLKCTRL_REG_IDLEST_FUNC !=
882 CSL_FEXT(l4PerCmReg->CM_L4PER2_PRUSS2_CLKCTRL_REG,
883 L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS2_CLKCTRL_REG_IDLEST));
885 while (CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_CLK_ACT !=
886 CSL_FEXT(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
887 L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_CLK));
889 while (CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_IEP_CLK_ACT !=
890 CSL_FEXT(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
891 L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_ICSS_IEP_CLK));
893 while (CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_PER_192M_GFCLK_ACT !=
894 CSL_FEXT(l4PerCmReg->CM_L4PER2_CLKSTCTRL_REG,
895 L4PER_CM_CORE_COMPONENT_CM_L4PER2_CLKSTCTRL_REG_CLKACTIVITY_PER_192M_GFCLK));
897 return BOARD_SOK;
898 }