psdk_cust/pdk_k2g_1_0_1_1_eng/packages/ti/board/src/idkAM572x/idkAM572x_ddr.c

   1 /******************************************************************************
   2  * Copyright (c) 2010-2015 Texas Instruments Incorporated - http://www.ti.com
   3  *
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   9  *    notice, this list of conditions and the following disclaimer.
  10  *
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  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the
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  18  *    from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  *****************************************************************************/
  33
  34 #include "board_cfg.h"
  35 #include "board_internal.h"
  36
  37 #include <ti/csl/csl_emif4fAux.h>
  38 #include <ti/csl/cslr_dmm.h>
  39 #include <ti/csl/cslr_ma_mpu_lsm.h>
  40 #include <ti/csl/src/ip/emif4/V2/csl_emif4d5.h>
  41
  42 /** \brief Compute EMIF phy control. */
  43 #define EXT_PHY_CTRL_VALUE(ctrlSlaveRatio)                                     \
  44     ((ctrlSlaveRatio << 20U) | (ctrlSlaveRatio << 10U) | (ctrlSlaveRatio << 0U))
  45
  46 /** \brief Compute EMIF phy FIFO WE. */
  47 #define EXT_PHY_FIFO_WE_VALUE(fifoWeSlaveRatio)                                \
  48     ((fifoWeSlaveRatio << 16U) | (fifoWeSlaveRatio << 0U))
  49
  50 /** \brief Compute EMIF phy read DQS. */
  51 #define EXT_PHY_RD_DQS_VALUE(rdDqsSlaveRatio)                                  \
  52     ((rdDqsSlaveRatio << 16U) | (rdDqsSlaveRatio << 0U))
  53
  54 /** \brief Compute EMIF phy write data. */
  55 #define EXT_PHY_WR_DATA_VALUE(wrDataslaveRatio)                                \
  56     ((wrDataslaveRatio << 16U) | (wrDataslaveRatio << 0U))
  57
  58 /** \brief Compute EMIF phy write DQS. */
  59 #define EXT_PHY_WR_DQS_VALUE(wrDqsSlaveRatio)                                  \
  60     ((wrDqsSlaveRatio << 16U) | (wrDqsSlaveRatio << 0U))
  61
  62 /** \brief Compute EMIF phy DQ. */
  63 #define EXT_PHY_DQ_VALUE(dqOffset)                                             \
  64     ((dqOffset << 21U) | (dqOffset << 14U) | (dqOffset << 7U) | (dqOffset << 0U))
  65
  66 /** \brief Compute EMIF phy gate level init. */
  67 #define EXT_PHY_GATE_LVL_INIT_VALUE(gateLvlInitRatio)                          \
  68     ((gateLvlInitRatio << 16U) | (gateLvlInitRatio << 0U))
  69
  70 /** \brief Compute EMIF phy gate level init. */
  71 #define EXT_PHY_WR_LVL_INIT_VALUE(wrLvlInitRatio)                              \
  72     ((wrLvlInitRatio << 16U) | (wrLvlInitRatio << 0U))
  73
  74 /** \brief Compute EMIF phy . */
  75 #define EXT_PHY_RANK0_DELAY_VALUE(dqOffset, gateLvlInitRatio, rank0Delay,      \
  76     wrDataslaveRatio)                                                          \
  77     ((dqOffset << 24U) | (gateLvlInitRatio << 16U) | (rank0Delay << 12U) |     \
  78     (wrDataslaveRatio << 0U))
  79
  80 /** \brief Compute EMIF phy slave and Rank0 delays. */
  81 #define EXT_PHY_RANK0_DELAY_MODE(dqOffset, gateLvlInitMode, rank0Delay,        \
  82     wrDataslaveDelay)                                                          \
  83     ((dqOffset << 24U) | (gateLvlInitMode << 16U) | (rank0Delay << 12U) |      \
  84     (wrDataslaveDelay << 0U))
  85
  86 /** \brief Compute FIFO_WE_IN and Phy control slave delay .*/
  87 #define EXT_PHY_FIFO_WE_SLAVE_CTRL_DELAY(fifoWeInDelay, ctrlSlaveDelay)        \
  88     ((fifoWeInDelay << 16U) | (ctrlSlaveDelay << 0U))
  89
  90 /** \brief Compute WR_LVL_NUM_DQ0 and GATE_LVL_NUM_DQ0.*/
  91 #define EXT_PHY_WR_LVL_GATE_LVL_NUM_DQ0(wrLvlNumDq0, gateLvlNumDq0)            \
  92     ((wrLvlNumDq0 << 4U) | (gateLvlNumDq0 << 0U))
  93
  94 /** \brief Compute Read and WriteDQS slave delay. */
  95 #define EXT_PHY_WR_RD_DQS_SLAVE_DELAY(wrDqsSlaveDelay, rdDqsSlaveDelay)        \
  96     ((wrDqsSlaveDelay << 16U) | (rdDqsSlaveDelay << 0U))
  97
  98 #define DDR_PHY_CTRL1_VALUE(emif_phy_read_latency, emif_phy_fast_dll_lock,       \
  99     emif_phy_dll_lock_diff, emif_phy_invert_clkout, emif_phy_dis_calib_rst,    \
 100     emif_phy_half_delay_mode, emif_phy_levelling_disabled)                     \
 101     ((emif_phy_read_latency << 0U) | (emif_phy_fast_dll_lock << 9U) |          \
 102     (emif_phy_dll_lock_diff << 10U) | (emif_phy_invert_clkout << 18U) |        \
 103     (emif_phy_dis_calib_rst << 19U) | (emif_phy_half_delay_mode << 21U) |      \
 104     (emif_phy_levelling_disabled))
 105
 106 #define MPU_DEVICE_PRM_REGS                              (0x4ae07d00U)
 107 #define PRM_RSTST_REG                                    (0x4U)
 108
 109 #define HW_WR_REG32(addr, data)   *(unsigned int*)(addr) =(unsigned int)(data)
 110 #define HW_RD_REG32(x)             (*((volatile uint32_t *)(x)))
 111
 112 /**< IODFT TLGC */
 113 uint32_t ioDftLogicCtrl;
 114 /**< Read Write level ramp window*/
 115 uint32_t readWriteLvlRampWin;
 116
 117 static void ddr_delay(uint32_t ix);
 118
 119 static void emif_ddr3_updateHwLevelOutput(CSL_emifHandle hEmif);
 120
 121 static void ddr_delay(uint32_t ix)
 122 {
 123     while (ix--) {
 124         asm("   NOP");
 125     }
 126 }
 127
 128 int emifConfigureDdr3
 129 (
 130     CSL_emifHandle hEmif,
 131     CSL_emifDdrConfig *ddr3Config,
 132     Uint32 enableHwLeveling
 133 );
 134
 135 /* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
 136 Board_STATUS Board_DDR3Init()
 137 {
 138     int retVal = BOARD_SOK;
 139     CSL_emifObj emifObj1;
 140     CSL_emifHandle hEmif1 = &emifObj1;
 141     CSL_emifDdrConfig ddr3Config1;
 142     CSL_emifObj emifObj2;
 143     CSL_emifHandle hEmif2 = &emifObj2;
 144     CSL_emifDdrConfig ddr3Config2;
 145     CSL_ckgen_cm_core_aonRegs *hCkgenCmCoreAon =
 146         (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
 147     CSL_control_core_padRegs *hCtrlCorePad =
 148         (CSL_control_core_padRegs *) CSL_MPU_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_REGS;
 149     CSL_control_core_wkupRegs *hCtrlCoreWkup =
 150         (CSL_control_core_wkupRegs *) CSL_MPU_CTRL_MODULE_WKUP_CORE_REGISTERS_REGS;
 151     CSL_DmmRegs *hDmmCfg =(CSL_DmmRegs *) CSL_MPU_DMM_CONF_REGS_REGS;
 152     CSL_MampuLsmRegs *hMampuLsm = (CSL_MampuLsmRegs *) CSL_MPU_MA_MPU_LSM_REGS;
 153
 154     hEmif1->regs = (CSL_emifRegsOvly)CSL_MPU_EMIF1_CONF_REGS_REGS;
 155     hEmif2->regs = (CSL_emifRegsOvly)CSL_MPU_EMIF2_CONF_REGS_REGS;
 156
 157     /* DLL override disable =0 ; enable = 1 */
 158     hCkgenCmCoreAon->CM_DLL_CTRL_REG = 0x00000000;
 159
 160     /*
 161      * CONTROL_DDR3CH1_0 -- channel_1 CMDs
 162      * -- 40Ohm Ron (011)
 163      * -- SR=slowest-3 (111) on CMDs
 164      * -- CLK SR=slow (011)
 165      * -- No pulls (00)
 166      */
 167     hCtrlCorePad->CONTROL_DDRCACH1_0 = 0x80808080;
 168
 169     /*
 170      * CONTROL_DDRCH1_0 -- channel_1 DATA byte 0+1
 171      * -- 40Ohm Ron (011)
 172      * -- SR=faster (001)
 173      * -- Pull-up (10) on DQS
 174      * -- No pull (00) on DQ
 175      */
 176     hCtrlCorePad->CONTROL_DDRCH1_0 = 0x40404040;
 177
 178     /*
 179      * CONTROL_DDRCH1_1 -- channel_1 DATA byte 2+3
 180      * -- 40Ohm Ron (011)
 181      * -- SR=faster (001)
 182      * -- Pull-up (10) on DQS
 183      * -- No pull (00) on DQ
 184      */
 185     hCtrlCorePad->CONTROL_DDRCH1_1 = 0x40404040;
 186
 187     /*
 188      * CONTROL_LPDDR2CH1_0
 189      * -- channel_1 LPDDR2 CMD PHYs IOs not used
 190      */
 191     hCtrlCorePad->CONTROL_DDRCH1_2 = 0x00404000U;
 192
 193     /*
 194      * CONTROL_DDR3CH2_0 -- channel_2 CMDs
 195      * -- 40Ohm Ron (011)
 196      * -- SR=slowest-3 (111) on CMDs
 197      * -- CLK SR=slow (011)
 198      * -- No pulls (00)
 199      */
 200     hCtrlCorePad->CONTROL_DDRCACH2_0 = 0x80808080;
 201
 202     /*
 203      * CONTROL_DDRCH2_0 -- channel_2 DATA byte 0+1
 204      * -- 40Ohm Ron (011)
 205      * -- SR=faster (001)
 206      * -- Pull-up (10) on DQS
 207      * -- No pull (00) on DQ
 208      */
 209     hCtrlCorePad->CONTROL_DDRCH2_0 = 0x40404040;
 210
 211     /*
 212      * CONTROL_DDRCH2_1 -- channel_2 DATA byte 2+3
 213      * -- 40Ohm Ron (011)
 214      * -- SR=faster (001)
 215      * -- Pull-up (10) on DQS
 216      * -- No pull (00) on DQ
 217      */
 218     hCtrlCorePad->CONTROL_DDRCH2_1 = 0x40404040;
 219
 220     /*
 221      * DDRIO_0 -- VREF cells
 222      * (CH1 DQ3/0 INT 2uA / Cap to GND / CMD1/0 DDR3 INT-OUT 32uA / Cap to GND)
 223      */
 224     hCtrlCorePad->CONTROL_DDRIO_0 = 0x00094A40U;
 225
 226     /*
 227      * DDRIO_1 -- VREF cells
 228      * (CH1 OUT 32uA Cap to GND / CH2 DQ3/0 INT 2uA / Cap to GND / CH2 OUT 32uA Cap to GND)
 229      */
 230     hCtrlCorePad->CONTROL_DDRIO_1 = 0x04A52000U;
 231
 232     /*
 233      * EMIF1_SDRAM_CONFIG_EXT
 234      * -- cslice_en[2:0]=111 / Local_odt=01 / dyn_pwrdn=1 / dis_reset=0 / rd_lvl_samples=11 (128)
 235      */
 236     /* EMIF1_EN_ECC = 0 */
 237     hCtrlCoreWkup->EMIF1_SDRAM_CONFIG_EXT = 0x0001C127U;
 238
 239     /*
 240      * EMIF2_SDRAM_CONFIG_EXT
 241      * -- slice_en[2:0]=111 / Local_odt=01 / dyn_pwrdn=1 / dis_reset=0 / rd_lvl_samples=11 (128)
 242      */
 243     hCtrlCoreWkup->EMIF2_SDRAM_CONFIG_EXT = 0x0001C127U;
 244
 245     ddr3Config1.emifDdrParam.ddrPhyCtrl = hEmif1->regs->DDR_PHY_CONTROL_2;
 246
 247     ddr3Config1.emifDdrParam.sdramTim1 = 0xCCCF36ABU;
 248     ddr3Config1.emifDdrParam.sdramTim2 = 0x308F7FDAU;
 249     ddr3Config1.emifDdrParam.sdramTim3 = 0x409F88A8U;
 250
 251     ddr3Config1.emifDdrParam.sdramCfg = 0x61851B32U;
 252     ddr3Config1.emifDdrParam.sdramCfg2 = 0x08000000U;
 253     ddr3Config1.emifDdrParam.sdramRefCtrl = 0x00001035U;
 254     ddr3Config1.emifDdrParam.zqConfig = 0x5007190BU;
 255     ddr3Config1.emifDdrParam.sdramPwrMngtCtrl = 0x00000000U;
 256
 257     ioDftLogicCtrl = hEmif1->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL;
 258     readWriteLvlRampWin = hEmif1->regs->READ_WRITE_LEVELING_RAMP_WINDOW;
 259
 260     ddr3Config1.emifDdrPhyParam.ctrlSlaveRatio = 0x80U;
 261     ddr3Config1.emifDdrPhyParam.dqOffset = 0x40U;
 262     ddr3Config1.emifDdrPhyParam.gateLevelInitMode = 0x01U;
 263     ddr3Config1.emifDdrPhyParam.fifoWeInDelay = 0x0U;
 264     ddr3Config1.emifDdrPhyParam.ctrlSlaveDelay = 0x0U;
 265     ddr3Config1.emifDdrPhyParam.readDqsSlaveDelay = 0x0020U;
 266     ddr3Config1.emifDdrPhyParam.writeDqsSlaveDelay = 0x0060U;
 267     ddr3Config1.emifDdrPhyParam.writeDataSlaveDelay = 0x80U;
 268
 269     ddr3Config1.emifDdrPhyParam.gateLevelRatio = 0x00U;
 270     ddr3Config1.emifDdrPhyParam.writeLevelInitRatio = 0x00;
 271     ddr3Config1.emifDdrPhyParam.writeDqsSlaveRatio = 0x60U;
 272     ddr3Config1.emifDdrPhyParam.fifoWeSlaveRatio = 0xBBU;
 273     ddr3Config1.emifDdrPhyParam.useRank0Delays = 0U;
 274
 275     ddr3Config1.emifDdrPhyParam.gateLevelNumDq0 = 0xFU;
 276     ddr3Config1.emifDdrPhyParam.writeLevelNumDq0 =
 277         hEmif1->regs->EXT_PHY_CONTROL_36;
 278
 279     retVal = emifConfigureDdr3(hEmif1, &ddr3Config1, 1U);
 280
 281     if(BOARD_SOK == retVal)
 282         {
 283         ddr3Config2.emifDdrParam.ddrPhyCtrl = hEmif2->regs->DDR_PHY_CONTROL_2;
 284         ddr3Config2.emifDdrParam.sdramTim1 = 0xCCCF36ABU;
 285         ddr3Config2.emifDdrParam.sdramTim2 = 0x308F7FDAU;
 286         ddr3Config2.emifDdrParam.sdramTim3 = 0x409F88A8U;
 287         ddr3Config2.emifDdrParam.sdramCfg = 0x61851B32U;
 288         ddr3Config2.emifDdrParam.sdramCfg2 = 0x00000000U;
 289         ddr3Config2.emifDdrParam.sdramRefCtrl = 0x00001035U;
 290         ddr3Config2.emifDdrParam.zqConfig = 0x0007190BU;
 291         ddr3Config2.emifDdrParam.sdramPwrMngtCtrl = 0x00000000U;
 292
 293         ioDftLogicCtrl = hEmif2->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL;
 294         readWriteLvlRampWin = hEmif2->regs->READ_WRITE_LEVELING_RAMP_WINDOW;
 295
 296         ddr3Config2.emifDdrPhyParam.ctrlSlaveRatio = 0x80U;
 297         ddr3Config2.emifDdrPhyParam.dqOffset = 0x40U;
 298         ddr3Config2.emifDdrPhyParam.gateLevelInitMode = 0x01U;
 299         ddr3Config2.emifDdrPhyParam.fifoWeInDelay = 0x0U;
 300         ddr3Config2.emifDdrPhyParam.ctrlSlaveDelay = 0x0U;
 301         ddr3Config2.emifDdrPhyParam.readDqsSlaveDelay = 0x0060U;
 302         ddr3Config2.emifDdrPhyParam.writeDqsSlaveDelay = 0x0080U;
 303         ddr3Config2.emifDdrPhyParam.writeDataSlaveDelay = 0x80U;
 304
 305         ddr3Config2.emifDdrPhyParam.gateLevelRatio = 0x00U;
 306         ddr3Config2.emifDdrPhyParam.writeLevelInitRatio = 0x00;
 307         ddr3Config2.emifDdrPhyParam.writeDqsSlaveRatio = 0x60U;
 308         ddr3Config2.emifDdrPhyParam.fifoWeSlaveRatio = 0xBBU;
 309         ddr3Config2.emifDdrPhyParam.useRank0Delays = 0U;
 310
 311         ddr3Config2.emifDdrPhyParam.gateLevelNumDq0 = 0xFU;
 312         ddr3Config2.emifDdrPhyParam.writeLevelNumDq0 =
 313             hEmif2->regs->EXT_PHY_CONTROL_36;
 314
 315         retVal = emifConfigureDdr3(hEmif2, &ddr3Config2, 1U);
 316
 317         if(BOARD_SOK == retVal)
 318         {
 319             /* Reset all LISA MAPs */
 320             hMampuLsm->MAP_0 = 0U;
 321             hMampuLsm->MAP_1 = 0U;
 322             hMampuLsm->MAP_2 = 0U;
 323             hMampuLsm->MAP_3 = 0U;
 324             hDmmCfg->LISA_MAP[0U] = 0U;
 325             hDmmCfg->LISA_MAP[1U] = 0U;
 326             hDmmCfg->LISA_MAP[2U] = 0U;
 327             hDmmCfg->LISA_MAP[3U] = 0U;
 328
 329             /* Two EMIFs in interleaved mode (2GB in total) */
 330             /* MA_LISA_MAP_i */
 331             hMampuLsm->MAP_0 = 0x80740300;
 332             hMampuLsm->MAP_1 = 0x80740300;
 333
 334             /* DMM_LISA_MAP_i */
 335             hDmmCfg->LISA_MAP[0U] = 0x80740300;
 336             hDmmCfg->LISA_MAP[1U] = 0x80740300;
 337         }
 338         else
 339         {
 340             retVal = BOARD_INIT_DDR_FAIL;
 341         }
 342     }
 343     else
 344     {
 345         retVal = BOARD_INIT_DDR_FAIL;
 346     }
 347
 348     return retVal;
 349 }
 350
 351 int emifConfigureDdr3
 352 (
 353     CSL_emifHandle hEmif,
 354     CSL_emifDdrConfig *ddr3Config,
 355     Uint32 enableHwLeveling
 356 )
 357 {
 358     int retVal = 0;
 359     Uint32 regVal = 0U;
 360     Uint32 emifPhyLevelDisable = 0U;
 361     Uint32 sdRamRefCtrlInit = 0x000040F1U;
 362
 363     /* Fields in DDR_PHY_CTRL_1 */
 364      /* Bit[21] - calculated using DataMacro/MDLL clock ratio
 365     * Set to 1 for 532M, so that PHY DLL runs at 266.
 366     * Set to 0 for 400M, so that PHY DLL runs at 400M.
 367     * Ensure PHY DLL lower limit of 266M is not violated.
 368     */
 369     uint32_t emifPhyHalfDelayMode = 1U;
 370     uint32_t emifPhyDisCalibRst = 0U;    /* Bit[19]    */
 371     uint32_t emifPhyInvertClkout = 1U;    /* Bit[18]    */
 372     uint32_t emifPhyDllLockDiff = 0x10U; /* Bit[17:10] */
 373     uint32_t emifPhyFastDllLock = 0U;   /* Bit[9]     */
 374     uint32_t emifPhyReadLatency = 0xBU;  /* Bit[4:0], Typically >= (CL + 4) */
 375
 376     if (0U != (HW_RD_REG32(MPU_DEVICE_PRM_REGS + PRM_RSTST_REG) &
 377         (PRM_RSTST_GLOBAL_WARM_SW_RST_MASK | PRM_RSTST_EXTERNAL_WARM_RST_MASK)))
 378     {
 379         /* Phy reset is required if you are coming back from a warm reset */
 380         regVal = hEmif->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL;
 381         regVal |= 0x400U;
 382         hEmif->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL = regVal;
 383     }
 384
 385     if(1U == emifPhyInvertClkout)
 386     {
 387         regVal = EXT_PHY_CTRL_VALUE((ddr3Config->emifDdrPhyParam.ctrlSlaveRatio + 0x80U));
 388         hEmif->regs->EXT_PHY_CONTROL_1 = regVal;
 389         hEmif->regs->EXT_PHY_CONTROL_1_SHADOW = regVal;
 390     }
 391
 392     /* PHY settings for DQ offset, DLL override delay, levelling etc. */
 393     regVal = EXT_PHY_FIFO_WE_SLAVE_CTRL_DELAY(ddr3Config->emifDdrPhyParam.fifoWeInDelay,
 394             ddr3Config->emifDdrPhyParam.ctrlSlaveDelay);
 395     hEmif->regs->EXT_PHY_CONTROL_22 = regVal;
 396     hEmif->regs->EXT_PHY_CONTROL_22_SHADOW = regVal;
 397
 398     regVal = EXT_PHY_WR_RD_DQS_SLAVE_DELAY(ddr3Config->emifDdrPhyParam.writeDqsSlaveDelay,
 399             ddr3Config->emifDdrPhyParam.readDqsSlaveDelay);
 400     hEmif->regs->EXT_PHY_CONTROL_23 = regVal;
 401     hEmif->regs->EXT_PHY_CONTROL_23_SHADOW = regVal;
 402
 403     regVal = EXT_PHY_RANK0_DELAY_VALUE(ddr3Config->emifDdrPhyParam.dqOffset,
 404             ddr3Config->emifDdrPhyParam.gateLevelInitMode,
 405             ddr3Config->emifDdrPhyParam.useRank0Delays,
 406             ddr3Config->emifDdrPhyParam.writeDataSlaveDelay);
 407     hEmif->regs->EXT_PHY_CONTROL_24 = regVal;
 408     hEmif->regs->EXT_PHY_CONTROL_24_SHADOW = regVal;
 409
 410     regVal = EXT_PHY_DQ_VALUE(ddr3Config->emifDdrPhyParam.dqOffset);
 411     hEmif->regs->EXT_PHY_CONTROL_25 = regVal;
 412     hEmif->regs->EXT_PHY_CONTROL_25_SHADOW = regVal;
 413
 414     /* Force Slave ratio values not required if HW levelling is enabled */
 415
 416     /* Use Init values if HW leveling is enabled */
 417     /* Gate level Init ratios */
 418     regVal = EXT_PHY_GATE_LVL_INIT_VALUE(ddr3Config->emifDdrPhyParam.gateLevelRatio);
 419     hEmif->regs->EXT_PHY_CONTROL_26 = regVal;
 420     hEmif->regs->EXT_PHY_CONTROL_26_SHADOW = regVal;
 421     hEmif->regs->EXT_PHY_CONTROL_27 = regVal;
 422     hEmif->regs->EXT_PHY_CONTROL_27_SHADOW = regVal;
 423     hEmif->regs->EXT_PHY_CONTROL_28 = regVal;
 424     hEmif->regs->EXT_PHY_CONTROL_28_SHADOW = regVal;
 425     hEmif->regs->EXT_PHY_CONTROL_29 = regVal;
 426     hEmif->regs->EXT_PHY_CONTROL_29_SHADOW = regVal;
 427     hEmif->regs->EXT_PHY_CONTROL_30 = regVal;
 428     hEmif->regs->EXT_PHY_CONTROL_30_SHADOW = regVal;
 429
 430     /* WR DQS Init ratios */
 431     regVal = EXT_PHY_WR_LVL_INIT_VALUE(ddr3Config->emifDdrPhyParam.writeLevelInitRatio);
 432     hEmif->regs->EXT_PHY_CONTROL_31 = regVal;
 433     hEmif->regs->EXT_PHY_CONTROL_31_SHADOW = regVal;
 434     hEmif->regs->EXT_PHY_CONTROL_32 = regVal;
 435     hEmif->regs->EXT_PHY_CONTROL_32_SHADOW = regVal;
 436     hEmif->regs->EXT_PHY_CONTROL_33 = regVal;
 437     hEmif->regs->EXT_PHY_CONTROL_33_SHADOW = regVal;
 438     hEmif->regs->EXT_PHY_CONTROL_34 = regVal;
 439     hEmif->regs->EXT_PHY_CONTROL_34_SHADOW = regVal;
 440     hEmif->regs->EXT_PHY_CONTROL_35 = regVal;
 441     hEmif->regs->EXT_PHY_CONTROL_35_SHADOW = regVal;
 442
 443     regVal = hEmif->regs->EXT_PHY_CONTROL_36;
 444     hEmif->regs->EXT_PHY_CONTROL_36 = regVal;
 445     hEmif->regs->EXT_PHY_CONTROL_36_SHADOW = regVal;
 446
 447     regVal = hEmif->regs->SDRAM_REFRESH_CONTROL;
 448     regVal = (regVal | CSL_EMIF4D5_SDRAM_REFRESH_CONTROL_INITREF_DIS_MASK |
 449             sdRamRefCtrlInit);
 450     hEmif->regs->SDRAM_REFRESH_CONTROL_SHADOW = regVal;
 451     hEmif->regs->SDRAM_REFRESH_CONTROL = regVal;
 452
 453         /* Set up the EMIF registers */
 454     hEmif->regs->SDRAM_TIMING_1 = ddr3Config->emifDdrParam.sdramTim1;
 455     hEmif->regs->SDRAM_TIMING_1_SHADOW = ddr3Config->emifDdrParam.sdramTim1;
 456     hEmif->regs->SDRAM_TIMING_2 = ddr3Config->emifDdrParam.sdramTim2;
 457     hEmif->regs->SDRAM_TIMING_2_SHADOW = ddr3Config->emifDdrParam.sdramTim2;
 458     hEmif->regs->SDRAM_TIMING_3 = ddr3Config->emifDdrParam.sdramTim3;
 459     hEmif->regs->SDRAM_TIMING_3_SHADOW = ddr3Config->emifDdrParam.sdramTim3;
 460
 461     hEmif->regs->POWER_MANAGEMENT_CONTROL = ddr3Config->emifDdrParam.sdramPwrMngtCtrl;
 462     hEmif->regs->POWER_MANAGEMENT_CONTROL_SHADOW = ddr3Config->emifDdrParam.sdramPwrMngtCtrl;
 463
 464     hEmif->regs->OCP_CONFIG = 0x0A500000U;
 465
 466     hEmif->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL = ioDftLogicCtrl;
 467     hEmif->regs->DLL_CALIB_CTRL = 0x00050000U;
 468     hEmif->regs->DLL_CALIB_CTRL_SHADOW = 0x00050000U;
 469     hEmif->regs->SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG = ddr3Config->emifDdrParam.zqConfig;
 470
 471     hEmif->regs->READ_WRITE_LEVELING_RAMP_WINDOW = readWriteLvlRampWin;
 472     hEmif->regs->READ_WRITE_LEVELING_RAMP_CONTROL = 0x80000000;
 473     hEmif->regs->READ_WRITE_LEVELING_CONTROL = 0U;
 474
 475     regVal = DDR_PHY_CTRL1_VALUE(emifPhyReadLatency, emifPhyFastDllLock,
 476                 emifPhyDllLockDiff, emifPhyInvertClkout, emifPhyDisCalibRst,
 477                 emifPhyHalfDelayMode, emifPhyLevelDisable);
 478     hEmif->regs->DDR_PHY_CONTROL_1 = regVal;
 479     hEmif->regs->DDR_PHY_CONTROL_1_SHADOW = regVal;
 480
 481     /* Backup of the previous value. */
 482     hEmif->regs->DDR_PHY_CONTROL_2 = ddr3Config->emifDdrParam.ddrPhyCtrl;
 483
 484     hEmif->regs->PRIORITY_TO_CLASS_OF_SERVICE_MAPPING = 0U;
 485     hEmif->regs->CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING = 0U;
 486     hEmif->regs->CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING = 0U;
 487     hEmif->regs->READ_WRITE_EXECUTION_THRESHOLD = 0x00000305U;
 488     hEmif->regs->COS_CONFIG = 0x00FFFFFFU;
 489
 490     /* SDRAM_REF_CTRL_INIT:
 491      * For DDR3:   value used initially to get 500us delay between
 492      *             RESET de-assertion to CKE assertion after power-up
 493      */
 494     hEmif->regs->SDRAM_REFRESH_CONTROL_SHADOW = 0x000040F1U;
 495     hEmif->regs->SDRAM_REFRESH_CONTROL = 0x000040F1U;
 496     hEmif->regs->SDRAM_CONFIG_2 = ddr3Config->emifDdrParam.sdramCfg2;
 497     hEmif->regs->SDRAM_CONFIG = ddr3Config->emifDdrParam.sdramCfg;
 498
 499     ddr_delay(100000);
 500
 501     /* Now update with the correct refresh time */
 502     hEmif->regs->SDRAM_REFRESH_CONTROL_SHADOW = ddr3Config->emifDdrParam.sdramRefCtrl;
 503     hEmif->regs->SDRAM_REFRESH_CONTROL = ddr3Config->emifDdrParam.sdramRefCtrl;
 504
 505         /* If ECC is enabled. */
 506         hEmif->regs->ECC_ADDRESS_RANGE_1 = 0U;
 507         hEmif->regs->ECC_ADDRESS_RANGE_2 = 0U;
 508         hEmif->regs->ECC_CTRL_REG = (CSL_EMIF4D5_ECC_CTRL_REG_REG_ECC_EN_MASK |
 509                 CSL_EMIF4D5_ECC_CTRL_REG_REG_ECC_ADDR_RGN_PROT_MASK);
 510
 511     /* Launch Full HW levelling. */
 512     regVal = hEmif->regs->EXT_PHY_CONTROL_36;
 513     regVal = (regVal | 0x00000100U);
 514     hEmif->regs->EXT_PHY_CONTROL_36 = regVal;
 515     regVal = hEmif->regs->EXT_PHY_CONTROL_36_SHADOW;
 516     regVal = (regVal | 0x00000100U);
 517     hEmif->regs->EXT_PHY_CONTROL_36_SHADOW = regVal;
 518
 519     /* Disable SDRAM refreshes before levelling */
 520     regVal = hEmif->regs->SDRAM_REFRESH_CONTROL;
 521     regVal = regVal | CSL_EMIF4D5_SDRAM_REFRESH_CONTROL_INITREF_DIS_MASK;
 522     hEmif->regs->SDRAM_REFRESH_CONTROL = regVal;
 523
 524     /* RDWR_LVL_CTRL */
 525     hEmif->regs->READ_WRITE_LEVELING_CONTROL =
 526         CSL_EMIF4D5_READ_WRITE_LEVELING_CONTROL_RDWRLVLFULL_START_MASK;
 527
 528     /* Some clock cycle delay for refresh to complete. */
 529     ddr_delay(30000U);
 530
 531     /* Wait for the levelling procedure to complete */
 532     while((hEmif->regs->READ_WRITE_LEVELING_CONTROL & 0x80000000) != 0x0U);
 533
 534     /* Enable SDRAM refreshes after levelling */
 535     regVal = hEmif->regs->SDRAM_REFRESH_CONTROL;
 536     regVal = (regVal & ~CSL_EMIF4D5_SDRAM_REFRESH_CONTROL_INITREF_DIS_MASK);
 537     hEmif->regs->SDRAM_REFRESH_CONTROL = regVal;
 538
 539     if((hEmif->regs->STATUS & 0x70) != 0U)
 540     {
 541         /* Indicates Hardware levelling timeout. */
 542         retVal = -1;
 543     }
 544     else
 545     {
 546         emif_ddr3_updateHwLevelOutput(hEmif);
 547
 548         hEmif->regs->ECC_CTRL_REG = 0U;
 549     }
 550
 551     return retVal;
 552 }
 553
 554 static void emif_ddr3_updateHwLevelOutput(CSL_emifHandle hEmif)
 555 {
 556     /* Following function is needed for whenever CORE can go in and out of
 557     * INACTIVE/CSWR.
 558     */
 559     Uint32 regVal = 0U;
 560
 561     /*
 562     ** Updating slave ratios in PHY_STATUSx registers as per HW levelling output
 563     */
 564     /* if DISABLE_READ_GATE_LEVELING is set to 0 */
 565     hEmif->regs->EXT_PHY_CONTROL_2 = hEmif->regs->PHY_STATUS_12;
 566     hEmif->regs->EXT_PHY_CONTROL_2_SHADOW = hEmif->regs->PHY_STATUS_12;
 567     hEmif->regs->EXT_PHY_CONTROL_3 = hEmif->regs->PHY_STATUS_13;
 568     hEmif->regs->EXT_PHY_CONTROL_3_SHADOW = hEmif->regs->PHY_STATUS_13;
 569     hEmif->regs->EXT_PHY_CONTROL_4 = hEmif->regs->PHY_STATUS_14;
 570     hEmif->regs->EXT_PHY_CONTROL_4_SHADOW = hEmif->regs->PHY_STATUS_14;
 571     hEmif->regs->EXT_PHY_CONTROL_5 = hEmif->regs->PHY_STATUS_15;
 572     hEmif->regs->EXT_PHY_CONTROL_5_SHADOW = hEmif->regs->PHY_STATUS_15;
 573     hEmif->regs->EXT_PHY_CONTROL_6 = hEmif->regs->PHY_STATUS_16;
 574     hEmif->regs->EXT_PHY_CONTROL_6_SHADOW = hEmif->regs->PHY_STATUS_16;
 575
 576     /* if DISABLE_READ_LEVELING is set to 0 */
 577     hEmif->regs->EXT_PHY_CONTROL_7 = hEmif->regs->PHY_STATUS_7;
 578     hEmif->regs->EXT_PHY_CONTROL_7_SHADOW = hEmif->regs->PHY_STATUS_7;
 579     hEmif->regs->EXT_PHY_CONTROL_8 = hEmif->regs->PHY_STATUS_8;
 580     hEmif->regs->EXT_PHY_CONTROL_8_SHADOW = hEmif->regs->PHY_STATUS_8;
 581     hEmif->regs->EXT_PHY_CONTROL_9 = hEmif->regs->PHY_STATUS_9;
 582     hEmif->regs->EXT_PHY_CONTROL_9_SHADOW = hEmif->regs->PHY_STATUS_9;
 583     hEmif->regs->EXT_PHY_CONTROL_10 = hEmif->regs->PHY_STATUS_10;
 584     hEmif->regs->EXT_PHY_CONTROL_10_SHADOW = hEmif->regs->PHY_STATUS_10;
 585     hEmif->regs->EXT_PHY_CONTROL_11 = hEmif->regs->PHY_STATUS_11;
 586     hEmif->regs->EXT_PHY_CONTROL_11_SHADOW = hEmif->regs->PHY_STATUS_11;
 587
 588     /* if DISABLE_WRITE_LEVELING is set to 0 */
 589     hEmif->regs->EXT_PHY_CONTROL_12 = hEmif->regs->PHY_STATUS_17;
 590     hEmif->regs->EXT_PHY_CONTROL_12_SHADOW = hEmif->regs->PHY_STATUS_17;
 591     hEmif->regs->EXT_PHY_CONTROL_13 = hEmif->regs->PHY_STATUS_18;
 592     hEmif->regs->EXT_PHY_CONTROL_13_SHADOW = hEmif->regs->PHY_STATUS_18;
 593     hEmif->regs->EXT_PHY_CONTROL_14 = hEmif->regs->PHY_STATUS_19;
 594     hEmif->regs->EXT_PHY_CONTROL_14_SHADOW = hEmif->regs->PHY_STATUS_19;
 595     hEmif->regs->EXT_PHY_CONTROL_15 = hEmif->regs->PHY_STATUS_20;
 596     hEmif->regs->EXT_PHY_CONTROL_15_SHADOW = hEmif->regs->PHY_STATUS_20;
 597     hEmif->regs->EXT_PHY_CONTROL_16 = hEmif->regs->PHY_STATUS_21;
 598     hEmif->regs->EXT_PHY_CONTROL_16_SHADOW = hEmif->regs->PHY_STATUS_21;
 599
 600     /* EMIF_PHY_WR_DQS_SLAVE_RATIO */
 601     hEmif->regs->EXT_PHY_CONTROL_17 = hEmif->regs->PHY_STATUS_22;
 602     hEmif->regs->EXT_PHY_CONTROL_17_SHADOW = hEmif->regs->PHY_STATUS_22;
 603     hEmif->regs->EXT_PHY_CONTROL_18 = hEmif->regs->PHY_STATUS_23;
 604     hEmif->regs->EXT_PHY_CONTROL_18_SHADOW = hEmif->regs->PHY_STATUS_23;
 605     hEmif->regs->EXT_PHY_CONTROL_19 = hEmif->regs->PHY_STATUS_24;
 606     hEmif->regs->EXT_PHY_CONTROL_19_SHADOW = hEmif->regs->PHY_STATUS_24;
 607     hEmif->regs->EXT_PHY_CONTROL_20 = hEmif->regs->PHY_STATUS_25;
 608     hEmif->regs->EXT_PHY_CONTROL_20_SHADOW = hEmif->regs->PHY_STATUS_25;
 609     hEmif->regs->EXT_PHY_CONTROL_21 = hEmif->regs->PHY_STATUS_26;
 610     hEmif->regs->EXT_PHY_CONTROL_21_SHADOW = hEmif->regs->PHY_STATUS_26;
 611
 612     regVal = hEmif->regs->DDR_PHY_CONTROL_1;
 613     regVal = (regVal | 0x0E000000U);
 614     hEmif->regs->DDR_PHY_CONTROL_1 = regVal;
 615
 616     regVal = hEmif->regs->DDR_PHY_CONTROL_1_SHADOW;
 617     regVal = (regVal | 0x0E000000U);
 618     hEmif->regs->DDR_PHY_CONTROL_1_SHADOW = regVal;
 619
 620     hEmif->regs->READ_WRITE_LEVELING_RAMP_CONTROL = 0U;
 621 }