[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / board / src / skAM335x / device / enet_phy.h
1 /**
2 * enet_phy.h
3 */
5 /*
6 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #ifndef _ENETPHY_H
40 #define _ENETPHY_H
42 //#include "cpsw_nimu_eth.h"
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
48 /***************************************************************************
49 **
50 ** M D I O R E G I S T E R A C C E S S M A C R O S
51 **
52 ***************************************************************************/
54 #define MDIO_USERACCESS_DATA (0xFFFF)
55 #define MDIO_USERPHYSEL_LINKSEL (1 << 7)
57 /****************************************************************************/
58 /* */
59 /* P H Y R E G I S T E R D E F I N I T I O N S */
60 /* */
61 /****************************************************************************/
63 /* PHY register offset definitions */
64 #define ENETPHY_BCR (0u)
65 #define ENETPHY_BSR (1u)
66 #define ENETPHY_ID1 (2u)
67 #define ENETPHY_ID2 (3u)
68 #define ENETPHY_AUTONEG_ADV (4u)
69 #define ENETPHY_LINK_PARTNER_ABLTY (5u)
70 #define ENETPHY_1000BT_CONTROL (9u)
71 #define ENETPHY_1000BT_STATUS (0x0A)
73 /* PHY status definitions */
74 #define ENETPHY_ID_SHIFT (16u)
75 #define ENETPHY_SOFTRESET (0x8000)
76 #define ENETPHY_AUTONEG_ENABLE (0x1000u)
77 #define ENETPHY_AUTONEG_RESTART (0x0200u)
78 #define ENETPHY_AUTONEG_COMPLETE (0x0020u)
79 #define ENETPHY_AUTONEG_INCOMPLETE (0x0000u)
80 #define ENETPHY_AUTONEG_STATUS (0x0020u)
81 #define ENETPHY_AUTONEG_ABLE (0x0008u)
82 #define ENETPHY_LPBK_ENABLE (0x4000u)
83 #define ENETPHY_LINK_STATUS (0x0004u)
85 /* PHY ID. The LSB nibble will vary between different phy revisions */
86 #define ENETPHY_ID_REV_MASK (0x0000000Fu)
88 /* Pause operations */
89 #define ENETPHY_PAUSE_NIL (0x0000u)
90 #define ENETPHY_PAUSE_SYM (0x0400u)
91 #define ENETPHY_PAUSE_ASYM (0x0800u)
92 #define ENETPHY_PAUSE_BOTH_SYM_ASYM (0x0C00u)
94 /* 1000 Base-T capabilities */
95 #define ENETPHY_NO_1000BT (0x0000u)
96 #define ENETPHY_1000BT_HD (0x0100u)
97 #define ENETPHY_1000BT_FD (0x0200u)
99 /* 100 Base TX Full Duplex capablity */
100 #define ENETPHY_100BTX_HD (0x0000u)
101 #define ENETPHY_100BTX_FD (0x0100u)
103 /* 100 Base TX capability */
104 #define ENETPHY_NO_100BTX (0x0000u)
105 #define ENETPHY_100BTX (0x0080u)
107 /* 10 BaseT duplex capabilities */
108 #define ENETPHY_10BT_HD (0x0000u)
109 #define ENETPHY_10BT_FD (0x0040u)
111 /* 10 BaseT ability*/
112 #define ENETPHY_NO_10BT (0x0000u)
113 #define ENETPHY_10BT (0x0020u)
115 #define ENETPHY_LINK_PARTNER_1000BT_FD (0x0800u)
116 #define ENETPHY_LINK_PARTNER_1000BT_HD (0x0400u)
118 /* Speed settings for BCR register */
119 #define ENETPHY_SPEED_MASK (0xDFBF)
120 #define ENETPHY_SPEED_10MBPS (0x0000u)
121 #define ENETPHY_SPEED_100MBPS (0x2000u)
122 #define ENETPHY_SPEED_1000MBPS (0x0040)
124 /* Duplex settings for BCR register */
125 #define ENETPHY_FULL_DUPLEX (0x0100)
127 #define ENETPHY_CONTROL_REG 0
128 #define MII_ENETPHY_RESET (1<<15)
129 #define MII_ENETPHY_LOOP (1<<14)
130 #define MII_ENETPHY_100 (1<<13)
131 #define MII_AUTO_NEGOTIATE_EN (1<<12)
132 #define MII_ENETPHY_PDOWN (1<<11)
133 #define MII_ENETPHY_ISOLATE (1<<10)
134 #define MII_RENEGOTIATE (1<<9)
135 #define MII_ENETPHY_FD (1<<8)
136 #define MII_ENETPHY_1000 (1<<6)
138 #define ENETPHY_STATUS_REG 1
139 #define MII_NWAY_COMPLETE (1<<5)
140 #define MII_NWAY_CAPABLE (1<<3)
141 #define MII_ENETPHY_LINKED (1<<2)
143 #define ENETPHY_IDENT_REG 2
144 #define NWAY_ADVERTIZE_REG 4
145 #define NWAY_REMADVERTISE_REG 5
146 #define MII_NWAY_FD100 (1<<8)
147 #define MII_NWAY_HD100 (1<<7)
148 #define MII_NWAY_FD10 (1<<6)
149 #define MII_NWAY_HD10 (1<<5)
150 #define MII_NWAY_SEL (1<<0)
152 #define NWAY_1000BT_ADVERTISE_REG 9
153 #define MII_NWAY_MY_FD1000 (1<<9)
154 #define MII_NWAY_MY_HD1000 (1<<8)
155 #define NWAY_1000BT_REMADVERTISE_REG 10
156 #define MII_NWAY_REM_FD1000 (1<<11)
157 #define MII_NWAY_REM_HD1000 (1<<10)
159 #define ENETPHY_CNTRL_REG 0x0019
161 #define ENETPHY_CONFIG_REG 22
162 #define SYSTEM_CLOCK_ENABLE_125MHZ (1<<4)
163 #define TRANSMIT_CLOCK_ENABLE_1000BASET (1<<5)
164 #define GMII_CLOCKED_BY_GTX_CLK (1<<1)
166 #define ENETPHY_LED_CONTROL_REG 28
168 /* Phy Mode Values */
169 #define NWAY_AUTOMDIX (1u << 16u)
170 #define NWAY_FD1000 (1u<<13u)
171 #define NWAY_HD1000 (1u<<12u)
172 #define NWAY_NOPHY (1u<<10u)
173 #define NWAY_LPBK (1u<<9u)
174 #define NWAY_FD100 (1u<<8u)
175 #define NWAY_HD100 (1u<<7u)
176 #define NWAY_FD10 (1u<<6u)
177 #define NWAY_HD10 (1u<<5u)
178 #define NWAY_AUTO (1u<<0u)
180 #define NWAY_AUTOMDIX_ENABLE (1u<<15)
182 /* Tic() return values */
183 #define _MIIMDIO_MDIXFLIP (1u<<28u)
184 #define _AUTOMDIX_DELAY_MIN 80u /* milli-seconds*/
185 #define _AUTOMDIX_DELAY_MAX 200u /* milli-seconds*/
187 /*-----------------------------------------------------------------------
188 * MDIO Events
189 *
190 * These events are returned as result param by ENETPHY_Tic() to allow the application
191 * (or EMAC) to track MDIO status.
192 *-----------------------------------------------------------------------*/
193 #define MDIO_EVENT_NOCHANGE 0u /* No change from previous status */
194 #define MDIO_EVENT_LINKDOWN 1u /* Link down event */
195 #define MDIO_EVENT_LINKUP 2u /* Link (or re-link) event */
196 #define MDIO_EVENT_PHYERROR 3u /* No PHY connected */
198 /*-----------------------------------------------------------------------
199 * MDIO Link Status Values
200 *
201 * These values indicate current PHY link status.
202 * Codes are constructed as follows
203 * Bit0: 0 for HD, 1 for FullDuplex
204 * Bit[2:1]: 10Mbps- 1, 100Mbps - 2, 1000Mbps - 3
205 *
206 *-----------------------------------------------------------------------*/
207 #define MDIO_LINKSTATUS_NOLINK 0u
208 #define MDIO_LINKSTATUS_HD10 2u
209 #define MDIO_LINKSTATUS_FD10 3u
210 #define MDIO_LINKSTATUS_HD100 4u
211 #define MDIO_LINKSTATUS_FD100 5u
212 #define MDIO_LINKSTATUS_FD1000 7u
214 typedef void *ENETPHY_Handle;
216 typedef struct _cpsw_phy_device
217 {
218 Uint32 miibase;
219 Uint32 inst;
220 Uint32 PhyState;
221 Uint32 MdixMask;
222 Uint32 PhyMask;
223 Uint32 MLinkMask;
224 Uint32 PhyMode;
225 Uint32 SPEED_1000; /* set to 1 for gig capable phys */
226 } ENETPHY_DEVICE;
228 /*Version Information */
229 void ENETPHY_GetVer(Uint32 miiBase, Uint32 *ModID, Uint32 *RevMaj, Uint32 *RevMin);
231 /*Called once at the begining of time */
232 int ENETPHY_GetPhyDevSize(void); /*Called first to get size of storage needed!*/
234 int ENETPHY_Init(ENETPHY_Handle hPhyDev, Uint32 miibase, Uint32 inst, Uint32 PhyMask,
235 Uint32 MLinkMask, Uint32 MdixMask, Uint32 PhyAddr, Uint32 ResetBit, Uint32 MdioBusFreq,
236 Uint32 MdioClockFreq,int verbose);
238 /*Called every 100 milli Seconds, returns TRUE if there has been a mode change */
239 int ENETPHY_Tic(ENETPHY_Handle hPhyDev, Uint32* mdioStatus);
241 /*Called to set Phy mode */
242 void ENETPHY_SetPhyMode(ENETPHY_Handle hPhyDev,Uint32 PhyMode);
244 /*Called to Get Phy mode */
245 Uint32 ENETPHY_GetPhyMode(ENETPHY_Handle hPhyDev);
247 /*Calls to retreive info after a mode change! */
248 int ENETPHY_GetDuplex(ENETPHY_Handle hPhyDev);
249 int ENETPHY_GetSpeed(ENETPHY_Handle hPhyDev);
250 int ENETPHY_GetPhyNum(ENETPHY_Handle hPhyDev);
251 int ENETPHY_GetLinked(ENETPHY_Handle hPhyDev);
252 void ENETPHY_LinkChange(ENETPHY_Handle hPhyDev);
253 int ENETPHY_GetLoopback(ENETPHY_Handle hPhyDev);
255 /* Shut Down */
256 void ENETPHY_Close(ENETPHY_Handle hPhyDev, int Full);
258 /* Expert Use Functions (exported) */
259 Uint32 _ENETPHY_UserAccessRead (ENETPHY_Handle hPhyDev, Uint32 regadr, Uint32 phyadr, Uint32 *data);
260 void _ENETPHY_UserAccessWrite(ENETPHY_Handle hPhyDev, Uint32 regadr, Uint32 phyadr, Uint32 data);
262 #ifdef __cplusplus
263 }
264 #endif
266 #endif /*_CPSW_MIIMDIO_H*/