[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / boot / sbl / soc / am57xx / sbl_prcm.c
1 /**
2 * \file sbl_prcm.c
3 *
4 * \brief This file contains PRCM functions used in SBL to enable clocks
5 * to the slave cores.
6 *
7 */
9 /*
10 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the
22 * distribution.
23 *
24 * Neither the name of Texas Instruments Incorporated nor the names of
25 * its contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
42 /* TI RTOS header files */
43 #include <stdint.h>
44 #include <ti/csl/cslr_device.h>
45 #include <ti/csl/hw_types.h>
46 #include <ti/drv/uart/UART_stdio.h>
48 #include "sbl_prcm.h"
50 void SBL_PRCMModuleEnable(uint32_t domainOffset,
51 uint32_t clkCtrlReg,
52 uint32_t clkStCtrlReg,
53 uint32_t clkActMask)
54 {
55 /* Enable the module */
56 HW_WR_REG32(domainOffset + clkCtrlReg, PRCM_MODULEMODE_AUTO);
57 /* Check for module enable status */
58 while(PRCM_MODULEMODE_AUTO !=
59 (HW_RD_REG32(domainOffset + clkCtrlReg) & PRCM_MODULEMODE_MASK));
61 /* Check clock activity - ungated */
62 while(clkActMask != (HW_RD_REG32(domainOffset + clkStCtrlReg) & clkActMask));
63 }
65 void SBL_PRCMModuleDisable(uint32_t domainOffset,
66 uint32_t clkCtrlReg,
67 uint32_t clkStCtrlReg)
68 {
69 /* Enable the module */
70 HW_WR_REG32(domainOffset + clkCtrlReg, PRCM_MODULEMODE_DISABLE);
72 /* Check for module enable status */
73 while(PRCM_MODULEMODE_DISABLE !=
74 (HW_RD_REG32(domainOffset + clkCtrlReg) & PRCM_MODULEMODE_MASK));
75 }
77 void SBL_PRCMSetClkOperMode(uint32_t domainOffset,
78 uint32_t clkStCtrlReg,
79 uint32_t clkMode)
80 {
81 /* Enable the module */
82 HW_WR_FIELD32(domainOffset + clkStCtrlReg, CM_DSP1_CLKSTCTRL_CLKTRCTRL, clkMode);
84 while(clkMode != HW_RD_FIELD32(domainOffset + clkStCtrlReg,
85 CM_DSP1_CLKSTCTRL_CLKTRCTRL));
86 }
88 void SBL_ResetAssert(uint32_t ctrlRegAddr, uint32_t ctrlregShift)
89 {
90 uint32_t resetCtrlMask;
92 resetCtrlMask = (uint32_t) 1U << ctrlregShift;
93 HW_WR_FIELD32_RAW(ctrlRegAddr, resetCtrlMask, ctrlregShift, 0x1U);
94 }
96 void SBL_ResetRelease(uint32_t ctrlRegAddr,
97 uint32_t ctrlregShift,
98 uint32_t stsRegAddr,
99 uint32_t stsRegShift)
100 {
101 uint32_t rstStsMask, resetCtrlMask;
103 resetCtrlMask = (uint32_t) 1U << ctrlregShift;
104 HW_WR_FIELD32_RAW(ctrlRegAddr, resetCtrlMask, ctrlregShift, 0x0U);
106 rstStsMask = (uint32_t) 1U << stsRegShift;
107 while(0x1U != ((uint32_t) HW_RD_FIELD32_RAW(stsRegAddr, rstStsMask,
108 stsRegShift)));
109 }
111 void SBL_ResetGetStatus(uint32_t stsRegAddr,
112 uint32_t stsRegShift,
113 uint32_t *rStsMask)
114 {
115 uint32_t rstStsMask;
117 rstStsMask = (uint32_t) 1U << stsRegShift;
118 *rStsMask = (uint32_t) HW_RD_FIELD32_RAW(stsRegAddr, rstStsMask,
119 stsRegShift);
120 }
122 void SBL_ResetClearStatus(uint32_t stsRegAddr,
123 uint32_t stsRegShift)
124 {
125 uint32_t rstStMask;
127 rstStMask = (uint32_t) 1U << stsRegShift;
128 HW_WR_FIELD32_RAW(stsRegAddr, rstStMask, stsRegShift, (uint32_t) 0x1U);
129 }