[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / csl / arch / a15 / hw_mpu_wugen.h
1 /*
2 * Copyright (C) 2008-2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 * \file hw_mpu_wugen.h
36 *
37 * \brief register-level header file for MPU
38 *
39 **/
41 #ifndef HW_MPU_WUGEN_H_
42 #define HW_MPU_WUGEN_H_
44 #ifdef __cplusplus
45 extern "C"
46 {
47 #endif
49 /****************************************************************************************************
50 * Register Definitions
51 ****************************************************************************************************/
52 #define MPU_WKG_CONTROL_0 (0x0U)
53 #define MPU_WKG_ENB_A_0 (uint32_t)(0x10U)
54 #define MPU_WKG_ENB_B_0 (0x14U)
55 #define MPU_WKG_ENB_C_0 (0x18U)
56 #define MPU_WKG_ENB_D_0 (0x1cU)
57 #define MPU_WKG_ENB_E_0 (0x20U)
58 #define MPU_WKG_CONTROL_1 (0x400U)
59 #define MPU_WKG_ENB_A_1 (uint32_t)(0x410U)
60 #define MPU_WKG_ENB_B_1 (0x414U)
61 #define MPU_WKG_ENB_C_1 (0x418U)
62 #define MPU_WKG_ENB_D_1 (0x41cU)
63 #define MPU_WKG_ENB_E_1 (0x420U)
64 #define MPU_AUX_CORE_BOOT_0 (0x800U)
65 #define MPU_AUX_CORE_BOOT_1 (0x804U)
66 #define MPU_STM_HWEVENTS_INV (0x808U)
67 #define MPU_AMBA_IF_MODE (0x80cU)
68 #define MPU_TIMESTAMPCYCLELO (0xc08U)
69 #define MPU_TIMESTAMPCYCLEHI (0xc0cU)
71 /****************************************************************************************************
72 * Field Definition Macros
73 ****************************************************************************************************/
75 #define MPU_WKG_CONTROL_0_RESERVED_SHIFT (0U)
76 #define MPU_WKG_CONTROL_0_RESERVED_MASK (0x000000ffU)
78 #define MPU_WKG_CONTROL_0_STANDBYWFI_SHIFT (8U)
79 #define MPU_WKG_CONTROL_0_STANDBYWFI_MASK (0x00000100U)
81 #define MPU_WKG_CONTROL_0_STANDBYWFE_SHIFT (9U)
82 #define MPU_WKG_CONTROL_0_STANDBYWFE_MASK (0x00000200U)
84 #define MPU_WKG_CONTROL_0_EVENTO_SHIFT (10U)
85 #define MPU_WKG_CONTROL_0_EVENTO_MASK (0x00000400U)
87 #define MPU_WKG_CONTROL_0_MPU_COLD_RESET_SHIFT (13U)
88 #define MPU_WKG_CONTROL_0_MPU_COLD_RESET_MASK (0x00002000U)
90 #define MPU_WKG_CONTROL_0_MPU_WARM_RESET_SHIFT (14U)
91 #define MPU_WKG_CONTROL_0_MPU_WARM_RESET_MASK (0x00004000U)
93 #define MPU_WKG_CONTROL_0_RESERVED3_SHIFT (16U)
94 #define MPU_WKG_CONTROL_0_RESERVED3_MASK (0xffff0000U)
96 #define MPU_WKG_CONTROL_0_RESERVED2_SHIFT (11U)
97 #define MPU_WKG_CONTROL_0_RESERVED2_MASK (0x00001800U)
99 #define MPU_WKG_CONTROL_0_DOMAINRESET_SHIFT (15U)
100 #define MPU_WKG_CONTROL_0_DOMAINRESET_MASK (0x00008000U)
102 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR0_SHIFT (0U)
103 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR0_MASK (0x00000001U)
105 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR1_SHIFT (1U)
106 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR1_MASK (0x00000002U)
108 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR2_SHIFT (2U)
109 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR2_MASK (0x00000004U)
111 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR3_SHIFT (3U)
112 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR3_MASK (0x00000008U)
114 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR4_SHIFT (4U)
115 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR4_MASK (0x00000010U)
117 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR5_SHIFT (5U)
118 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR5_MASK (0x00000020U)
120 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR6_SHIFT (6U)
121 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR6_MASK (0x00000040U)
123 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR7_SHIFT (7U)
124 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR7_MASK (0x00000080U)
126 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR8_SHIFT (8U)
127 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR8_MASK (0x00000100U)
129 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR9_SHIFT (9U)
130 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR9_MASK (0x00000200U)
132 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR10_SHIFT (10U)
133 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR10_MASK (0x00000400U)
135 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR11_SHIFT (11U)
136 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR11_MASK (0x00000800U)
138 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR12_SHIFT (12U)
139 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR12_MASK (0x00001000U)
141 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR13_SHIFT (13U)
142 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR13_MASK (0x00002000U)
144 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR14_SHIFT (14U)
145 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR14_MASK (0x00004000U)
147 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR15_SHIFT (15U)
148 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR15_MASK (0x00008000U)
150 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR16_SHIFT (16U)
151 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR16_MASK (0x00010000U)
153 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR17_SHIFT (17U)
154 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR17_MASK (0x00020000U)
156 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR18_SHIFT (18U)
157 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR18_MASK (0x00040000U)
159 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR19_SHIFT (19U)
160 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR19_MASK (0x00080000U)
162 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR20_SHIFT (20U)
163 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR20_MASK (0x00100000U)
165 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR21_SHIFT (21U)
166 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR21_MASK (0x00200000U)
168 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR22_SHIFT (22U)
169 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR22_MASK (0x00400000U)
171 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR23_SHIFT (23U)
172 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR23_MASK (0x00800000U)
174 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR24_SHIFT (24U)
175 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR24_MASK (0x01000000U)
177 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR25_SHIFT (25U)
178 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR25_MASK (0x02000000U)
180 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR26_SHIFT (26U)
181 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR26_MASK (0x04000000U)
183 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR27_SHIFT (27U)
184 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR27_MASK (0x08000000U)
186 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR28_SHIFT (28U)
187 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR28_MASK (0x10000000U)
189 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR29_SHIFT (29U)
190 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR29_MASK (0x20000000U)
192 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR30_SHIFT (30U)
193 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR30_MASK (0x40000000U)
195 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR31_SHIFT (31U)
196 #define MPU_WKG_ENB_A_0_WKG_ENB_FOR_INTR31_MASK (0x80000000U)
198 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR32_SHIFT (0U)
199 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR32_MASK (0x00000001U)
201 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR33_SHIFT (1U)
202 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR33_MASK (0x00000002U)
204 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR34_SHIFT (2U)
205 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR34_MASK (0x00000004U)
207 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR35_SHIFT (3U)
208 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR35_MASK (0x00000008U)
210 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR36_SHIFT (4U)
211 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR36_MASK (0x00000010U)
213 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR37_SHIFT (5U)
214 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR37_MASK (0x00000020U)
216 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR38_SHIFT (6U)
217 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR38_MASK (0x00000040U)
219 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR39_SHIFT (7U)
220 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR39_MASK (0x00000080U)
222 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR40_SHIFT (8U)
223 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR40_MASK (0x00000100U)
225 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR41_SHIFT (9U)
226 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR41_MASK (0x00000200U)
228 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR42_SHIFT (10U)
229 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR42_MASK (0x00000400U)
231 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR43_SHIFT (11U)
232 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR43_MASK (0x00000800U)
234 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR44_SHIFT (12U)
235 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR44_MASK (0x00001000U)
237 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR45_SHIFT (13U)
238 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR45_MASK (0x00002000U)
240 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR46_SHIFT (14U)
241 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR46_MASK (0x00004000U)
243 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR47_SHIFT (15U)
244 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR47_MASK (0x00008000U)
246 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR48_SHIFT (16U)
247 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR48_MASK (0x00010000U)
249 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR49_SHIFT (17U)
250 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR49_MASK (0x00020000U)
252 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR50_SHIFT (18U)
253 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR50_MASK (0x00040000U)
255 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR51_SHIFT (19U)
256 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR51_MASK (0x00080000U)
258 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR52_SHIFT (20U)
259 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR52_MASK (0x00100000U)
261 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR53_SHIFT (21U)
262 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR53_MASK (0x00200000U)
264 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR54_SHIFT (22U)
265 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR54_MASK (0x00400000U)
267 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR55_SHIFT (23U)
268 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR55_MASK (0x00800000U)
270 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR56_SHIFT (24U)
271 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR56_MASK (0x01000000U)
273 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR57_SHIFT (25U)
274 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR57_MASK (0x02000000U)
276 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR58_SHIFT (26U)
277 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR58_MASK (0x04000000U)
279 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR59_SHIFT (27U)
280 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR59_MASK (0x08000000U)
282 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR60_SHIFT (28U)
283 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR60_MASK (0x10000000U)
285 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR61_SHIFT (29U)
286 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR61_MASK (0x20000000U)
288 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR62_SHIFT (30U)
289 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR62_MASK (0x40000000U)
291 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR63_SHIFT (31U)
292 #define MPU_WKG_ENB_B_0_WKG_ENB_FOR_INTR63_MASK (0x80000000U)
294 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR64_SHIFT (0U)
295 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR64_MASK (0x00000001U)
297 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR65_SHIFT (1U)
298 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR65_MASK (0x00000002U)
300 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR66_SHIFT (2U)
301 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR66_MASK (0x00000004U)
303 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR67_SHIFT (3U)
304 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR67_MASK (0x00000008U)
306 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR68_SHIFT (4U)
307 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR68_MASK (0x00000010U)
309 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR69_SHIFT (5U)
310 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR69_MASK (0x00000020U)
312 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR70_SHIFT (6U)
313 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR70_MASK (0x00000040U)
315 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR71_SHIFT (7U)
316 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR71_MASK (0x00000080U)
318 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR72_SHIFT (8U)
319 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR72_MASK (0x00000100U)
321 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR73_SHIFT (9U)
322 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR73_MASK (0x00000200U)
324 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR74_SHIFT (10U)
325 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR74_MASK (0x00000400U)
327 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR75_SHIFT (11U)
328 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR75_MASK (0x00000800U)
330 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR76_SHIFT (12U)
331 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR76_MASK (0x00001000U)
333 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR77_SHIFT (13U)
334 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR77_MASK (0x00002000U)
336 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR78_SHIFT (14U)
337 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR78_MASK (0x00004000U)
339 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR79_SHIFT (15U)
340 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR79_MASK (0x00008000U)
342 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR80_SHIFT (16U)
343 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR80_MASK (0x00010000U)
345 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR81_SHIFT (17U)
346 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR81_MASK (0x00020000U)
348 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR82_SHIFT (18U)
349 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR82_MASK (0x00040000U)
351 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR83_SHIFT (19U)
352 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR83_MASK (0x00080000U)
354 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR84_SHIFT (20U)
355 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR84_MASK (0x00100000U)
357 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR85_SHIFT (21U)
358 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR85_MASK (0x00200000U)
360 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR86_SHIFT (22U)
361 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR86_MASK (0x00400000U)
363 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR87_SHIFT (23U)
364 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR87_MASK (0x00800000U)
366 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR88_SHIFT (24U)
367 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR88_MASK (0x01000000U)
369 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR89_SHIFT (25U)
370 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR89_MASK (0x02000000U)
372 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR90_SHIFT (26U)
373 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR90_MASK (0x04000000U)
375 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR91_SHIFT (27U)
376 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR91_MASK (0x08000000U)
378 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR92_SHIFT (28U)
379 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR92_MASK (0x10000000U)
381 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR93_SHIFT (29U)
382 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR93_MASK (0x20000000U)
384 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR94_SHIFT (30U)
385 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR94_MASK (0x40000000U)
387 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR95_SHIFT (31U)
388 #define MPU_WKG_ENB_C_0_WKG_ENB_FOR_INTR95_MASK (0x80000000U)
390 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR96_SHIFT (0U)
391 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR96_MASK (0x00000001U)
393 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR97_SHIFT (1U)
394 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR97_MASK (0x00000002U)
396 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR98_SHIFT (2U)
397 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR98_MASK (0x00000004U)
399 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR99_SHIFT (3U)
400 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR99_MASK (0x00000008U)
402 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR100_SHIFT (4U)
403 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR100_MASK (0x00000010U)
405 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR101_SHIFT (5U)
406 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR101_MASK (0x00000020U)
408 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR102_SHIFT (6U)
409 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR102_MASK (0x00000040U)
411 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR103_SHIFT (7U)
412 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR103_MASK (0x00000080U)
414 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR104_SHIFT (8U)
415 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR104_MASK (0x00000100U)
417 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR105_SHIFT (9U)
418 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR105_MASK (0x00000200U)
420 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR106_SHIFT (10U)
421 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR106_MASK (0x00000400U)
423 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR107_SHIFT (11U)
424 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR107_MASK (0x00000800U)
426 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR108_SHIFT (12U)
427 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR108_MASK (0x00001000U)
429 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR109_SHIFT (13U)
430 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR109_MASK (0x00002000U)
432 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR110_SHIFT (14U)
433 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR110_MASK (0x00004000U)
435 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR111_SHIFT (15U)
436 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR111_MASK (0x00008000U)
438 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR112_SHIFT (16U)
439 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR112_MASK (0x00010000U)
441 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR113_SHIFT (17U)
442 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR113_MASK (0x00020000U)
444 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR114_SHIFT (18U)
445 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR114_MASK (0x00040000U)
447 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR115_SHIFT (19U)
448 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR115_MASK (0x00080000U)
450 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR116_SHIFT (20U)
451 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR116_MASK (0x00100000U)
453 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR117_SHIFT (21U)
454 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR117_MASK (0x00200000U)
456 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR118_SHIFT (22U)
457 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR118_MASK (0x00400000U)
459 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR119_SHIFT (23U)
460 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR119_MASK (0x00800000U)
462 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR120_SHIFT (24U)
463 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR120_MASK (0x01000000U)
465 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR121_SHIFT (25U)
466 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR121_MASK (0x02000000U)
468 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR122_SHIFT (26U)
469 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR122_MASK (0x04000000U)
471 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR123_SHIFT (27U)
472 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR123_MASK (0x08000000U)
474 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR124_SHIFT (28U)
475 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR124_MASK (0x10000000U)
477 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR125_SHIFT (29U)
478 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR125_MASK (0x20000000U)
480 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR126_SHIFT (30U)
481 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR126_MASK (0x40000000U)
483 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR127_SHIFT (31U)
484 #define MPU_WKG_ENB_D_0_WKG_ENB_FOR_INTR127_MASK (0x80000000U)
486 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR128_SHIFT (0U)
487 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR128_MASK (0x00000001U)
489 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR129_SHIFT (1U)
490 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR129_MASK (0x00000002U)
492 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR130_SHIFT (2U)
493 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR130_MASK (0x00000004U)
495 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR131_SHIFT (3U)
496 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR131_MASK (0x00000008U)
498 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR132_SHIFT (4U)
499 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR132_MASK (0x00000010U)
501 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR133_SHIFT (5U)
502 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR133_MASK (0x00000020U)
504 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR134_SHIFT (6U)
505 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR134_MASK (0x00000040U)
507 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR135_SHIFT (7U)
508 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR135_MASK (0x00000080U)
510 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR136_SHIFT (8U)
511 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR136_MASK (0x00000100U)
513 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR137_SHIFT (9U)
514 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR137_MASK (0x00000200U)
516 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR138_SHIFT (10U)
517 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR138_MASK (0x00000400U)
519 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR139_SHIFT (11U)
520 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR139_MASK (0x00000800U)
522 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR140_SHIFT (12U)
523 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR140_MASK (0x00001000U)
525 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR141_SHIFT (13U)
526 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR141_MASK (0x00002000U)
528 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR142_SHIFT (14U)
529 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR142_MASK (0x00004000U)
531 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR143_SHIFT (15U)
532 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR143_MASK (0x00008000U)
534 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR144_SHIFT (16U)
535 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR144_MASK (0x00010000U)
537 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR145_SHIFT (17U)
538 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR145_MASK (0x00020000U)
540 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR146_SHIFT (18U)
541 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR146_MASK (0x00040000U)
543 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR147_SHIFT (19U)
544 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR147_MASK (0x00080000U)
546 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR148_SHIFT (20U)
547 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR148_MASK (0x00100000U)
549 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR149_SHIFT (21U)
550 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR149_MASK (0x00200000U)
552 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR150_SHIFT (22U)
553 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR150_MASK (0x00400000U)
555 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR151_SHIFT (23U)
556 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR151_MASK (0x00800000U)
558 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR152_SHIFT (24U)
559 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR152_MASK (0x01000000U)
561 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR153_SHIFT (25U)
562 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR153_MASK (0x02000000U)
564 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR154_SHIFT (26U)
565 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR154_MASK (0x04000000U)
567 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR155_SHIFT (27U)
568 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR155_MASK (0x08000000U)
570 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR156_SHIFT (28U)
571 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR156_MASK (0x10000000U)
573 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR157_SHIFT (29U)
574 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR157_MASK (0x20000000U)
576 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR158_SHIFT (30U)
577 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR158_MASK (0x40000000U)
579 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR159_SHIFT (31U)
580 #define MPU_WKG_ENB_E_0_WKG_ENB_FOR_INTR159_MASK (0x80000000U)
582 #define MPU_WKG_CONTROL_1_RESERVED_SHIFT (0U)
583 #define MPU_WKG_CONTROL_1_RESERVED_MASK (0x000000ffU)
585 #define MPU_WKG_CONTROL_1_STANDBYWFI_SHIFT (8U)
586 #define MPU_WKG_CONTROL_1_STANDBYWFI_MASK (0x00000100U)
588 #define MPU_WKG_CONTROL_1_STANDBYWFE_SHIFT (9U)
589 #define MPU_WKG_CONTROL_1_STANDBYWFE_MASK (0x00000200U)
591 #define MPU_WKG_CONTROL_1_EVENTO_SHIFT (10U)
592 #define MPU_WKG_CONTROL_1_EVENTO_MASK (0x00000400U)
594 #define MPU_WKG_CONTROL_1_MPU_COLD_RESET_SHIFT (13U)
595 #define MPU_WKG_CONTROL_1_MPU_COLD_RESET_MASK (0x00002000U)
597 #define MPU_WKG_CONTROL_1_MPU_WARM_RESET_SHIFT (14U)
598 #define MPU_WKG_CONTROL_1_MPU_WARM_RESET_MASK (0x00004000U)
600 #define MPU_WKG_CONTROL_1_RESERVED3_SHIFT (16U)
601 #define MPU_WKG_CONTROL_1_RESERVED3_MASK (0xffff0000U)
603 #define MPU_WKG_CONTROL_1_RESERVED2_SHIFT (11U)
604 #define MPU_WKG_CONTROL_1_RESERVED2_MASK (0x00001800U)
606 #define MPU_WKG_CONTROL_1_DOMAINRESET_SHIFT (15U)
607 #define MPU_WKG_CONTROL_1_DOMAINRESET_MASK (0x00008000U)
609 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR0_SHIFT (0U)
610 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR0_MASK (0x00000001U)
612 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR1_SHIFT (1U)
613 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR1_MASK (0x00000002U)
615 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR2_SHIFT (2U)
616 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR2_MASK (0x00000004U)
618 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR3_SHIFT (3U)
619 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR3_MASK (0x00000008U)
621 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR4_SHIFT (4U)
622 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR4_MASK (0x00000010U)
624 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR5_SHIFT (5U)
625 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR5_MASK (0x00000020U)
627 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR6_SHIFT (6U)
628 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR6_MASK (0x00000040U)
630 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR7_SHIFT (7U)
631 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR7_MASK (0x00000080U)
633 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR8_SHIFT (8U)
634 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR8_MASK (0x00000100U)
636 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR9_SHIFT (9U)
637 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR9_MASK (0x00000200U)
639 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR10_SHIFT (10U)
640 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR10_MASK (0x00000400U)
642 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR11_SHIFT (11U)
643 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR11_MASK (0x00000800U)
645 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR12_SHIFT (12U)
646 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR12_MASK (0x00001000U)
648 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR13_SHIFT (13U)
649 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR13_MASK (0x00002000U)
651 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR14_SHIFT (14U)
652 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR14_MASK (0x00004000U)
654 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR15_SHIFT (15U)
655 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR15_MASK (0x00008000U)
657 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR16_SHIFT (16U)
658 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR16_MASK (0x00010000U)
660 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR17_SHIFT (17U)
661 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR17_MASK (0x00020000U)
663 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR18_SHIFT (18U)
664 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR18_MASK (0x00040000U)
666 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR19_SHIFT (19U)
667 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR19_MASK (0x00080000U)
669 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR20_SHIFT (20U)
670 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR20_MASK (0x00100000U)
672 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR21_SHIFT (21U)
673 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR21_MASK (0x00200000U)
675 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR22_SHIFT (22U)
676 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR22_MASK (0x00400000U)
678 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR23_SHIFT (23U)
679 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR23_MASK (0x00800000U)
681 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR24_SHIFT (24U)
682 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR24_MASK (0x01000000U)
684 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR25_SHIFT (25U)
685 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR25_MASK (0x02000000U)
687 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR26_SHIFT (26U)
688 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR26_MASK (0x04000000U)
690 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR27_SHIFT (27U)
691 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR27_MASK (0x08000000U)
693 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR28_SHIFT (28U)
694 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR28_MASK (0x10000000U)
696 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR29_SHIFT (29U)
697 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR29_MASK (0x20000000U)
699 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR30_SHIFT (30U)
700 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR30_MASK (0x40000000U)
702 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR31_SHIFT (31U)
703 #define MPU_WKG_ENB_A_1_WKG_ENB_FOR_INTR31_MASK (0x80000000U)
705 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR32_SHIFT (0U)
706 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR32_MASK (0x00000001U)
708 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR33_SHIFT (1U)
709 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR33_MASK (0x00000002U)
711 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR34_SHIFT (2U)
712 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR34_MASK (0x00000004U)
714 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR35_SHIFT (3U)
715 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR35_MASK (0x00000008U)
717 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR36_SHIFT (4U)
718 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR36_MASK (0x00000010U)
720 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR37_SHIFT (5U)
721 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR37_MASK (0x00000020U)
723 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR38_SHIFT (6U)
724 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR38_MASK (0x00000040U)
726 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR39_SHIFT (7U)
727 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR39_MASK (0x00000080U)
729 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR40_SHIFT (8U)
730 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR40_MASK (0x00000100U)
732 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR41_SHIFT (9U)
733 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR41_MASK (0x00000200U)
735 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR42_SHIFT (10U)
736 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR42_MASK (0x00000400U)
738 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR43_SHIFT (11U)
739 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR43_MASK (0x00000800U)
741 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR44_SHIFT (12U)
742 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR44_MASK (0x00001000U)
744 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR45_SHIFT (13U)
745 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR45_MASK (0x00002000U)
747 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR46_SHIFT (14U)
748 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR46_MASK (0x00004000U)
750 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR47_SHIFT (15U)
751 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR47_MASK (0x00008000U)
753 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR48_SHIFT (16U)
754 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR48_MASK (0x00010000U)
756 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR49_SHIFT (17U)
757 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR49_MASK (0x00020000U)
759 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR50_SHIFT (18U)
760 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR50_MASK (0x00040000U)
762 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR51_SHIFT (19U)
763 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR51_MASK (0x00080000U)
765 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR52_SHIFT (20U)
766 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR52_MASK (0x00100000U)
768 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR53_SHIFT (21U)
769 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR53_MASK (0x00200000U)
771 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR54_SHIFT (22U)
772 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR54_MASK (0x00400000U)
774 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR55_SHIFT (23U)
775 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR55_MASK (0x00800000U)
777 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR56_SHIFT (24U)
778 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR56_MASK (0x01000000U)
780 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR57_SHIFT (25U)
781 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR57_MASK (0x02000000U)
783 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR58_SHIFT (26U)
784 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR58_MASK (0x04000000U)
786 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR59_SHIFT (27U)
787 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR59_MASK (0x08000000U)
789 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR60_SHIFT (28U)
790 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR60_MASK (0x10000000U)
792 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR61_SHIFT (29U)
793 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR61_MASK (0x20000000U)
795 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR62_SHIFT (30U)
796 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR62_MASK (0x40000000U)
798 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR63_SHIFT (31U)
799 #define MPU_WKG_ENB_B_1_WKG_ENB_FOR_INTR63_MASK (0x80000000U)
801 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR64_SHIFT (0U)
802 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR64_MASK (0x00000001U)
804 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR65_SHIFT (1U)
805 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR65_MASK (0x00000002U)
807 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR66_SHIFT (2U)
808 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR66_MASK (0x00000004U)
810 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR67_SHIFT (3U)
811 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR67_MASK (0x00000008U)
813 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR68_SHIFT (4U)
814 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR68_MASK (0x00000010U)
816 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR69_SHIFT (5U)
817 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR69_MASK (0x00000020U)
819 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR70_SHIFT (6U)
820 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR70_MASK (0x00000040U)
822 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR71_SHIFT (7U)
823 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR71_MASK (0x00000080U)
825 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR72_SHIFT (8U)
826 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR72_MASK (0x00000100U)
828 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR73_SHIFT (9U)
829 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR73_MASK (0x00000200U)
831 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR74_SHIFT (10U)
832 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR74_MASK (0x00000400U)
834 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR75_SHIFT (11U)
835 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR75_MASK (0x00000800U)
837 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR76_SHIFT (12U)
838 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR76_MASK (0x00001000U)
840 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR77_SHIFT (13U)
841 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR77_MASK (0x00002000U)
843 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR78_SHIFT (14U)
844 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR78_MASK (0x00004000U)
846 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR79_SHIFT (15U)
847 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR79_MASK (0x00008000U)
849 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR80_SHIFT (16U)
850 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR80_MASK (0x00010000U)
852 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR81_SHIFT (17U)
853 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR81_MASK (0x00020000U)
855 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR82_SHIFT (18U)
856 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR82_MASK (0x00040000U)
858 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR83_SHIFT (19U)
859 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR83_MASK (0x00080000U)
861 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR84_SHIFT (20U)
862 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR84_MASK (0x00100000U)
864 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR85_SHIFT (21U)
865 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR85_MASK (0x00200000U)
867 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR86_SHIFT (22U)
868 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR86_MASK (0x00400000U)
870 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR87_SHIFT (23U)
871 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR87_MASK (0x00800000U)
873 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR88_SHIFT (24U)
874 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR88_MASK (0x01000000U)
876 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR89_SHIFT (25U)
877 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR89_MASK (0x02000000U)
879 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR90_SHIFT (26U)
880 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR90_MASK (0x04000000U)
882 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR91_SHIFT (27U)
883 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR91_MASK (0x08000000U)
885 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR92_SHIFT (28U)
886 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR92_MASK (0x10000000U)
888 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR93_SHIFT (29U)
889 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR93_MASK (0x20000000U)
891 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR94_SHIFT (30U)
892 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR94_MASK (0x40000000U)
894 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR95_SHIFT (31U)
895 #define MPU_WKG_ENB_C_1_WKG_ENB_FOR_INTR95_MASK (0x80000000U)
897 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR96_SHIFT (0U)
898 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR96_MASK (0x00000001U)
900 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR97_SHIFT (1U)
901 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR97_MASK (0x00000002U)
903 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR98_SHIFT (2U)
904 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR98_MASK (0x00000004U)
906 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR99_SHIFT (3U)
907 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR99_MASK (0x00000008U)
909 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR100_SHIFT (4U)
910 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR100_MASK (0x00000010U)
912 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR101_SHIFT (5U)
913 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR101_MASK (0x00000020U)
915 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR102_SHIFT (6U)
916 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR102_MASK (0x00000040U)
918 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR103_SHIFT (7U)
919 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR103_MASK (0x00000080U)
921 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR104_SHIFT (8U)
922 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR104_MASK (0x00000100U)
924 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR105_SHIFT (9U)
925 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR105_MASK (0x00000200U)
927 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR106_SHIFT (10U)
928 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR106_MASK (0x00000400U)
930 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR107_SHIFT (11U)
931 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR107_MASK (0x00000800U)
933 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR108_SHIFT (12U)
934 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR108_MASK (0x00001000U)
936 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR109_SHIFT (13U)
937 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR109_MASK (0x00002000U)
939 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR110_SHIFT (14U)
940 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR110_MASK (0x00004000U)
942 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR111_SHIFT (15U)
943 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR111_MASK (0x00008000U)
945 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR112_SHIFT (16U)
946 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR112_MASK (0x00010000U)
948 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR113_SHIFT (17U)
949 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR113_MASK (0x00020000U)
951 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR114_SHIFT (18U)
952 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR114_MASK (0x00040000U)
954 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR115_SHIFT (19U)
955 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR115_MASK (0x00080000U)
957 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR116_SHIFT (20U)
958 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR116_MASK (0x00100000U)
960 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR117_SHIFT (21U)
961 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR117_MASK (0x00200000U)
963 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR118_SHIFT (22U)
964 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR118_MASK (0x00400000U)
966 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR119_SHIFT (23U)
967 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR119_MASK (0x00800000U)
969 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR120_SHIFT (24U)
970 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR120_MASK (0x01000000U)
972 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR121_SHIFT (25U)
973 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR121_MASK (0x02000000U)
975 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR122_SHIFT (26U)
976 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR122_MASK (0x04000000U)
978 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR123_SHIFT (27U)
979 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR123_MASK (0x08000000U)
981 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR124_SHIFT (28U)
982 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR124_MASK (0x10000000U)
984 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR125_SHIFT (29U)
985 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR125_MASK (0x20000000U)
987 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR126_SHIFT (30U)
988 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR126_MASK (0x40000000U)
990 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR127_SHIFT (31U)
991 #define MPU_WKG_ENB_D_1_WKG_ENB_FOR_INTR127_MASK (0x80000000U)
993 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR128_SHIFT (0U)
994 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR128_MASK (0x00000001U)
996 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR129_SHIFT (1U)
997 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR129_MASK (0x00000002U)
999 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR130_SHIFT (2U)
1000 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR130_MASK (0x00000004U)
1002 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR131_SHIFT (3U)
1003 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR131_MASK (0x00000008U)
1005 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR132_SHIFT (4U)
1006 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR132_MASK (0x00000010U)
1008 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR133_SHIFT (5U)
1009 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR133_MASK (0x00000020U)
1011 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR134_SHIFT (6U)
1012 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR134_MASK (0x00000040U)
1014 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR135_SHIFT (7U)
1015 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR135_MASK (0x00000080U)
1017 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR136_SHIFT (8U)
1018 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR136_MASK (0x00000100U)
1020 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR137_SHIFT (9U)
1021 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR137_MASK (0x00000200U)
1023 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR138_SHIFT (10U)
1024 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR138_MASK (0x00000400U)
1026 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR139_SHIFT (11U)
1027 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR139_MASK (0x00000800U)
1029 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR140_SHIFT (12U)
1030 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR140_MASK (0x00001000U)
1032 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR141_SHIFT (13U)
1033 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR141_MASK (0x00002000U)
1035 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR142_SHIFT (14U)
1036 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR142_MASK (0x00004000U)
1038 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR143_SHIFT (15U)
1039 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR143_MASK (0x00008000U)
1041 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR144_SHIFT (16U)
1042 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR144_MASK (0x00010000U)
1044 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR145_SHIFT (17U)
1045 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR145_MASK (0x00020000U)
1047 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR146_SHIFT (18U)
1048 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR146_MASK (0x00040000U)
1050 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR147_SHIFT (19U)
1051 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR147_MASK (0x00080000U)
1053 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR148_SHIFT (20U)
1054 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR148_MASK (0x00100000U)
1056 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR149_SHIFT (21U)
1057 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR149_MASK (0x00200000U)
1059 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR150_SHIFT (22U)
1060 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR150_MASK (0x00400000U)
1062 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR151_SHIFT (23U)
1063 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR151_MASK (0x00800000U)
1065 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR152_SHIFT (24U)
1066 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR152_MASK (0x01000000U)
1068 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR153_SHIFT (25U)
1069 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR153_MASK (0x02000000U)
1071 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR154_SHIFT (26U)
1072 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR154_MASK (0x04000000U)
1074 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR155_SHIFT (27U)
1075 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR155_MASK (0x08000000U)
1077 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR156_SHIFT (28U)
1078 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR156_MASK (0x10000000U)
1080 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR157_SHIFT (29U)
1081 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR157_MASK (0x20000000U)
1083 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR158_SHIFT (30U)
1084 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR158_MASK (0x40000000U)
1086 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR159_SHIFT (31U)
1087 #define MPU_WKG_ENB_E_1_WKG_ENB_FOR_INTR159_MASK (0x80000000U)
1089 #define MPU_AUX_CORE_BOOT_0_AUX_CORE_BOOT_0_SHIFT (0U)
1090 #define MPU_AUX_CORE_BOOT_0_AUX_CORE_BOOT_0_MASK (0xffffffffU)
1092 #define MPU_AUX_CORE_BOOT_1_AUX_CORE_BOOT_1_SHIFT (0U)
1093 #define MPU_AUX_CORE_BOOT_1_AUX_CORE_BOOT_1_MASK (0xffffffffU)
1095 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_0_SHIFT (0U)
1096 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_0_MASK (0x00000001U)
1098 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_1_SHIFT (1U)
1099 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_1_MASK (0x00000002U)
1101 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_2_SHIFT (2U)
1102 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_2_MASK (0x00000004U)
1104 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_3_SHIFT (3U)
1105 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_3_MASK (0x00000008U)
1107 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_4_SHIFT (4U)
1108 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_4_MASK (0x00000010U)
1110 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_5_SHIFT (5U)
1111 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_5_MASK (0x00000020U)
1113 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_6_SHIFT (6U)
1114 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_6_MASK (0x00000040U)
1116 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_7_SHIFT (7U)
1117 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_7_MASK (0x00000080U)
1119 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_8_SHIFT (8U)
1120 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_8_MASK (0x00000100U)
1122 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_9_SHIFT (9U)
1123 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_9_MASK (0x00000200U)
1125 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_10_SHIFT (10U)
1126 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_10_MASK (0x00000400U)
1128 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_11_SHIFT (11U)
1129 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_11_MASK (0x00000800U)
1131 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_12_SHIFT (12U)
1132 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_12_MASK (0x00001000U)
1134 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_13_SHIFT (13U)
1135 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_13_MASK (0x00002000U)
1137 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_14_SHIFT (14U)
1138 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_14_MASK (0x00004000U)
1140 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_15_SHIFT (15U)
1141 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_15_MASK (0x00008000U)
1143 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_16_SHIFT (16U)
1144 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_16_MASK (0x00010000U)
1146 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_17_SHIFT (17U)
1147 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_17_MASK (0x00020000U)
1149 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_18_SHIFT (18U)
1150 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_18_MASK (0x00040000U)
1152 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_19_SHIFT (19U)
1153 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_19_MASK (0x00080000U)
1155 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_20_SHIFT (20U)
1156 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_20_MASK (0x00100000U)
1158 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_21_SHIFT (21U)
1159 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_21_MASK (0x00200000U)
1161 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_22_SHIFT (22U)
1162 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_22_MASK (0x00400000U)
1164 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_23_SHIFT (23U)
1165 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_23_MASK (0x00800000U)
1167 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_24_SHIFT (24U)
1168 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_24_MASK (0x01000000U)
1170 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_25_SHIFT (25U)
1171 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_25_MASK (0x02000000U)
1173 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_26_SHIFT (26U)
1174 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_26_MASK (0x04000000U)
1176 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_27_SHIFT (27U)
1177 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_27_MASK (0x08000000U)
1179 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_28_SHIFT (28U)
1180 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_28_MASK (0x10000000U)
1182 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_29_SHIFT (29U)
1183 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_29_MASK (0x20000000U)
1185 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_30_SHIFT (30U)
1186 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_30_MASK (0x40000000U)
1188 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_31_SHIFT (31U)
1189 #define MPU_STM_HWEVENTS_INV_STM_HWEVENT_INV_31_MASK (0x80000000U)
1191 #define MPU_AMBA_IF_MODE_SBD_SHIFT (0U)
1192 #define MPU_AMBA_IF_MODE_SBD_MASK (0x00000001U)
1194 #define MPU_AMBA_IF_MODE_BCM_SHIFT (1U)
1195 #define MPU_AMBA_IF_MODE_BCM_MASK (0x00000002U)
1197 #define MPU_AMBA_IF_MODE_BO_SHIFT (2U)
1198 #define MPU_AMBA_IF_MODE_BO_MASK (0x00000004U)
1200 #define MPU_AMBA_IF_MODE_BI_SHIFT (3U)
1201 #define MPU_AMBA_IF_MODE_BI_MASK (0x00000008U)
1203 #define MPU_AMBA_IF_MODE_APB_FENCE_EN_SHIFT (4U)
1204 #define MPU_AMBA_IF_MODE_APB_FENCE_EN_MASK (0x00000010U)
1206 #define MPU_AMBA_IF_MODE_RESERVED_SHIFT (6U)
1207 #define MPU_AMBA_IF_MODE_RESERVED_MASK (0xffffffc0U)
1209 #define MPU_AMBA_IF_MODE_ES2_PM_MODE_SHIFT (5U)
1210 #define MPU_AMBA_IF_MODE_ES2_PM_MODE_MASK (0x00000020U)
1212 #define MPU_TIMESTAMPCYCLELO_COUNTER_31_0_SHIFT (0U)
1213 #define MPU_TIMESTAMPCYCLELO_COUNTER_31_0_MASK (0xffffffffU)
1215 #define MPU_TIMESTAMPCYCLEHI_COUNTER_47_32_SHIFT (0U)
1216 #define MPU_TIMESTAMPCYCLEHI_COUNTER_47_32_MASK (0x0000ffffU)
1218 #define MPU_TIMESTAMPCYCLEHI_RESERVED_SHIFT (16U)
1219 #define MPU_TIMESTAMPCYCLEHI_RESERVED_MASK (0xffff0000U)
1221 #ifdef __cplusplus
1222 }
1223 #endif
1224 #endif /* _HW_MPU_WUGEN_H_ */