[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / csl / arch / c66x / src / dsp_wugen.c
1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 * \file dsp_wugen.c
36 *
37 * \brief DSP Wake up Generator related APIs.
38 *
39 * This file contains the APIs for configuring DSP_WUGEN
40 *
41 **/
43 /* ========================================================================== */
44 /* Include Files */
45 /* ========================================================================== */
47 #include <stdint.h>
48 #include <ti/csl/hw_types.h>
49 #include <ti/csl/soc.h>
50 #include <ti/csl/soc.h>
51 #include <ti/csl/arch/csl_arch.h>
52 #include <dsp_wugen.h>
54 /* ========================================================================== */
55 /* Macros & Typedefs */
56 /* ========================================================================== */
58 #define MAX_INTERNAL_INTR (32U)
59 /** \brief Maximum Number of internal interrupts */
61 #define REG_IDX_SHIFT (0x05U)
62 /** \brief Register Index */
64 #define REG_BIT_MASK (0x1FU)
65 /** \brief Register Bit Mask */
67 #define NUM_BYTES_REG (0x4U)
68 /** \brief Address offset per register */
70 /* ========================================================================== */
71 /* Structures and Enums */
72 /* ========================================================================== */
74 /* None */
76 /* ========================================================================== */
77 /* Internal Function Declarations */
78 /* ========================================================================== */
80 /**
81 * \brief Configure the wakeup gen register.
82 *
83 * \param intNum Interrupt number to be set.
84 *
85 * \return None
86 */
87 void DSP_wugen_setWakeupReg(uint32_t intNum);
89 /* ========================================================================== */
90 /* Global Variables */
91 /* ========================================================================== */
93 /* None */
95 /* ========================================================================== */
96 /* Function Definitions */
97 /* ========================================================================== */
99 void DSP_WUGEN_IRQ_Init(void)
100 {
101 DSP_WUGEN_IRQ_DisableAll();
102 }
104 void DSP_WUGEN_IRQ_DisableAll(void)
105 {
106 HW_WR_REG32(SOC_DSP_SYSTEM_BASE + DSP_IRQWAKEEN0, 0);
107 HW_WR_REG32(SOC_DSP_SYSTEM_BASE + DSP_IRQWAKEEN1, 0);
108 }
110 void DSP_WUGEN_DMAEVENT_Init(void)
111 {
112 DSP_WUGEN_DMAEVENT_DisableAll();
113 }
115 void DSP_WUGEN_DMAEVENT_DisableAll(void)
116 {
117 HW_WR_REG32(SOC_DSP_SYSTEM_BASE + DSP_DMAWAKEEN0, 0);
118 HW_WR_REG32(SOC_DSP_SYSTEM_BASE + DSP_DMAWAKEEN1, 0);
119 }
121 void DSP_WUGEN_IRQ_Interrupt_Lookup(void)
122 {
123 uint32_t index;
124 uint32_t regval;
125 uint32_t intsel;
127 for (index = 0U; index < 3U; index++)
128 {
129 regval = HW_RD_REG32(SOC_DSP_ICFG_BASE +
130 (DSP_INTMUX1 + (4U * index)));
131 intsel = regval & 0xFFU;
132 DSP_wugen_setWakeupReg(intsel);
133 intsel = (regval & 0xFF00U) >> 8U;
134 DSP_wugen_setWakeupReg(intsel);
135 intsel = (regval & 0xFF0000U) >> 16U;
136 DSP_wugen_setWakeupReg(intsel);
137 intsel = (regval & 0xFF000000U) >> 24U;
138 DSP_wugen_setWakeupReg(intsel);
139 }
141 for (index = 0U; index < 2U; index++)
142 {
143 regval = HW_RD_REG32(SOC_DSP_ICFG_BASE +
144 (DSP_EVTMASK1 + (4U * index)));
145 regval = ~(regval);
146 regval = HW_RD_REG32(SOC_DSP_SYSTEM_BASE +
147 (DSP_IRQWAKEEN0 + (4U * index))) | regval;
148 HW_WR_REG32(SOC_DSP_SYSTEM_BASE +
149 (DSP_IRQWAKEEN0 + (4U * index)),
150 regval);
151 }
152 }
154 void DSP_WUGEN_IRQ_Enable(uint16_t intrNum)
155 {
156 uint32_t addr, index, mask, shift;
157 int32_t modIntrNum = ((int32_t) intrNum - (int32_t) MAX_INTERNAL_INTR);
159 if (modIntrNum >= 0)
160 {
161 index = (uint32_t) modIntrNum >> REG_IDX_SHIFT;
162 /* To Handle cases of interrupt numbers being higher than 95 */
163 if (index < 2U)
164 {
165 shift = (uint32_t) modIntrNum & REG_BIT_MASK;
166 mask = ((uint32_t) 1) << shift;
167 addr = SOC_DSP_SYSTEM_BASE + (DSP_IRQWAKEEN0 + (NUM_BYTES_REG * index));
169 /* Enable the wakeup event for interrupt number passed */
170 HW_WR_FIELD32_RAW(addr,
171 mask,
172 shift,
173 (uint32_t) 1);
174 }
175 }
176 }
178 void DSP_WUGEN_DMAEVENT_Enable(uint16_t dmaEvtNum)
179 {
180 uint32_t addr, index, mask, shift;
181 if (dmaEvtNum < CSL_XBAR_INST_DMA_DSP1_DREQ_19)
182 {
183 index = (uint32_t) dmaEvtNum >> REG_IDX_SHIFT;
184 shift = (uint32_t) dmaEvtNum & REG_BIT_MASK;
185 mask = ((uint32_t) 1) << shift;
186 addr = SOC_DSP_SYSTEM_BASE + (DSP_DMAWAKEEN0 + (NUM_BYTES_REG * index));
188 /* Enable the wakeup event for dma event number passed */
189 HW_WR_FIELD32_RAW(addr,
190 mask,
191 shift,
192 (uint32_t) 1);
193 }
194 }
196 void DSP_WUGEN_IRQ_Disable(uint16_t intrNum)
197 {
198 uint32_t addr, index, mask, shift;
199 int32_t modIntrNum = ((int32_t) intrNum - (int32_t) MAX_INTERNAL_INTR);
201 if (modIntrNum >= 0)
202 {
203 index = (uint32_t) modIntrNum >> REG_IDX_SHIFT;
204 shift = (uint32_t) modIntrNum & REG_BIT_MASK;
205 mask = ((uint32_t) 1) << shift;
206 addr = SOC_DSP_SYSTEM_BASE + (DSP_IRQWAKEEN0 + (NUM_BYTES_REG * index));
208 /* Enable the wakeup event for interrupt number passed */
209 HW_WR_FIELD32_RAW(addr,
210 mask,
211 shift,
212 0);
213 }
214 }
216 void DSP_WUGEN_DMAEVENT_Disable(uint16_t dmaEvtNum)
217 {
218 uint32_t addr, index, mask, shift;
219 if (dmaEvtNum < CSL_XBAR_INST_DMA_DSP1_DREQ_19)
220 {
221 index = (uint32_t) dmaEvtNum >> REG_IDX_SHIFT;
222 shift = (uint32_t) dmaEvtNum & REG_BIT_MASK;
223 mask = ((uint32_t) 1) << shift;
224 addr = SOC_DSP_SYSTEM_BASE + (DSP_DMAWAKEEN0 + (NUM_BYTES_REG * index));
226 /* Enable the wakeup event for dma event number passed */
227 HW_WR_FIELD32_RAW(addr,
228 mask,
229 shift,
230 0);
231 }
232 }
234 /* ========================================================================== */
235 /* Internal Function Definitions */
236 /* ========================================================================== */
238 void DSP_wugen_setWakeupReg(uint32_t intNum)
239 {
240 int32_t modIntrNum = ((int32_t) intNum - (int32_t) MAX_INTERNAL_INTR);
241 uint32_t offset;
242 uint32_t shift;
243 uint32_t wakeupregval;
245 if (modIntrNum >= 0)
246 {
247 offset = ((uint32_t) modIntrNum / 32U);
248 shift = ((uint32_t) modIntrNum % 32U);
249 wakeupregval = HW_RD_REG32(SOC_DSP_SYSTEM_BASE +
250 (DSP_IRQWAKEEN0 + (4U * offset)));
251 wakeupregval = wakeupregval | ((uint32_t) 1 << shift);
252 HW_WR_REG32(SOC_DSP_SYSTEM_BASE +
253 (DSP_IRQWAKEEN0 + (4U * offset)),
254 wakeupregval);
255 }
256 }
257 /********************************** End Of File ******************************/