[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / csl / arch / m4 / src / ipu_wugen.c
1 /*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 * \file ipu_wugen.c
36 *
37 * \brief IPU WUGEN related APIs.
38 *
39 * This file contains the APIs for configuring IPU_WUGEN
40 *
41 */
43 /* ========================================================================== */
44 /* Include Files */
45 /* ========================================================================== */
47 #include <stdint.h>
48 #include <ti/csl/hw_types.h>
49 #include <ti/csl/soc.h>
50 #include <ipu_wugen.h>
52 /* ========================================================================== */
53 /* Macros & Typedefs */
54 /* ========================================================================== */
56 #define REG_IDX_SHIFT (0x05U)
57 /** \brief Register Index */
59 #define REG_BIT_MASK (0x1FU)
60 /** \brief Register Bit Mask */
62 #define NUM_BYTES_REG (0x4U)
63 /** \brief Address offset per register */
65 /* ========================================================================== */
66 /* Structures and Enums */
67 /* ========================================================================== */
69 /* None */
71 /* ========================================================================== */
72 /* Internal Function Declarations */
73 /* ========================================================================== */
75 /* None */
77 /* ========================================================================== */
78 /* Global Variables */
79 /* ========================================================================== */
81 /* None */
83 /* ========================================================================== */
84 /* Function Declarations */
85 /* ========================================================================== */
87 void IPU_WUGEN_Init(void)
88 {
89 IPU_WUGEN_DisableAll();
90 }
92 void IPU_WUGEN_DisableAll(void)
93 {
94 HW_WR_REG32(SOC_IPU1_WUGEN_BASE + IPU_WUGEN_MEVT0, 0U);
95 HW_WR_REG32(SOC_IPU1_WUGEN_BASE + IPU_WUGEN_MEVT1, 0U);
96 }
98 /*
99 * Interrupts should be dis/enabled before/after calling this function.
100 */
101 void IPU_WUGEN_Interrupt_Lookup(void)
102 {
103 uint32_t regval, rdVal;
104 uint32_t index = 0U;
106 for (index = 0U; index < 2U; index++)
107 {
108 /*
109 * Fix for OMAPS00325441
110 * Just copy:
111 * IPU_M4_NVIC_EXTERNAL_INTERRUPT_SETEN_0_31 -> IPU_WUGEN_MEVT0
112 * IPU_M4_NVIC_EXTERNAL_INTERRUPT_SETEN_0_31 + 4 -> IPU_WUGEN_MEVT1
113 */
114 /* Writing to WUGEN_MEVT0 & WUGEN_MEVT1*/
115 regval = HW_RD_REG32((SOC_IPU1_C0_INTC_BASE +
116 IPU_M4_NVIC_EXTERNAL_INTERRUPT_SETEN_0_31) +
117 (NUM_BYTES_REG * index));
118 regval |= HW_RD_REG32(SOC_IPU1_WUGEN_BASE +
119 (IPU_WUGEN_MEVT0 + (NUM_BYTES_REG * index)));
121 HW_WR_REG32(SOC_IPU1_WUGEN_BASE +
122 (IPU_WUGEN_MEVT0 + (NUM_BYTES_REG * index)),
123 regval);
125 rdVal = HW_RD_REG32(SOC_IPU1_WUGEN_BASE +
126 (IPU_WUGEN_MEVT0 + (NUM_BYTES_REG * index)));
128 /*
129 * Fix for OMAPS00325441: Fix race condition
130 * In case of possible race-conditions between core0 and core1, one
131 * write will be missed. So if write was not successful, write again.
132 * This approach will work because only two cores are writing to same
133 * register. It will not work for more than two cores.
134 * Race condition within the following if-condition will not occur since
135 * the other core will read the same register only after at least one
136 * iteration of this for-loop and, therefore, later than the execution
137 * of the following if-condition.
138 */
139 if (regval != (regval & rdVal))
140 {
141 regval |= HW_RD_REG32(SOC_IPU1_WUGEN_BASE +
142 (IPU_WUGEN_MEVT0 + (NUM_BYTES_REG * index)));
143 HW_WR_REG32(SOC_IPU1_WUGEN_BASE +
144 (IPU_WUGEN_MEVT0 + (NUM_BYTES_REG * index)),
145 regval);
146 }
147 }
148 }
150 void IPU_WUGEN_Enable(uint16_t intrNum)
151 {
152 uint32_t addr, index, mask, shift;
153 uint16_t modIntNum = intrNum - IPU_WUGEN_NUM_INTR_INTERNAL;
155 if (modIntNum > (IPU_WUGEN_FIRST_EXTERNAL_INT_NUM -
156 IPU_WUGEN_NUM_INTR_INTERNAL))
157 {
158 index = (uint32_t) modIntNum >> REG_IDX_SHIFT;
159 shift = (uint32_t) modIntNum & REG_BIT_MASK;
160 mask = ((uint32_t) 1U) << shift;
161 addr = SOC_IPU1_WUGEN_BASE + (IPU_WUGEN_MEVT0 + (NUM_BYTES_REG * index));
163 /* Enable the wakeup event for interrupt number passed */
164 HW_WR_FIELD32_RAW(addr,
165 mask,
166 shift,
167 (uint32_t) 1U);
168 }
169 }
171 void IPU_WUGEN_Disable(uint16_t intrNum)
172 {
173 uint32_t addr, index, mask, shift;
174 uint16_t modIntNum = intrNum - IPU_WUGEN_NUM_INTR_INTERNAL;
176 if (modIntNum > (IPU_WUGEN_FIRST_EXTERNAL_INT_NUM -
177 IPU_WUGEN_NUM_INTR_INTERNAL))
178 {
179 index = (uint32_t) modIntNum >> REG_IDX_SHIFT;
180 shift = (uint32_t) modIntNum & REG_BIT_MASK;
181 mask = ((uint32_t) 1U) << shift;
182 addr = SOC_IPU1_WUGEN_BASE + (IPU_WUGEN_MEVT0 + (NUM_BYTES_REG * index));
184 /* Enable the wakeup event for interrupt number passed */
185 HW_WR_FIELD32_RAW(addr, mask, shift, (uint32_t) 0U);
186 }
187 }
189 /* -------------------------------------------------------------------------- */
190 /* Internal Function Definitions */
191 /* -------------------------------------------------------------------------- */
193 /* None */