[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / csl / csl_edma3Aux.h
1 /**
2 * @file csl_edma3Aux.h
3 *
4 * @brief
5 * This is the EDMA Auxilary Header File which exposes the various
6 * CSL Functional Layer API's to configure the EDMA Module.
7 *
8 * \par
9 * ============================================================================
10 * @n (C) Copyright 2002, 2003, 2004, 2005, 2008, 2009, Texas Instruments, Inc.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 *
19 * Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the
22 * distribution.
23 *
24 * Neither the name of Texas Instruments Incorporated nor the names of
25 * its contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 */
42 #ifndef CSL_EDMA3AUX_H
43 #define CSL_EDMA3AUX_H
45 #include <ti/csl/csl_edma3.h>
47 /** @addtogroup CSL_EDMA3_FUNCTION
48 @{ */
50 /** ============================================================================
51 * @n@b CSL_edma3GetInfo
52 *
53 * @b Description
54 * @n The function gets the EDMA Channel Controller Configuration Information
55 * which includes reading the peripheral revision register and configuration
56 * register.
57 *
58 * @b Arguments
59 * @verbatim
60 hModule Module Handle
61 response Output parameter populated with the configuration information.
62 @endverbatim
63 *
64 * <b> Return Value </b>
65 * @n None
66 *
67 * <b> Pre Condition </b>
68 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
69 *
70 * <b> Post Condition </b>
71 * @n None
72 *
73 * @b Reads
74 * @n TPCC_TPCC_CFG,TPCC_TPCC_PID
75 *
76 * @b Example
77 * @verbatim
78 CSL_Edma3Handle hModule;
79 CSL_Edma3Obj edmaObj;
80 CSL_Edma3Context context;
81 CSL_Status status;
82 CSL_Edma3QueryInfo info;
84 // Module Initialization
85 CSL_edma3Init(&context);
87 // Module Level Open
88 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
90 // Get Module Info
91 CSL_edma3GetInfo(hModule,&info);
92 ...
93 @endverbatim
94 * ===========================================================================
95 */
96 /* for misra warnings*/
97 static inline void CSL_edma3GetInfo
98 (
99 CSL_Edma3Handle hModule,
100 CSL_Edma3QueryInfo* response
101 );
102 static inline void CSL_edma3GetInfo
103 (
104 CSL_Edma3Handle hModule,
105 CSL_Edma3QueryInfo* response
106 )
107 {
108 /* Populate the configuration and peripheral id. */
109 response->config = hModule->regs->TPCC_CFG;
110 response->revision = hModule->regs->TPCC_PID;
111 return;
112 }
114 /** ============================================================================
115 * @n@b CSL_edma3MapDMAChannelToParamBlock
116 *
117 * @b Description
118 * @n The function maps the DMA Channel to the specified PARAM Entry Block.
119 *
120 * @b Arguments
121 * @verbatim
122 hModule Module Handle
123 dmaChannel DMA Channel Number which is to be mapped.
124 paramId Parameter Identifier to be mapped to.
125 @endverbatim
126 *
127 * <b> Return Value </b>
128 * @n None
129 *
130 * <b> Pre Condition </b>
131 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
132 *
133 * <b> Post Condition </b>
134 * @n DMA Channel is mapped to the specified PARAM Block.
135 *
136 * @b Writes
137 * @n TPCC_TPCC_DCHMAP_PAENTRY
138 *
139 * @b Example
140 * @verbatim
141 CSL_Edma3Handle hModule;
142 CSL_Edma3Obj edmaObj;
143 CSL_Edma3Context context;
144 CSL_Status status;
146 // Module Initialization
147 CSL_edma3Init(&context);
149 // Module Level Open
150 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
152 // Maps DMA Channel 1 to Param ID Block 5.
153 CSL_edma3MapDMAChannelToParamBlock(hModule, 1, 5);
154 ...
155 @endverbatim
156 * ===========================================================================
157 */
158 /* for misra warnings*/
159 static inline void CSL_edma3MapDMAChannelToParamBlock
160 (
161 CSL_Edma3Handle hModule,
162 Uint8 dmaChannel,
163 Uint16 paramId
164 );
165 static inline void CSL_edma3MapDMAChannelToParamBlock
166 (
167 CSL_Edma3Handle hModule,
168 Uint8 dmaChannel,
169 Uint16 paramId
170 )
171 {
172 /* Map the DMA channel to the parameter block. */
173 CSL_FINS(hModule->regs->TPCC_DCHMAP[dmaChannel], TPCC_TPCC_DCHMAP0_PAENTRY, (Uint32)paramId);
174 return;
175 }
177 /** ============================================================================
178 * @n@b CSL_edma3GetDMAChannelToParamBlockMapping
179 *
180 * @b Description
181 * @n The function gets the PARAM Entry ID to which a specific DMA Channel
182 * is mapped.
183 *
184 * @b Arguments
185 * @verbatim
186 hModule Module Handle
187 dmaChannel DMA Channel Number whose mapping is to be found.
188 @endverbatim
189 *
190 * <b> Return Value </b>
191 * @n Paramater ID to which the specific DMA Channel is mapped to.
192 *
193 * <b> Pre Condition </b>
194 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
195 *
196 * <b> Post Condition </b>
197 * @n None
198 *
199 * @b Reads
200 * @n TPCC_TPCC_DCHMAP_PAENTRY
201 *
202 * @b Example
203 * @verbatim
204 CSL_Edma3Handle hModule;
205 CSL_Edma3Obj edmaObj;
206 CSL_Edma3Context context;
207 CSL_Status status;
208 Uint16 paramId;
210 // Module Initialization
211 CSL_edma3Init(&context);
213 // Module Level Open
214 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
216 // Get the mapping information for DMA channel 1.
217 paramId = CSL_edma3GetDMAChannelToParamBlockMapping(hModule, 1);
218 ...
219 @endverbatim
220 * ===========================================================================
221 */
222 /* for misra warnings*/
223 static inline Uint16 CSL_edma3GetDMAChannelToParamBlockMapping
224 (
225 CSL_Edma3Handle hModule,
226 Uint8 dmaChannel
227 );
228 static inline Uint16 CSL_edma3GetDMAChannelToParamBlockMapping
229 (
230 CSL_Edma3Handle hModule,
231 Uint8 dmaChannel
232 )
233 {
234 /* Get the Param Block to which the DMA channel is mapped to. */
235 return (Uint16) CSL_FEXT(hModule->regs->TPCC_DCHMAP[dmaChannel], TPCC_TPCC_DCHMAP0_PAENTRY);
236 }
238 /** ============================================================================
239 * @n@b CSL_edma3MapQDMAChannelToParamBlock
240 *
241 * @b Description
242 * @n The function maps the QDMA Channel to the specified PARAM Entry Block.
243 *
244 * @b Arguments
245 * @verbatim
246 hModule Module Handle
247 qdmaChannel QDMA Channel Number which is to be mapped.
248 paramId Parameter Identifier to be mapped to.
249 @endverbatim
250 *
251 * <b> Return Value </b>
252 * @n None
253 *
254 * <b> Pre Condition </b>
255 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
256 *
257 * <b> Post Condition </b>
258 * @n QDMA Channel is mapped to the specified PARAM Block.
259 *
260 * @b Writes
261 * @n TPCC_TPCC_QCHMAP_PAENTRY
262 *
263 * @b Example
264 * @verbatim
265 CSL_Edma3Handle hModule;
266 CSL_Edma3Obj edmaObj;
267 CSL_Edma3Context context;
268 CSL_Status status;
270 // Module Initialization
271 CSL_edma3Init(&context);
273 // Module Level Open
274 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
276 // Maps QDMA Channel 1 to Param ID Block 5.
277 CSL_edma3MapQDMAChannelToParamBlock(hModule, 1, 5);
278 ...
279 @endverbatim
280 * ===========================================================================
281 */
282 /* for misra warnings*/
283 static inline void CSL_edma3MapQDMAChannelToParamBlock
284 (
285 CSL_Edma3Handle hModule,
286 Uint8 qdmaChannel,
287 Uint16 paramId
288 );
289 static inline void CSL_edma3MapQDMAChannelToParamBlock
290 (
291 CSL_Edma3Handle hModule,
292 Uint8 qdmaChannel,
293 Uint16 paramId
294 )
295 {
296 CSL_FINS(hModule->regs->TPCC_QCHMAP[qdmaChannel], TPCC_TPCC_QCHMAP0_PAENTRY, (Uint32)paramId);
297 return;
298 }
300 /** ============================================================================
301 * @n@b CSL_edma3GetQDMAChannelToParamBlockMapping
302 *
303 * @b Description
304 * @n The function gets the PARAM Entry ID to which a specific QDMA Channel
305 * is mapped.
306 *
307 * @b Arguments
308 * @verbatim
309 hModule Module Handle
310 qdmaChannel QDMA Channel Number whose mapping is to be found.
311 @endverbatim
312 *
313 * <b> Return Value </b>
314 * @n Paramater ID to which the specific QDMA Channel is mapped to.
315 *
316 * <b> Pre Condition </b>
317 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
318 *
319 * <b> Post Condition </b>
320 * @n None
321 *
322 * @b Reads
323 * @n TPCC_TPCC_QCHMAP_PAENTRY
324 *
325 * @b Example
326 * @verbatim
327 CSL_Edma3Handle hModule;
328 CSL_Edma3Obj edmaObj;
329 CSL_Edma3Context context;
330 CSL_Status status;
332 // Module Initialization
333 CSL_edma3Init(&context);
335 // Module Level Open
336 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
338 // Get the mapping information for QDMA channel 1.
339 paramId = CSL_edma3GetQDMAChannelMap(hModule, 1);
340 ...
341 @endverbatim
342 * ===========================================================================
343 */
344 /* for misra warnings*/
345 static inline Uint16 CSL_edma3GetQDMAChannelToParamBlockMapping
346 (
347 CSL_Edma3Handle hModule,
348 Uint8 qdmaChannel
349 );
350 static inline Uint16 CSL_edma3GetQDMAChannelToParamBlockMapping
351 (
352 CSL_Edma3Handle hModule,
353 Uint8 qdmaChannel
354 )
355 {
356 return (Uint16) CSL_FEXT(hModule->regs->TPCC_QCHMAP[qdmaChannel], TPCC_TPCC_QCHMAP0_PAENTRY);
357 }
359 /** ============================================================================
360 * @n@b CSL_edma3SetQDMATriggerWord
361 *
362 * @b Description
363 * @n The function sets the trigger word of the PaRAM Entry block.
364 *
365 * @b Arguments
366 * @verbatim
367 hModule Module Handle
368 qdmaChannel QDMA Channel Number which is to be configured.
369 trword Trigger Word to be configured.
370 @endverbatim
371 *
372 * <b> Return Value </b>
373 * @n None
374 *
375 * <b> Pre Condition </b>
376 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
377 *
378 * <b> Post Condition </b>
379 * @n QDMA Channel is mapped to the specified PARAM Block.
380 *
381 * @b Writes
382 * @n TPCC_TPCC_QCHMAP_TRWORD
383 *
384 * @b Example
385 * @verbatim
386 CSL_Edma3Handle hModule;
387 CSL_Edma3Obj edmaObj;
388 CSL_Edma3Context context;
389 CSL_Status status;
391 // Module Initialization
392 CSL_edma3Init(&context);
394 // Module Level Open
395 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
397 // Configure QDMA Channel 1 Trigger Word as 0
398 CSL_edma3SetQDMATriggerWord(hModule, 1, 0);
399 ...
400 @endverbatim
401 * ===========================================================================
402 */
403 /* for misra warnings*/
404 static inline void CSL_edma3SetQDMATriggerWord
405 (
406 CSL_Edma3Handle hModule,
407 Uint8 qdmaChannel,
408 Uint8 trword
409 );
410 static inline void CSL_edma3SetQDMATriggerWord
411 (
412 CSL_Edma3Handle hModule,
413 Uint8 qdmaChannel,
414 Uint8 trword
415 )
416 {
417 CSL_FINS(hModule->regs->TPCC_QCHMAP[qdmaChannel], TPCC_TPCC_QCHMAP0_TRWORD, (Uint32)trword);
418 return;
419 }
421 /** ============================================================================
422 * @n@b CSL_edma3GetQDMATriggerWord
423 *
424 * @b Description
425 * @n The function gets the trigger word of the PaRAM Entry block.
426 *
427 * @b Arguments
428 * @verbatim
429 hModule Module Handle
430 qdmaChannel QDMA Channel Number which is to be configured.
431 trword Trigger Word to be retreived populated by this API.
432 @endverbatim
433 *
434 * <b> Return Value </b>
435 * @n None
436 *
437 * <b> Pre Condition </b>
438 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
439 *
440 * <b> Post Condition </b>
441 * @n QDMA Channel is mapped to the specified PARAM Block.
442 *
443 * @b Reads
444 * @n TPCC_TPCC_QCHMAP_TRWORD
445 *
446 * @b Example
447 * @verbatim
448 CSL_Edma3Handle hModule;
449 CSL_Edma3Obj edmaObj;
450 CSL_Edma3Context context;
451 CSL_Status status;
452 Uint8 trWord;
454 // Module Initialization
455 CSL_edma3Init(&context);
457 // Module Level Open
458 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
460 // Get the QDMA Channel 1 Trigger Word
461 trWord = CSL_edma3SetQDMATriggerWord(hModule, 1);
462 ...
463 @endverbatim
464 * ===========================================================================
465 */
466 /* for misra warnings*/
467 static inline void CSL_edma3GetQDMATriggerWord
468 (
469 CSL_Edma3Handle hModule,
470 Uint8 qdmaChannel,
471 Uint8* trword
472 );
473 static inline void CSL_edma3GetQDMATriggerWord
474 (
475 CSL_Edma3Handle hModule,
476 Uint8 qdmaChannel,
477 Uint8* trword
478 )
479 {
480 /* Extract the trigger word. */
481 *trword = CSL_FEXT(hModule->regs->TPCC_QCHMAP[qdmaChannel], TPCC_TPCC_QCHMAP0_TRWORD);
482 }
484 /** ============================================================================
485 * @n@b CSL_edma3MapDMAChannelToEventQueue
486 *
487 * @b Description
488 * @n The function maps the event ID to the specific DMA Queue.
489 *
490 * @b Arguments
491 * @verbatim
492 hModule Module Handle
493 dmaChannel DMA Channel to which the event is mapped.
494 eventQueue Event Queue which is to be mapped.
495 @endverbatim
496 *
497 * <b> Return Value </b>
498 * @n None
499 *
500 * <b> Pre Condition </b>
501 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
502 *
503 * <b> Post Condition </b>
504 * @n DMA Channel is mapped to the specified Event Queue.
505 *
506 * @b Writes
507 * @n TPCC_TPCC_DMAQNUM_E0;TPCC_TPCC_DMAQNUM_E1;TPCC_TPCC_DMAQNUM_E2;
508 * TPCC_TPCC_DMAQNUM_E3;TPCC_TPCC_DMAQNUM_E4;TPCC_TPCC_DMAQNUM_E5;
509 * TPCC_TPCC_DMAQNUM_E6;TPCC_TPCC_DMAQNUM_E7
510 *
511 * @b Example
512 * @verbatim
513 CSL_Edma3Handle hModule;
514 CSL_Edma3Obj edmaObj;
515 CSL_Edma3Context context;
516 CSL_Status status;
518 // Module Initialization
519 CSL_edma3Init(&context);
521 // Module Level Open
522 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
524 // Maps DMA Channel 1 to Event Queue 2
525 CSL_edma3MapDMAChannelToEventQueue(hModule, 1, 2);
526 ...
527 @endverbatim
528 * ===========================================================================
529 */
530 /* for misra warnings*/
531 static inline void CSL_edma3MapDMAChannelToEventQueue
532 (
533 CSL_Edma3Handle hModule,
534 Uint8 dmaChannel,
535 Uint8 eventQueue
536 );
537 static inline void CSL_edma3MapDMAChannelToEventQueue
538 (
539 CSL_Edma3Handle hModule,
540 Uint8 dmaChannel,
541 Uint8 eventQueue
542 )
543 {
544 Uint8 dmaRegIndex;
545 Uint8 lsb;
547 /* There are 8 channels per register; use this to determine the DMAQNUM register Index. */
548 dmaRegIndex = dmaChannel >> 3;
550 /* Compute the bit position where the value is to be written. */
551 lsb = (dmaChannel - (dmaRegIndex * 8U)) << 2;
553 /* Write the event Queue */
554 Uint32 temp_Var = ((Uint32)lsb) + 2U;
555 CSL_FINSR(hModule->regs->TPCC_DMAQNUM[dmaRegIndex], (temp_Var), (Uint32)(lsb), (Uint32)eventQueue);
556 }
558 /** ============================================================================
559 * @n@b CSL_edma3GetDMAChannelToEventQueueMapping
560 *
561 * @b Description
562 * @n The function gets the mapping of the DMA Channel to the Event Queue
563 *
564 * @b Arguments
565 * @verbatim
566 hModule Module Handle
567 dmaChannel DMA Channel for which the mapping is to be retreived.
568 @endverbatim
569 *
570 * <b> Return Value </b>
571 * @n Event Queue to which the DMA channel is mapped to
572 *
573 * <b> Pre Condition </b>
574 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
575 *
576 * <b> Post Condition </b>
577 * @n None
578 *
579 * @b Reads
580 * @n TPCC_TPCC_DMAQNUM_E0;TPCC_TPCC_DMAQNUM_E1;TPCC_TPCC_DMAQNUM_E2;
581 * TPCC_TPCC_DMAQNUM_E3;TPCC_TPCC_DMAQNUM_E4;TPCC_TPCC_DMAQNUM_E5;
582 * TPCC_TPCC_DMAQNUM_E6;TPCC_TPCC_DMAQNUM_E7
583 *
584 * @b Example
585 * @verbatim
586 CSL_Edma3Handle hModule;
587 CSL_Edma3Obj edmaObj;
588 CSL_Edma3Context context;
589 CSL_Status status;
590 Uint8 eventQueue;
592 // Module Initialization
593 CSL_edma3Init(&context);
595 // Module Level Open
596 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
598 // Get the Event Queue mapping of DMA Channel 1
599 eventQueue = CSL_edma3GetDMAChannelToEventQueueMapping(hModule, 1);
600 ...
601 @endverbatim
602 * ===========================================================================
603 */
604 /* for misra warnings*/
605 static inline Uint8 CSL_edma3GetDMAChannelToEventQueueMapping
606 (
607 CSL_Edma3Handle hModule,
608 Uint8 dmaChannel
609 );
610 static inline Uint8 CSL_edma3GetDMAChannelToEventQueueMapping
611 (
612 CSL_Edma3Handle hModule,
613 Uint8 dmaChannel
614 )
615 {
616 Uint8 dmaRegIndex;
617 Uint8 lsb;
619 /* There are 8 channels per register; use this to determine the DMAQNUM register Index. */
620 dmaRegIndex = dmaChannel >> 3;
622 /* Compute the bit position from where the value is to be retreived. */
623 lsb = (dmaChannel - (dmaRegIndex * 8U)) << 2;
625 /* Get the event queue. */
626 Uint32 temp_Var = ((Uint32)lsb) + 2U;
627 return (Uint8)(CSL_FEXTR(hModule->regs->TPCC_DMAQNUM[dmaRegIndex], (temp_Var), (Uint32)(lsb)));
628 }
630 /** ============================================================================
631 * @n@b CSL_edma3MapQDMAChannelToEventQueue
632 *
633 * @b Description
634 * @n The function maps the event ID to the specific DMA Queue.
635 *
636 * @b Arguments
637 * @verbatim
638 hModule Module Handle
639 qdmaChannel QDMA Channel to which the event is mapped.
640 eventQueue Event Queue which is to be mapped.
641 @endverbatim
642 *
643 * <b> Return Value </b>
644 * @n None
645 *
646 * <b> Pre Condition </b>
647 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
648 *
649 * <b> Post Condition </b>
650 * @n DMA Channel is mapped to the specified Event Queue.
651 *
652 * @b Writes
653 * @n TPCC_TPCC_QDMAQNUM_E0;TPCC_TPCC_QDMAQNUM_E1;TPCC_TPCC_QDMAQNUM_E2;
654 * TPCC_TPCC_QDMAQNUM_E3;TPCC_TPCC_QDMAQNUM_E4;TPCC_TPCC_QDMAQNUM_E5;
655 * TPCC_TPCC_QDMAQNUM_E6;TPCC_TPCC_QDMAQNUM_E7
656 *
657 * @b Example
658 * @verbatim
659 CSL_Edma3Handle hModule;
660 CSL_Edma3Obj edmaObj;
661 CSL_Edma3Context context;
662 CSL_Status status;
664 // Module Initialization
665 CSL_edma3Init(&context);
667 // Module Level Open
668 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
670 // Maps QDMA Channel 1 to Event Queue 2
671 CSL_edma3MapQDMAChannelToEventQueue(hModule, 1, 2);
672 ...
673 @endverbatim
674 * ===========================================================================
675 */
676 /* for misra warnings*/
677 static inline void CSL_edma3MapQDMAChannelToEventQueue
678 (
679 CSL_Edma3Handle hModule,
680 Uint8 qdmaChannel,
681 Uint8 eventQueue
682 );
683 static inline void CSL_edma3MapQDMAChannelToEventQueue
684 (
685 CSL_Edma3Handle hModule,
686 Uint8 qdmaChannel,
687 Uint8 eventQueue
688 )
689 {
690 Uint8 lsb;
692 /* Compute the bit position where the value is to be written. */
693 lsb = qdmaChannel << 2;
695 /* Write the event Queue */
696 Uint32 temp_Var = ((Uint32)lsb) + 2U;
697 CSL_FINSR(hModule->regs->TPCC_QDMAQNUM, (temp_Var), (Uint32)(lsb), (Uint32)eventQueue);
698 }
700 /** ============================================================================
701 * @n@b CSL_edma3GetQDMAChannelToEventQueueMapping
702 *
703 * @b Description
704 * @n The function gets the mapping of the QDMA Channel to the Event Queue
705 *
706 * @b Arguments
707 * @verbatim
708 hModule Module Handle
709 qdmaChannel QDMA Channel for which the mapping is to be retreived.
710 @endverbatim
711 *
712 * <b> Return Value </b>
713 * @n Event Queue to which the QDMA channel is mapped to
714 *
715 * <b> Pre Condition </b>
716 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
717 *
718 * <b> Post Condition </b>
719 * @n None
720 *
721 * @b Reads
722 * @n TPCC_TPCC_QDMAQNUM_E0;TPCC_TPCC_QDMAQNUM_E1;TPCC_TPCC_QDMAQNUM_E2;
723 * TPCC_TPCC_QDMAQNUM_E3;TPCC_TPCC_QDMAQNUM_E4;TPCC_TPCC_QDMAQNUM_E5;
724 * TPCC_TPCC_QDMAQNUM_E6;TPCC_TPCC_QDMAQNUM_E7
725 *
726 * @b Example
727 * @verbatim
728 CSL_Edma3Handle hModule;
729 CSL_Edma3Obj edmaObj;
730 CSL_Edma3Context context;
731 CSL_Status status;
732 Uint8 eventQueue;
734 // Module Initialization
735 CSL_edma3Init(&context);
737 // Module Level Open
738 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
740 // Get the Event Queue mapping of QDMA Channel 1
741 eventQueue = CSL_edma3GetQDMAChannelToEventQueueMapping(hModule, 1);
742 ...
743 @endverbatim
744 * ===========================================================================
745 */
746 /* for misra warnings*/
747 static inline Uint8 CSL_edma3GetQDMAChannelToEventQueueMapping
748 (
749 CSL_Edma3Handle hModule,
750 Uint8 qdmaChannel
751 );
752 static inline Uint8 CSL_edma3GetQDMAChannelToEventQueueMapping
753 (
754 CSL_Edma3Handle hModule,
755 Uint8 qdmaChannel
756 )
757 {
758 Uint8 lsb;
760 /* Compute the bit position from where the value is to be retreived. */
761 lsb = qdmaChannel << 2;
763 /* Get the event Queue */
764 Uint32 temp_Var = ((Uint32)lsb) + 2U;
765 return (Uint8)(CSL_FEXTR(hModule->regs->TPCC_QDMAQNUM, (temp_Var), (Uint32)(lsb)));
766 }
768 /** ============================================================================
769 * @n@b CSL_edma3MapEventQueueToTC
770 *
771 * @b Description
772 * @n The function maps the event queue to a specific TC
773 *
774 * @b Arguments
775 * @verbatim
776 hModule Module Handle
777 eventQueue Event Queue which is to be mapped.
778 tcNum TC to which the queue is to be mapped to.
779 @endverbatim
780 *
781 * <b> Return Value </b>
782 * @n None
783 *
784 * <b> Pre Condition </b>
785 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
786 *
787 * <b> Post Condition </b>
788 * @n Event Queue is mapped to the specific TC
789 *
790 * @b Writes
791 * @n TPCC_TPCC_QUETCMAP_TCNUMQ0;TPCC_TPCC_QUETCMAP_TCNUMQ1;TPCC_TPCC_QUETCMAP_TCNUMQ2;
792 * TPCC_TPCC_QUETCMAP_TCNUMQ3;TPCC_TPCC_QUETCMAP_TCNUMQ4;TPCC_TPCC_QUETCMAP_TCNUMQ5;
793 * TPCC_TPCC_QUETCMAP_TCNUMQ6;TPCC_TPCC_QUETCMAP_TCNUMQ7
794 *
795 * @b Example
796 * @verbatim
797 CSL_Edma3Handle hModule;
798 CSL_Edma3Obj edmaObj;
799 CSL_Edma3Context context;
800 CSL_Status status;
802 // Module Initialization
803 CSL_edma3Init(&context);
805 // Module Level Open
806 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
808 // Maps Event Queue 1 to TC0
809 CSL_edma3MapEventQueueToTC(hModule, 1, 0);
810 ...
811 @endverbatim
812 * ===========================================================================
813 */
814 /* for misra warnings*/
815 static inline void CSL_edma3MapEventQueueToTC
816 (
817 CSL_Edma3Handle hModule,
818 Uint8 eventQueue,
819 Uint8 tcNum
820 );
821 static inline void CSL_edma3MapEventQueueToTC
822 (
823 CSL_Edma3Handle hModule,
824 Uint8 eventQueue,
825 Uint8 tcNum
826 )
827 {
828 Uint8 lsb;
830 /* Compute the bit position where the value is to be written. */
831 lsb = eventQueue << 2;
833 /* Write the event Queue */
834 Uint32 temp_Var = ((Uint32)lsb) + 2U;
835 CSL_FINSR(hModule->regs->TPCC_QUETCMAP, (temp_Var), (Uint32)(lsb), (Uint32)tcNum);
836 return;
837 }
839 /** ============================================================================
840 * @n@b CSL_edma3GetEventQueueToTCMapping
841 *
842 * @b Description
843 * @n The function gets the TC mapping for the specific event queue.
844 *
845 * @b Arguments
846 * @verbatim
847 hModule Module Handle
848 eventQueue Event Queue which for which the mapping is needed.
849 @endverbatim
850 *
851 * <b> Return Value </b>
852 * @n TC Number to which the event queue is mapped to
853 *
854 * <b> Pre Condition </b>
855 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
856 *
857 * <b> Post Condition </b>
858 * @n Event Queue is mapped to the specific TC
859 *
860 * @b Reads
861 * @n TPCC_TPCC_QUETCMAP_TCNUMQ0;TPCC_TPCC_QUETCMAP_TCNUMQ1;TPCC_TPCC_QUETCMAP_TCNUMQ2;
862 * TPCC_TPCC_QUETCMAP_TCNUMQ3;TPCC_TPCC_QUETCMAP_TCNUMQ4;TPCC_TPCC_QUETCMAP_TCNUMQ5;
863 * TPCC_TPCC_QUETCMAP_TCNUMQ6;TPCC_TPCC_QUETCMAP_TCNUMQ7
864 *
865 * @b Example
866 * @verbatim
867 CSL_Edma3Handle hModule;
868 CSL_Edma3Obj edmaObj;
869 CSL_Edma3Context context;
870 CSL_Status status;
871 Uint8 tcNum;
873 // Module Initialization
874 CSL_edma3Init(&context);
876 // Module Level Open
877 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
879 // Get the TC mapping for Event Queue 1
880 tcNum = CSL_edma3GetEventQueueToTCMapping(hModule, 1, 0);
881 ...
882 @endverbatim
883 * ===========================================================================
884 */
885 /* for misra warnings*/
886 static inline Uint8 CSL_edma3GetEventQueueToTCMapping
887 (
888 CSL_Edma3Handle hModule,
889 Uint8 eventQueue
890 );
891 static inline Uint8 CSL_edma3GetEventQueueToTCMapping
892 (
893 CSL_Edma3Handle hModule,
894 Uint8 eventQueue
895 )
896 {
897 Uint8 lsb;
899 /* Compute the bit position where the value is to be written. */
900 lsb = eventQueue << 2;
902 /* Get the TC Number */
903 Uint32 temp_Var = ((Uint32)lsb) + 2U;
904 return (Uint8)(CSL_FEXTR(hModule->regs->TPCC_QUETCMAP, (temp_Var), (Uint32)(lsb)));
905 }
907 /** ============================================================================
908 * @n@b CSL_edma3SetEventQueuePriority
909 *
910 * @b Description
911 * @n The function sets the priority of the specific event queue.
912 *
913 * @b Arguments
914 * @verbatim
915 hModule Module Handle
916 eventQueue Event Queue whose priority is to be configured.
917 priority Priority to be configured.
918 @endverbatim
919 *
920 * <b> Return Value </b>
921 * @n None
922 *
923 * <b> Pre Condition </b>
924 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
925 *
926 * <b> Post Condition </b>
927 * @n Event Queue is configured to the specific priority.
928 *
929 * @b Writes
930 * @n TPCC_TPCC_QUEPRI_PRIQ0;TPCC_TPCC_QUEPRI_PRIQ1;TPCC_TPCC_QUEPRI_PRIQ2;
931 * TPCC_TPCC_QUEPRI_PRIQ3;TPCC_TPCC_QUEPRI_PRIQ4;TPCC_TPCC_QUEPRI_PRIQ5;
932 * TPCC_TPCC_QUEPRI_PRIQ6;TPCC_TPCC_QUEPRI_PRIQ7
933 *
934 * @b Example
935 * @verbatim
936 CSL_Edma3Handle hModule;
937 CSL_Edma3Obj edmaObj;
938 CSL_Edma3Context context;
939 CSL_Status status;
941 // Module Initialization
942 CSL_edma3Init(&context);
944 // Module Level Open
945 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
947 // Maps Event Queue 2 to Priority 4
948 CSL_edma3SetEventQueuePriority(hModule, 2, 4);
949 ...
950 @endverbatim
951 * ===========================================================================
952 */
953 /* for misra warnings*/
954 static inline void CSL_edma3SetEventQueuePriority
955 (
956 CSL_Edma3Handle hModule,
957 Uint8 eventQueue,
958 Uint8 priority
959 );
960 static inline void CSL_edma3SetEventQueuePriority
961 (
962 CSL_Edma3Handle hModule,
963 Uint8 eventQueue,
964 Uint8 priority
965 )
966 {
967 Uint8 lsb;
969 /* Compute the bit position where the value is to be written. */
970 lsb = eventQueue << 2;
972 /* Write the priority. */
973 Uint32 temp_Var = ((Uint32)lsb) + 2U;
974 CSL_FINSR(hModule->regs->TPCC_QUEPRI, (temp_Var), (Uint32)(lsb), (Uint32)priority);
975 return;
976 }
978 /** ============================================================================
979 * @n@b CSL_edma3GetEventQueuePriority
980 *
981 * @b Description
982 * @n The function gets the priority of the specific event queue.
983 *
984 * @b Arguments
985 * @verbatim
986 hModule Module Handle
987 eventQueue Event Queue whose priority is to be retrieved.
988 @endverbatim
989 *
990 * <b> Return Value </b>
991 * @n Priority to which the Event Queue is mapped to.
992 *
993 * <b> Pre Condition </b>
994 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
995 *
996 * <b> Post Condition </b>
997 * @n Event Queue is configured to the specific priority.
998 *
999 * @b Reads
1000 * @n TPCC_TPCC_QUEPRI_PRIQ0;TPCC_TPCC_QUEPRI_PRIQ1;TPCC_TPCC_QUEPRI_PRIQ2;
1001 * TPCC_TPCC_QUEPRI_PRIQ3;TPCC_TPCC_QUEPRI_PRIQ4;TPCC_TPCC_QUEPRI_PRIQ5;
1002 * TPCC_TPCC_QUEPRI_PRIQ6;TPCC_TPCC_QUEPRI_PRIQ7
1003 *
1004 * @b Example
1005 * @verbatim
1006 CSL_Edma3Handle hModule;
1007 CSL_Edma3Obj edmaObj;
1008 CSL_Edma3Context context;
1009 CSL_Status status;
1010 Uint8 priority;
1012 // Module Initialization
1013 CSL_edma3Init(&context);
1015 // Module Level Open
1016 hModule = CSL_edma3Open(&edmaObj, CSL_EDMA3, NULL, &status);
1018 // Get the priority of Event Queue 2.
1019 priority = CSL_edma3GetEventQueuePriority(hModule, 2);
1020 ...
1021 @endverbatim
1022 * ===========================================================================
1023 */
1024 /* for misra warnings*/
1025 static inline Uint8 CSL_edma3GetEventQueuePriority
1026 (
1027 CSL_Edma3Handle hModule,
1028 Uint8 eventQueue
1029 );
1030 static inline Uint8 CSL_edma3GetEventQueuePriority
1031 (
1032 CSL_Edma3Handle hModule,
1033 Uint8 eventQueue
1034 )
1035 {
1036 Uint8 lsb;
1038 /* Compute the bit position where the value is to be written. */
1039 lsb = eventQueue << 2;
1041 /* Get the priority. */
1042 Uint32 temp_Var = ((Uint32)lsb) + 2U;
1043 return (Uint8)(CSL_FEXTR(hModule->regs->TPCC_QUEPRI, (temp_Var), (Uint32)(lsb)));
1044 }
1046 /** ============================================================================
1047 * @n@b CSL_edma3GetEventMissed
1048 *
1049 * @b Description
1050 * @n Queries all the events missed.Since there may be upto 64 EDMA
1051 * channels + upto 8 QDMA channels,this points to an array of 3,
1052 * 32 bit elements.Gets the status of the missed events.
1053 *
1054 * @b Arguments
1055 * @verbatim
1056 hModule Module Handle
1057 missedLo missed [0] - holds status from EMR
1058 missedHi missed [1] - holds status from EMRH
1059 missedQdma missed [2] - holds status from QEMR
1060 @endverbatim
1061 *
1062 * <b> Return Value </b>
1063 * @n None
1064 *
1065 * <b> Pre Condition </b>
1066 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1067 *
1068 * <b> Post Condition </b>
1069 * @n None
1070 *
1071 * @b Reads
1072 * @n TPCC_TPCC_EMR,TPCC_TPCC_EMRH,TPCC_TPCC_QEMR
1073 *
1074 * @b Example
1075 * @verbatim
1076 CSL_Edma3Handle hModule;
1077 CSL_Edma3Obj edmaObj;
1078 CSL_Edma3Context context;
1079 CSL_Status status;
1080 CSL_BitMask32 missedLo, missedHi, missedQdma;
1082 // Module Initialization
1083 CSL_edma3Init(&context);
1085 // Module Level Open
1086 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1087 ...
1088 // Get the missed events
1089 CSL_edma3GetEventMissed(hModule, &missedEdma, &missedEdmaHi, &missedQdma);
1090 ...
1091 @endverbatim
1092 * ===========================================================================
1093 */
1094 /* for misra warnings*/
1095 static inline void CSL_edma3GetEventMissed
1096 (
1097 CSL_Edma3Handle hModule,
1098 CSL_BitMask32* missedLo,
1099 CSL_BitMask32* missedHi,
1100 CSL_BitMask32* missedQdma
1101 );
1102 static inline void CSL_edma3GetEventMissed
1103 (
1104 CSL_Edma3Handle hModule,
1105 CSL_BitMask32* missedLo,
1106 CSL_BitMask32* missedHi,
1107 CSL_BitMask32* missedQdma
1108 )
1109 {
1110 /* Reading the missed Status registers */
1111 *missedLo = hModule->regs->TPCC_EMR;
1112 *missedHi = hModule->regs->TPCC_EMRH;
1113 *missedQdma = hModule->regs->TPCC_QEMR;
1114 return;
1115 }
1117 /** ============================================================================
1118 * @n@b CSL_edma3IsDMAChannelMissedEventSet
1119 *
1120 * @b Description
1121 * @n The API checks determines if there is a missed Event for a specific
1122 * DMA channel
1123 *
1124 * @b Arguments
1125 * @verbatim
1126 hModule Module Handle
1127 dmaChannel DMA Channel to be checked
1128 response This is populated by the API and returns TRUE if the
1129 event was missed else it returns FALSE.
1130 @endverbatim
1131 *
1132 * <b> Return Value </b>
1133 * @n None
1134 *
1135 * <b> Pre Condition </b>
1136 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1137 *
1138 * <b> Post Condition </b>
1139 * @n None
1140 *
1141 * @b Reads
1142 * @n TPCC_TPCC_EMR_EMR0;TPCC_TPCC_EMR_EMR1;TPCC_TPCC_EMR_EMR2;
1143 * TPCC_TPCC_EMR_EMR3;TPCC_TPCC_EMR_EMR4;TPCC_TPCC_EMR_EMR5;
1144 * TPCC_TPCC_EMR_EMR6;TPCC_TPCC_EMR_EMR7;TPCC_TPCC_EMR_EMR8;
1145 * TPCC_TPCC_EMR_EMR9;TPCC_TPCC_EMR_EMR10;TPCC_TPCC_EMR_EMR11;
1146 * TPCC_TPCC_EMR_EMR12;TPCC_TPCC_EMR_EMR13;TPCC_TPCC_EMR_EMR14;
1147 * TPCC_TPCC_EMR_EMR15;TPCC_TPCC_EMR_EMR16;TPCC_TPCC_EMR_EMR17;
1148 * TPCC_TPCC_EMR_EMR18;TPCC_TPCC_EMR_EMR19;TPCC_TPCC_EMR_EMR20;
1149 * TPCC_TPCC_EMR_EMR21;TPCC_TPCC_EMR_EMR22;TPCC_TPCC_EMR_EMR23;
1150 * TPCC_TPCC_EMR_EMR24;TPCC_TPCC_EMR_EMR25;TPCC_TPCC_EMR_EMR26;
1151 * TPCC_TPCC_EMR_EMR27;TPCC_TPCC_EMR_EMR28;TPCC_TPCC_EMR_EMR29;
1152 * TPCC_TPCC_EMR_EMR30;TPCC_TPCC_EMR_EMR31;
1153 * TPCC_TPCC_EMRH_EMR32;TPCC_TPCC_EMRH_EMR33;TPCC_TPCC_EMRH_EMR34;
1154 * TPCC_TPCC_EMRH_EMR35;TPCC_TPCC_EMRH_EMR36;TPCC_TPCC_EMRH_EMR37;
1155 * TPCC_TPCC_EMRH_EMR38;TPCC_TPCC_EMRH_EMR39;TPCC_TPCC_EMRH_EMR40;
1156 * TPCC_TPCC_EMRH_EMR41;TPCC_TPCC_EMRH_EMR42;TPCC_TPCC_EMRH_EMR43;
1157 * TPCC_TPCC_EMRH_EMR44;TPCC_TPCC_EMRH_EMR45;TPCC_TPCC_EMRH_EMR46;
1158 * TPCC_TPCC_EMRH_EMR47;TPCC_TPCC_EMRH_EMR48;TPCC_TPCC_EMRH_EMR49;
1159 * TPCC_TPCC_EMRH_EMR50;TPCC_TPCC_EMRH_EMR51;TPCC_TPCC_EMRH_EMR52;
1160 * TPCC_TPCC_EMRH_EMR53;TPCC_TPCC_EMRH_EMR54;TPCC_TPCC_EMRH_EMR55;
1161 * TPCC_TPCC_EMRH_EMR56;TPCC_TPCC_EMRH_EMR57;TPCC_TPCC_EMRH_EMR58;
1162 * TPCC_TPCC_EMRH_EMR59;TPCC_TPCC_EMRH_EMR60;TPCC_TPCC_EMRH_EMR61;
1163 * TPCC_TPCC_EMRH_EMR62;TPCC_TPCC_EMRH_EMR63;
1164 *
1165 * @b Example
1166 * @verbatim
1167 CSL_Edma3Handle hModule;
1168 CSL_Edma3Obj edmaObj;
1169 CSL_Edma3Context context;
1170 CSL_Status status;
1171 Bool missed;
1173 // Module Initialization
1174 CSL_edma3Init(&context);
1176 // Module Level Open
1177 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1178 ...
1179 // Check if DMA Channel 1 has an event missed.
1180 CSL_edma3IsDMAChannelMissedEventSet(hModule, 1, &missed);
1181 ...
1182 @endverbatim
1183 * ===========================================================================
1184 */
1185 /* for misra warnings*/
1186 static inline void CSL_edma3IsDMAChannelMissedEventSet
1187 (
1188 CSL_Edma3Handle hModule,
1189 Uint8 dmaChannel,
1190 Bool* response
1191 );
1192 static inline void CSL_edma3IsDMAChannelMissedEventSet
1193 (
1194 CSL_Edma3Handle hModule,
1195 Uint8 dmaChannel,
1196 Bool* response
1197 )
1198 {
1199 /* Determine which register needs to be looked into. */
1200 if (dmaChannel < 32U)
1201 {
1202 /* EMR: Extract the appropriate bit. */
1203 if (CSL_FEXTR(hModule->regs->TPCC_EMR, (Uint32)(dmaChannel), (Uint32)(dmaChannel)))
1204 {
1205 *response = TRUE;
1206 }
1207 else
1208 {
1209 *response = FALSE;
1210 }
1211 }
1212 else
1213 {
1214 /* EMRH: Extract the appropriate bit. */
1215 if (CSL_FEXTR(hModule->regs->TPCC_EMRH, ((Uint32)(dmaChannel)-32U), ((Uint32)(dmaChannel)-32U)))
1216 {
1217 *response = TRUE;
1218 }
1219 else
1220 {
1221 *response = FALSE;
1222 }
1223 }
1224 return;
1225 }
1227 /** ============================================================================
1228 * @n@b CSL_edma3IsQDMAChannelMissedEventSet
1229 *
1230 * @b Description
1231 * @n The API checks determines if there is a missed Event for a specific
1232 * DMA channel
1233 *
1234 * @b Arguments
1235 * @verbatim
1236 hModule Module Handle
1237 qdmaChannel QDMA Channel to be checked
1238 response This is populated by the API and returns TRUE if the
1239 event was missed else it returns FALSE.
1240 @endverbatim
1241 *
1242 * <b> Return Value </b>
1243 * @n None
1244 *
1245 * <b> Pre Condition </b>
1246 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1247 *
1248 * <b> Post Condition </b>
1249 * @n None
1250 *
1251 * @b Reads
1252 * @n TPCC_TPCC_QEMR_QEMR0;TPCC_TPCC_QEMR_QEMR1;TPCC_TPCC_QEMR_QEMR2;
1253 * TPCC_TPCC_QEMR_QEMR3;TPCC_TPCC_QEMR_QEMR4;TPCC_TPCC_QEMR_QEMR5;
1254 * TPCC_TPCC_QEMR_QEMR6;TPCC_TPCC_QEMR_QEMR7
1255 *
1256 * @b Example
1257 * @verbatim
1258 CSL_Edma3Handle hModule;
1259 CSL_Edma3Obj edmaObj;
1260 CSL_Edma3Context context;
1261 CSL_Status status;
1262 Bool missed;
1264 // Module Initialization
1265 CSL_edma3Init(&context);
1267 // Module Level Open
1268 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1269 ...
1270 // Check if DMA Channel 0 has an event missed.
1271 CSL_edma3IsQDMAChannelMissedEventSet(hModule, 0, &missed);
1272 ...
1273 @endverbatim
1274 * ===========================================================================
1275 */
1276 /* for misra warnings*/
1277 static inline void CSL_edma3IsQDMAChannelMissedEventSet
1278 (
1279 CSL_Edma3Handle hModule,
1280 Uint8 qdmaChannel,
1281 Bool* response
1282 );
1283 static inline void CSL_edma3IsQDMAChannelMissedEventSet
1284 (
1285 CSL_Edma3Handle hModule,
1286 Uint8 qdmaChannel,
1287 Bool* response
1288 )
1289 {
1290 /* Extract the appropriate QDMA Channel bit. */
1291 if (CSL_FEXTR(hModule->regs->TPCC_QEMR, (Uint32)(qdmaChannel), (Uint32)(qdmaChannel)))
1292 {
1293 *response = TRUE;
1294 }
1295 else
1296 {
1297 *response = FALSE;
1298 }
1299 return;
1300 }
1302 /** ============================================================================
1303 * @n@b CSL_edma3EventMissedClear
1304 *
1305 * @b Description
1306 * @n Clear the Event missed errors
1307 *
1308 * @b Arguments
1309 * @verbatim
1310 hModule Module Handle
1311 missedLo Lower 32 of of the Event Missed register needing to
1312 be cleared (This is the same value as EMR)
1313 missedHi Upper 32 of of the Event Missed register needing to
1314 be cleared (This is the same value as EMRH)
1315 missedQdma Bit mask of Qdma events missed needing to be cleared
1316 @endverbatim
1317 *
1318 * <b> Return Value </b>
1319 * @n None
1320 *
1321 * <b> Pre Condition </b>
1322 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1323 *
1324 * <b> Post Condition </b>
1325 * @n Clears all the missed events
1326 *
1327 * @b Writes
1328 * @n TPCC_TPCC_EMCR,TPCC_TPCC_EMCRH,TPCC_TPCC_QEMCR
1329 *
1330 * @b Example
1331 * @verbatim
1332 CSL_Edma3Handle hModule;
1333 CSL_Edma3Obj edmaObj;
1334 CSL_Edma3Context context;
1335 CSL_Status status;
1336 CSL_BitMask32 missedLo, missedHi, missedQdma;
1338 // Module Initialization
1339 CSL_edma3Init(&context);
1341 // Module Level Open
1342 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1343 ...
1344 // Get the missed events
1345 CSL_edma3GetEventMissed(hModule, &missedEdma, &missedEdmaHi, &missedQdma);
1346 ...
1347 // Clear the error
1348 CSL_edma3EventMissedClear(hModule,missedLo, missedHi,qdmamissed);
1349 ...
1350 @endverbatim
1351 * ===========================================================================
1352 */
1353 /* for misra warnings*/
1354 static inline void CSL_edma3EventsMissedClear
1355 (
1356 CSL_Edma3Handle hModule,
1357 CSL_BitMask32 missedLo,
1358 CSL_BitMask32 missedHi,
1359 CSL_BitMask32 missedQdma
1360 );
1361 static inline void CSL_edma3EventsMissedClear
1362 (
1363 CSL_Edma3Handle hModule,
1364 CSL_BitMask32 missedLo,
1365 CSL_BitMask32 missedHi,
1366 CSL_BitMask32 missedQdma
1367 )
1368 {
1369 /* Clear the reported missed events. */
1370 hModule->regs->TPCC_EMCR = missedLo;
1371 hModule->regs->TPCC_EMCRH = missedHi;
1372 hModule->regs->TPCC_QEMCR = missedQdma;
1373 return;
1374 }
1376 /** ============================================================================
1377 * @n@b CSL_edma3ClearDMAMissedEvent
1378 *
1379 * @b Description
1380 * @n The API clears the missed event for the specific DMA Channel.
1381 *
1382 * @b Arguments
1383 * @verbatim
1384 hModule Module Handle
1385 dmaChannel DMA Channel for which the event is cleared.
1386 @endverbatim
1387 *
1388 * <b> Return Value </b>
1389 * @n None
1390 *
1391 * <b> Pre Condition </b>
1392 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1393 *
1394 * <b> Post Condition </b>
1395 * @n Clears all the missed events
1396 *
1397 * @b Writes
1398 * @n TPCC_TPCC_EMCR_EMCR0;TPCC_TPCC_EMCR_EMCR1;TPCC_TPCC_EMCR_EMCR2;
1399 * TPCC_TPCC_EMCR_EMCR3;TPCC_TPCC_EMCR_EMCR4;TPCC_TPCC_EMCR_EMCR5;
1400 * TPCC_TPCC_EMCR_EMCR6;TPCC_TPCC_EMCR_EMCR7;TPCC_TPCC_EMCR_EMCR8;
1401 * TPCC_TPCC_EMCR_EMCR9;TPCC_TPCC_EMCR_EMCR10;TPCC_TPCC_EMCR_EMCR11;
1402 * TPCC_TPCC_EMCR_EMCR12;TPCC_TPCC_EMCR_EMCR13;TPCC_TPCC_EMCR_EMCR14;
1403 * TPCC_TPCC_EMCR_EMCR15;TPCC_TPCC_EMCR_EMCR16;TPCC_TPCC_EMCR_EMCR17;
1404 * TPCC_TPCC_EMCR_EMCR18;TPCC_TPCC_EMCR_EMCR19;TPCC_TPCC_EMCR_EMCR20;
1405 * TPCC_TPCC_EMCR_EMCR21;TPCC_TPCC_EMCR_EMCR22;TPCC_TPCC_EMCR_EMCR23;
1406 * TPCC_TPCC_EMCR_EMCR24;TPCC_TPCC_EMCR_EMCR25;TPCC_TPCC_EMCR_EMCR26;
1407 * TPCC_TPCC_EMCR_EMCR27;TPCC_TPCC_EMCR_EMCR28;TPCC_TPCC_EMCR_EMCR29;
1408 * TPCC_TPCC_EMCR_EMCR30;TPCC_TPCC_EMCR_EMCR31;
1409 * TPCC_TPCC_EMCRH_EMCR32;TPCC_TPCC_EMCRH_EMCR33;TPCC_TPCC_EMCRH_EMCR34
1410 * TPCC_TPCC_EMCRH_EMCR35;TPCC_TPCC_EMCRH_EMCR36;TPCC_TPCC_EMCRH_EMCR37
1411 * TPCC_TPCC_EMCRH_EMCR38;TPCC_TPCC_EMCRH_EMCR39;TPCC_TPCC_EMCRH_EMCR40
1412 * TPCC_TPCC_EMCRH_EMCR41;TPCC_TPCC_EMCRH_EMCR42;TPCC_TPCC_EMCRH_EMCR43
1413 * TPCC_TPCC_EMCRH_EMCR44;TPCC_TPCC_EMCRH_EMCR45;TPCC_TPCC_EMCRH_EMCR46
1414 * TPCC_TPCC_EMCRH_EMCR47;TPCC_TPCC_EMCRH_EMCR48;TPCC_TPCC_EMCRH_EMCR49
1415 * TPCC_TPCC_EMCRH_EMCR50;TPCC_TPCC_EMCRH_EMCR51;TPCC_TPCC_EMCRH_EMCR52
1416 * TPCC_TPCC_EMCRH_EMCR53;TPCC_TPCC_EMCRH_EMCR54;TPCC_TPCC_EMCRH_EMCR55
1417 * TPCC_TPCC_EMCRH_EMCR56;TPCC_TPCC_EMCRH_EMCR57;TPCC_TPCC_EMCRH_EMCR58
1418 * TPCC_TPCC_EMCRH_EMCR59;TPCC_TPCC_EMCRH_EMCR60;TPCC_TPCC_EMCRH_EMCR61
1419 * TPCC_TPCC_EMCRH_EMCR62;TPCC_TPCC_EMCRH_EMCR63;
1420 *
1421 * @b Example
1422 * @verbatim
1423 CSL_Edma3Handle hModule;
1424 CSL_Edma3Obj edmaObj;
1425 CSL_Edma3Context context;
1426 CSL_Status status;
1427 CSL_BitMask32 missedLo, missedHi, missedQdma;
1429 // Module Initialization
1430 CSL_edma3Init(&context);
1432 // Module Level Open
1433 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1434 ...
1435 // Clear missed DMA 1 channel event.
1436 CSL_edma3ClearDMAMissedEvent(hModule, 1);
1437 ...
1438 @endverbatim
1439 * ===========================================================================
1440 */
1441 /* for misra warnings*/
1442 static inline void CSL_edma3ClearDMAMissedEvent
1443 (
1444 CSL_Edma3Handle hModule,
1445 Uint8 dmaChannel
1446 );
1447 static inline void CSL_edma3ClearDMAMissedEvent
1448 (
1449 CSL_Edma3Handle hModule,
1450 Uint8 dmaChannel
1451 )
1452 {
1453 /* Determine which register needs to be looked into. */
1454 if (dmaChannel < 32U)
1455 {
1456 /* EMCR: Set the appropriate DMA Channel bit. */
1457 hModule->regs->TPCC_EMCR = CSL_FMKR (dmaChannel, dmaChannel, 1U);
1458 }
1459 else
1460 {
1461 /* EMCRH: Set the appropriate DMA Channel bit. */
1462 dmaChannel = dmaChannel - 32U;
1463 hModule->regs->TPCC_EMCRH = CSL_FMKR (dmaChannel, dmaChannel, 1U);
1464 }
1465 return;
1466 }
1468 /** ============================================================================
1469 * @n@b CSL_edma3ClearQDMAMissedEvent
1470 *
1471 * @b Description
1472 * @n The API clears the missed event for the specific QDMA Channel.
1473 *
1474 * @b Arguments
1475 * @verbatim
1476 hModule Module Handle
1477 qdmaChannel QDMA Channel for which the event is cleared.
1478 @endverbatim
1479 *
1480 * <b> Return Value </b>
1481 * @n None
1482 *
1483 * <b> Pre Condition </b>
1484 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1485 *
1486 * <b> Post Condition </b>
1487 * @n Clears all the missed events
1488 *
1489 * @b Writes
1490 * @n TPCC_TPCC_QEMCR_QEMCR0;TPCC_TPCC_QEMCR_QEMCR1;TPCC_TPCC_QEMCR_QEMCR2;
1491 * TPCC_TPCC_QEMCR_QEMCR3;TPCC_TPCC_QEMCR_QEMCR4;TPCC_TPCC_QEMCR_QEMCR5;
1492 * TPCC_TPCC_QEMCR_QEMCR6;TPCC_TPCC_QEMCR_QEMCR7
1493 *
1494 * @b Example
1495 * @verbatim
1496 CSL_Edma3Handle hModule;
1497 CSL_Edma3Obj edmaObj;
1498 CSL_Edma3Context context;
1499 CSL_Status status;
1500 CSL_BitMask32 missedLo, missedHi, missedQdma;
1502 // Module Initialization
1503 CSL_edma3Init(&context);
1505 // Module Level Open
1506 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1507 ...
1508 // Clear missed QDMA Channel 1 event.
1509 CSL_edma3ClearQDMAMissedEvent(hModule, 1);
1510 ...
1511 @endverbatim
1512 * ===========================================================================
1513 */
1514 /* for misra warnings*/
1515 static inline void CSL_edma3ClearQDMAMissedEvent
1516 (
1517 CSL_Edma3Handle hModule,
1518 Uint8 qdmaChannel
1519 );
1520 static inline void CSL_edma3ClearQDMAMissedEvent
1521 (
1522 CSL_Edma3Handle hModule,
1523 Uint8 qdmaChannel
1524 )
1525 {
1526 /* Set the appropriate QDMA Channel bit. */
1527 CSL_FINSR(hModule->regs->TPCC_QEMCR, qdmaChannel, qdmaChannel, 1U);
1528 return;
1529 }
1531 /** ============================================================================
1532 * @n@b CSL_edma3GetControllerError
1533 *
1534 * @b Description
1535 * @n The function gets the status of the controller error.
1536 *
1537 * @b Arguments
1538 * @verbatim
1539 hModule Module Handle
1540 ccStat Controller Error populated by this API
1541 @endverbatim
1542 *
1543 * <b> Return Value </b>
1544 * @n None
1545 *
1546 * <b> Pre Condition </b>
1547 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1548 *
1549 * <b> Post Condition </b>
1550 * @n None
1551 *
1552 * @b Reads
1553 * @n TPCC_TPCC_CCERR_QTHRXD0;TPCC_TPCC_CCERR_QTHRXD1;TPCC_TPCC_CCERR_QTHRXD2;
1554 * TPCC_TPCC_CCERR_QTHRXD3;TPCC_TPCC_CCERR_QTHRXD4;TPCC_TPCC_CCERR_QTHRXD5;
1555 * TPCC_TPCC_CCERR_QTHRXD6;TPCC_TPCC_CCERR_QTHRXD7,
1556 * TPCC_TPCC_CCERR_TCCERR
1557 *
1558 * @b Example
1559 * @verbatim
1560 CSL_Edma3Handle hModule;
1561 CSL_Edma3Obj edmaObj;
1562 CSL_Edma3Context context;
1563 CSL_Status status;
1564 CSL_Edma3CtrlErrStat ccError;
1566 // Module Initialization
1567 CSL_edma3Init(&context);
1569 // Module Level Open
1570 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1571 ...
1572 // Get Controller Error
1573 status = CSL_edma3GetControllerError(hModule,&ccError);
1574 ...
1575 @endverbatim
1576 * ===========================================================================
1577 */
1578 /* for misra warnings*/
1579 static inline void CSL_edma3GetControllerError
1580 (
1581 CSL_Edma3Handle hModule,
1582 CSL_Edma3CtrlErrStat* ccStat
1583 );
1584 static inline void CSL_edma3GetControllerError
1585 (
1586 CSL_Edma3Handle hModule,
1587 CSL_Edma3CtrlErrStat* ccStat
1588 )
1589 {
1590 /* Extract the Queue Thresholds and TCC-Error. */
1591 ccStat->error = hModule->regs->TPCC_CCERR & 0xFFU ;
1592 ccStat->exceedTcc = (Bool)(CSL_FEXT(hModule->regs->TPCC_CCERR, TPCC_TPCC_CCERR_TCCERR));
1593 return;
1594 }
1596 /** ============================================================================
1597 * @n@b CSL_edma3ClearControllerError
1598 *
1599 * @b Description
1600 * @n Channel Controller Error Fault.
1601 *
1602 * @b Arguments
1603 * @verbatim
1604 hModule Module Handle
1605 ccStat Error Status which is to be cleared.
1606 @endverbatim
1607 *
1608 * <b> Return Value </b>
1609 * @n None
1610 *
1611 * <b> Pre Condition </b>
1612 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1613 *
1614 * <b> Post Condition </b>
1615 * @n None
1616 *
1617 * @b Writes
1618 * @n TPCC_TPCC_CCERRCLR_QTHRXD0;TPCC_TPCC_CCERRCLR_QTHRXD1;TPCC_TPCC_CCERRCLR_QTHRXD2;
1619 * TPCC_TPCC_CCERRCLR_QTHRXD3;TPCC_TPCC_CCERRCLR_QTHRXD4;TPCC_TPCC_CCERRCLR_QTHRXD5;
1620 * TPCC_TPCC_CCERRCLR_QTHRXD6;TPCC_TPCC_CCERRCLR_QTHRXD7,
1621 * TPCC_TPCC_CCERR_TCCERR
1622 *
1623 * @b Example
1624 * @verbatim
1625 CSL_Edma3Handle hModule;
1626 CSL_Edma3Obj edmaObj;
1627 CSL_Edma3Context context;
1628 CSL_Status status;
1629 CSL_Edma3CtrlErrStat ccError;
1631 // Module Initialization
1632 CSL_edma3Init(&context);
1634 // Module Level Open
1635 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1636 ...
1637 // Get Controller Error
1638 status = CSL_edma3GetControllerError(hModule,&ccError);
1639 ...
1640 // Clear the error.
1641 CSL_edma3ClearControllerError(hModule,&ccError);
1642 ...
1643 @endverbatim
1644 * ===========================================================================
1645 */
1646 static inline void CSL_edma3ClearControllerError
1647 (
1648 CSL_Edma3Handle hModule,
1649 const CSL_Edma3CtrlErrStat* ccStat
1650 );
1651 static inline void CSL_edma3ClearControllerError
1652 (
1653 CSL_Edma3Handle hModule,
1654 const CSL_Edma3CtrlErrStat* ccStat
1655 )
1656 {
1657 /* Clears the errors */
1658 hModule->regs->TPCC_CCERRCLR = CSL_FMK(TPCC_TPCC_CCERR_TCCERR, (Uint32)ccStat->exceedTcc) | ccStat->error;
1659 return;
1660 }
1662 /** ============================================================================
1663 * @n@b CSL_edma3ErrorEval
1664 *
1665 * @b Description
1666 * @n This API enables enables evaluation of errros for the specified
1667 * view/shadow region.Sets EVAL bit of the EEVAL register in the Global
1668 * register space
1669 *
1670 * @b Arguments
1671 * @verbatim
1672 hModule Module Handle
1673 @endverbatim
1674 *
1675 * <b> Return Value </b>
1676 * @n None
1677 *
1678 * <b> Pre Condition </b>
1679 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1680 *
1681 * <b> Post Condition </b>
1682 * @n None
1683 *
1684 * @b Writes
1685 * @n TPCC_TPCC_EEVAL_EVAL=1
1686 *
1687 * @b Example
1688 * @verbatim
1689 CSL_Edma3Handle hModule;
1690 CSL_Edma3Obj edmaObj;
1691 CSL_Edma3Context context;
1692 CSL_Status status;
1694 // Module Initialization
1695 CSL_edma3Init(&context);
1697 // Module Level Open
1698 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1700 // Set the Error Interrupt Evaluation
1701 CSL_edma3ErrorEval(hModule);
1702 ...
1703 @endverbatim
1704 * ===========================================================================
1705 */
1706 /* for misra warnings*/
1707 static inline void CSL_edma3ErrorEval (CSL_Edma3Handle hModule);
1708 static inline void CSL_edma3ErrorEval (CSL_Edma3Handle hModule)
1709 {
1710 hModule->regs->TPCC_EEVAL = CSL_FMK(TPCC_TPCC_EEVAL_EVAL, 1U);
1711 return;
1712 }
1714 /** ============================================================================
1715 * @n@b CSL_edma3DmaRegionAccessEnable
1716 *
1717 * @b Description
1718 * @n This API enables read/write access to the shadow regions for the
1719 * specific DMA channels.
1720 *
1721 * @b Arguments
1722 * @verbatim
1723 hModule Module Handle
1724 edmaRegion Shadow Region
1725 access Region bits to be programmed
1726 drae Bitmask to be enabled in DRAE
1727 draeh Bitmask to be enabled in DRAEH
1728 @endverbatim
1729 *
1730 * <b> Return Value </b>
1731 * @n None
1732 *
1733 * <b> Pre Condition </b>
1734 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1735 *
1736 * <b> Post Condition </b>
1737 * @n None
1738 *
1739 * @b Writes
1740 * @n TPCC_TPCC_DRA_DRAE_E0=1;TPCC_TPCC_DRA_DRAE_E1=1;TPCC_TPCC_DRA_DRAE_E2=1;
1741 * TPCC_TPCC_DRA_DRAE_E3=1;TPCC_TPCC_DRA_DRAE_E4=1;TPCC_TPCC_DRA_DRAE_E5=1;
1742 * TPCC_TPCC_DRA_DRAE_E6=1;TPCC_TPCC_DRA_DRAE_E7=1;TPCC_TPCC_DRA_DRAE_E8=1;
1743 * TPCC_TPCC_DRA_DRAE_E9=1;TPCC_TPCC_DRA_DRAE_E10=1;TPCC_TPCC_DRA_DRAE_E11=1;
1744 * TPCC_TPCC_DRA_DRAE_E12=1;TPCC_TPCC_DRA_DRAE_E13=1;TPCC_TPCC_DRA_DRAE_E14=1;
1745 * TPCC_TPCC_DRA_DRAE_E15=1;TPCC_TPCC_DRA_DRAE_E16=1;TPCC_TPCC_DRA_DRAE_E17=1;
1746 * TPCC_TPCC_DRA_DRAE_E18=1;TPCC_TPCC_DRA_DRAE_E19=1;TPCC_TPCC_DRA_DRAE_E20=1;
1747 * TPCC_TPCC_DRA_DRAE_E21=1;TPCC_TPCC_DRA_DRAE_E22=1;TPCC_TPCC_DRA_DRAE_E23=1;
1748 * TPCC_TPCC_DRA_DRAE_E24=1;TPCC_TPCC_DRA_DRAE_E25=1;TPCC_TPCC_DRA_DRAE_E26=1;
1749 * TPCC_TPCC_DRA_DRAE_E27=1;TPCC_TPCC_DRA_DRAE_E28=1;TPCC_TPCC_DRA_DRAE_E29=1;
1750 * TPCC_TPCC_DRA_DRAE_E30=1;TPCC_TPCC_DRA_DRAE_E31=1;
1751 * @n TPCC_TPCC_DRA_DRAEH_E32=1;TPCC_TPCC_DRA_DRAEH_E33=1;TPCC_TPCC_DRA_DRAEH_E34=1;
1752 * TPCC_TPCC_DRA_DRAEH_E35=1;TPCC_TPCC_DRA_DRAEH_E36=1;TPCC_TPCC_DRA_DRAEH_E37=1;
1753 * TPCC_TPCC_DRA_DRAEH_E38=1;TPCC_TPCC_DRA_DRAEH_E39=1;TPCC_TPCC_DRA_DRAEH_E40=1;
1754 * TPCC_TPCC_DRA_DRAEH_E41=1;TPCC_TPCC_DRA_DRAEH_E42=1;TPCC_TPCC_DRA_DRAEH_E43=1;
1755 * TPCC_TPCC_DRA_DRAEH_E44=1;TPCC_TPCC_DRA_DRAEH_E45=1;TPCC_TPCC_DRA_DRAEH_E46=1;
1756 * TPCC_TPCC_DRA_DRAEH_E47=1;TPCC_TPCC_DRA_DRAEH_E48=1;TPCC_TPCC_DRA_DRAEH_E49=1;
1757 * TPCC_TPCC_DRA_DRAEH_E50=1;TPCC_TPCC_DRA_DRAEH_E51=1;TPCC_TPCC_DRA_DRAEH_E52=1;
1758 * TPCC_TPCC_DRA_DRAEH_E53=1;TPCC_TPCC_DRA_DRAEH_E54=1;TPCC_TPCC_DRA_DRAEH_E55=1;
1759 * TPCC_TPCC_DRA_DRAEH_E56=1;TPCC_TPCC_DRA_DRAEH_E57=1;TPCC_TPCC_DRA_DRAEH_E58=1;
1760 * TPCC_TPCC_DRA_DRAEH_E59=1;TPCC_TPCC_DRA_DRAEH_E60=1;TPCC_TPCC_DRA_DRAEH_E61=1;
1761 * TPCC_TPCC_DRA_DRAEH_E62=1;TPCC_TPCC_DRA_DRAEH_E63=1;
1762 *
1763 * @b Example
1764 * @verbatim
1765 CSL_Edma3Handle hModule;
1766 CSL_Edma3Obj edmaObj;
1767 CSL_Edma3Context context;
1768 CSL_Status status;
1770 // Module Initialization
1771 CSL_edma3Init(&context);
1773 // Module Level Open
1774 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1776 // Enable read/write access in Region 0 for DMA Channel 0 to 7
1777 CSL_edma3DmaRegionAccessEnable(hModule, 0, 0x000000FF, 0x0);
1778 ...
1779 @endverbatim
1780 * ===========================================================================
1781 */
1782 /* for misra warnings*/
1783 static inline void CSL_edma3DmaRegionAccessEnable
1784 (
1785 CSL_Edma3Handle hModule,
1786 Int edmaRegion,
1787 CSL_BitMask32 drae,
1788 CSL_BitMask32 draeh
1789 );
1790 static inline void CSL_edma3DmaRegionAccessEnable
1791 (
1792 CSL_Edma3Handle hModule,
1793 Int edmaRegion,
1794 CSL_BitMask32 drae,
1795 CSL_BitMask32 draeh
1796 )
1797 {
1798 /* Set the appropriate bit masks. */
1799 hModule->regs->TPCC_DRA[edmaRegion].DRAE |= drae;
1801 #ifdef SOC_C6678
1802 if (edmaRegion != 0) {
1803 #endif
1804 hModule->regs->TPCC_DRA[edmaRegion].DRAEH |= draeh;
1806 #ifdef SOC_C6678
1807 }
1808 #endif
1809 return;
1810 }
1812 /** ============================================================================
1813 * @n@b CSL_edma3DmaRegionAccessDisable
1814 *
1815 * @b Description
1816 * @n This API disables read/write access to the shadow regions for the
1817 * specific DMA channels.
1818 *
1819 * @b Arguments
1820 * @verbatim
1821 hModule Module Handle
1822 edmaRegion Shadow Region
1823 access Region bits to be programmed
1824 drae Bitmask to be disabled in DRAE
1825 draeh Bitmask to be disabled in DRAEH
1826 @endverbatim
1827 *
1828 * <b> Return Value </b>
1829 * @n None
1830 *
1831 * <b> Pre Condition </b>
1832 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1833 *
1834 * <b> Post Condition </b>
1835 * @n None
1836 *
1837 * @b Writes
1838 * @n TPCC_TPCC_DRA_DRAE_E0=0;TPCC_TPCC_DRA_DRAE_E1=0;TPCC_TPCC_DRA_DRAE_E2=0;
1839 * TPCC_TPCC_DRA_DRAE_E3=0;TPCC_TPCC_DRA_DRAE_E4=0;TPCC_TPCC_DRA_DRAE_E5=0;
1840 * TPCC_TPCC_DRA_DRAE_E6=0;TPCC_TPCC_DRA_DRAE_E7=0;TPCC_TPCC_DRA_DRAE_E8=0;
1841 * TPCC_TPCC_DRA_DRAE_E9=0;TPCC_TPCC_DRA_DRAE_E10=0;TPCC_TPCC_DRA_DRAE_E11=0;
1842 * TPCC_TPCC_DRA_DRAE_E12=0;TPCC_TPCC_DRA_DRAE_E13=0;TPCC_TPCC_DRA_DRAE_E14=0;
1843 * TPCC_TPCC_DRA_DRAE_E15=0;TPCC_TPCC_DRA_DRAE_E16=0;TPCC_TPCC_DRA_DRAE_E17=0;
1844 * TPCC_TPCC_DRA_DRAE_E18=0;TPCC_TPCC_DRA_DRAE_E19=0;TPCC_TPCC_DRA_DRAE_E20=0;
1845 * TPCC_TPCC_DRA_DRAE_E21=0;TPCC_TPCC_DRA_DRAE_E22=0;TPCC_TPCC_DRA_DRAE_E23=0;
1846 * TPCC_TPCC_DRA_DRAE_E24=0;TPCC_TPCC_DRA_DRAE_E25=0;TPCC_TPCC_DRA_DRAE_E26=0;
1847 * TPCC_TPCC_DRA_DRAE_E27=0;TPCC_TPCC_DRA_DRAE_E28=0;TPCC_TPCC_DRA_DRAE_E29=0;
1848 * TPCC_TPCC_DRA_DRAE_E30=0;TPCC_TPCC_DRA_DRAE_E31=0;
1849 * @n TPCC_TPCC_DRA_DRAEH_E32=0;TPCC_TPCC_DRA_DRAEH_E33=0;TPCC_TPCC_DRA_DRAEH_E34=0;
1850 * TPCC_TPCC_DRA_DRAEH_E35=0;TPCC_TPCC_DRA_DRAEH_E36=0;TPCC_TPCC_DRA_DRAEH_E37=0;
1851 * TPCC_TPCC_DRA_DRAEH_E38=0;TPCC_TPCC_DRA_DRAEH_E39=0;TPCC_TPCC_DRA_DRAEH_E40=0;
1852 * TPCC_TPCC_DRA_DRAEH_E41=0;TPCC_TPCC_DRA_DRAEH_E42=0;TPCC_TPCC_DRA_DRAEH_E43=0;
1853 * TPCC_TPCC_DRA_DRAEH_E44=0;TPCC_TPCC_DRA_DRAEH_E45=0;TPCC_TPCC_DRA_DRAEH_E46=0;
1854 * TPCC_TPCC_DRA_DRAEH_E47=0;TPCC_TPCC_DRA_DRAEH_E48=0;TPCC_TPCC_DRA_DRAEH_E49=0;
1855 * TPCC_TPCC_DRA_DRAEH_E50=0;TPCC_TPCC_DRA_DRAEH_E51=0;TPCC_TPCC_DRA_DRAEH_E52=0;
1856 * TPCC_TPCC_DRA_DRAEH_E53=0;TPCC_TPCC_DRA_DRAEH_E54=0;TPCC_TPCC_DRA_DRAEH_E55=0;
1857 * TPCC_TPCC_DRA_DRAEH_E56=0;TPCC_TPCC_DRA_DRAEH_E57=0;TPCC_TPCC_DRA_DRAEH_E58=0;
1858 * TPCC_TPCC_DRA_DRAEH_E59=0;TPCC_TPCC_DRA_DRAEH_E60=0;TPCC_TPCC_DRA_DRAEH_E61=0;
1859 * TPCC_TPCC_DRA_DRAEH_E62=0;TPCC_TPCC_DRA_DRAEH_E63=0;
1860 *
1861 * @b Example
1862 * @verbatim
1863 CSL_Edma3Handle hModule;
1864 CSL_Edma3Obj edmaObj;
1865 CSL_Edma3Context context;
1866 CSL_Status status;
1868 // Module Initialization
1869 CSL_edma3Init(&context);
1871 // Module Level Open
1872 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1874 // Disable read/write access in Region 0 for DMA Channel 0 to 7
1875 CSL_edma3DmaRegionAccessDisable(hModule, 0, 0x000000FF, 0x0);
1876 ...
1877 @endverbatim
1878 * ===========================================================================
1879 */
1880 /* for misra warnings*/
1881 static inline void CSL_edma3DmaRegionAccessDisable
1882 (
1883 CSL_Edma3Handle hModule,
1884 Int edmaRegion,
1885 CSL_BitMask32 drae,
1886 CSL_BitMask32 draeh
1887 );
1888 static inline void CSL_edma3DmaRegionAccessDisable
1889 (
1890 CSL_Edma3Handle hModule,
1891 Int edmaRegion,
1892 CSL_BitMask32 drae,
1893 CSL_BitMask32 draeh
1894 )
1895 {
1896 /* Clear the appropriate bit masks. */
1897 hModule->regs->TPCC_DRA[edmaRegion].DRAE &= ~drae;
1898 hModule->regs->TPCC_DRA[edmaRegion].DRAEH &= ~draeh;
1899 return;
1900 }
1902 /** ============================================================================
1903 * @n@b CSL_edma3QdmaRegionAccessEnable
1904 *
1905 * @b Description
1906 * @n This API enables read/write access to the shadow regions for the
1907 * specific QDMA channels.
1908 *
1909 * @b Arguments
1910 * @verbatim
1911 hModule Module Handle
1912 edmaRegion Shadow Region
1913 qrae Bitmask to be enabled in QRAE
1914 @endverbatim
1915 *
1916 * <b> Return Value </b>
1917 * @n None
1918 *
1919 * <b> Pre Condition </b>
1920 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1921 *
1922 * <b> Post Condition </b>
1923 * @n None
1924 *
1925 * @b Writes
1926 * @n TPCC_TPCC_QRAE_E0=1;TPCC_TPCC_QRAE_E1=1;TPCC_TPCC_QRAE_E2=1;
1927 * TPCC_TPCC_QRAE_E3=1;TPCC_TPCC_QRAE_E4=1;TPCC_TPCC_QRAE_E5=1;
1928 * TPCC_TPCC_QRAE_E6=1;TPCC_TPCC_QRAE_E7=1
1929 *
1930 * @b Example
1931 * @verbatim
1932 CSL_Edma3Handle hModule;
1933 CSL_Edma3Obj edmaObj;
1934 CSL_Edma3Context context;
1935 CSL_Status status;
1937 // Module Initialization
1938 CSL_edma3Init(&context);
1940 // Module Level Open
1941 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
1943 // Enable read/write access in Region 0 for QDMA 0 to 3
1944 CSL_edma3QdmaRegionAccessEnable(hModule, 0, 0x0000000F);
1946 @endverbatim
1947 * ===========================================================================
1948 */
1949 /* for misra warnings*/
1950 static inline void CSL_edma3QdmaRegionAccessEnable
1951 (
1952 CSL_Edma3Handle hModule,
1953 Int edmaRegion,
1954 CSL_BitMask32 qrae
1955 );
1956 static inline void CSL_edma3QdmaRegionAccessEnable
1957 (
1958 CSL_Edma3Handle hModule,
1959 Int edmaRegion,
1960 CSL_BitMask32 qrae
1961 )
1962 {
1963 /* Set the appropriate bit masks. */
1964 hModule->regs->TPCC_QRAE[edmaRegion] |= qrae;
1965 return;
1966 }
1968 /** ============================================================================
1969 * @n@b CSL_edma3QdmaRegionAccessDisable
1970 *
1971 * @b Description
1972 * @n This API disables read/write access to the shadow regions for the
1973 * specific QDMA channels.
1974 *
1975 * @b Arguments
1976 * @verbatim
1977 hModule Module Handle
1978 edmaRegion Shadow Region.
1979 qrae Bitmask to be enabled in QRAE
1980 @endverbatim
1981 *
1982 * <b> Return Value </b>
1983 * @n None
1984 *
1985 * <b> Pre Condition </b>
1986 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
1987 *
1988 * <b> Post Condition </b>
1989 * @n None
1990 *
1991 * @b Writes
1992 * @n TPCC_TPCC_QRAE_E0=0;TPCC_TPCC_QRAE_E1=0;TPCC_TPCC_QRAE_E2=0;
1993 * TPCC_TPCC_QRAE_E3=0;TPCC_TPCC_QRAE_E4=0;TPCC_TPCC_QRAE_E5=0;
1994 * TPCC_TPCC_QRAE_E6=0;TPCC_TPCC_QRAE_E7=0
1995 *
1996 * @b Example
1997 * @verbatim
1998 CSL_Edma3Handle hModule;
1999 CSL_Edma3Obj edmaObj;
2000 CSL_Edma3Context context;
2001 CSL_Status status;
2003 // Module Initialization
2004 CSL_edma3Init(&context);
2006 // Module Level Open
2007 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2009 // Disable read/write access in Region 0 for QDMA 0 to 3
2010 CSL_edma3QdmaRegionAccessDisable(hModule, 0, 0x0000000F);
2011 ...
2012 @endverbatim
2013 * ===========================================================================
2014 */
2015 /* for misra warnings*/
2016 static inline void CSL_edma3QdmaRegionAccessDisable
2017 (
2018 CSL_Edma3Handle hModule,
2019 Int edmaRegion,
2020 CSL_BitMask32 qrae
2021 );
2022 static inline void CSL_edma3QdmaRegionAccessDisable
2023 (
2024 CSL_Edma3Handle hModule,
2025 Int edmaRegion,
2026 CSL_BitMask32 qrae
2027 )
2028 {
2029 /* Clear the appropriate bits */
2030 hModule->regs->TPCC_QRAE[edmaRegion] &= ~qrae;
2031 return;
2032 }
2034 /** ============================================================================
2035 * @n@b CSL_edma3GetWaterMark
2036 *
2037 * @b Description
2038 * @n The function gets the Queue Watermark for the specific event queue.
2039 *
2040 * @b Arguments
2041 * @verbatim
2042 hModule Module Handle
2043 eventQueue Event queue number for which the watermark is retreived.
2044 waterMark This is populated by the API to the configured water mark
2045 @endverbatim
2046 *
2047 * <b> Return Value </b>
2048 * @n None
2049 *
2050 * <b> Pre Condition </b>
2051 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2052 *
2053 * <b> Post Condition </b>
2054 * @n None
2055 *
2056 * @b Reads
2057 * @n TPCC_TPCC_QSTAT_WM
2058 *
2059 * @b Example
2060 * @verbatim
2061 CSL_Edma3Handle hModule;
2062 CSL_Edma3Obj edmaObj;
2063 CSL_Edma3Context context;
2064 CSL_Status status;
2065 Uint8 waterMark;
2067 // Module Initialization
2068 CSL_edma3Init(&context);
2070 // Module Level Open
2071 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2073 // Get the Water Mark Queue for event queue 0
2074 CSL_edma3GetWaterMark(hModule, 0, &waterMark);
2075 ...
2076 @endverbatim
2077 * ===========================================================================
2078 */
2079 /* for misra warnings*/
2080 static inline void CSL_edma3GetWaterMark
2081 (
2082 CSL_Edma3Handle hModule,
2083 Uint8 eventQueue,
2084 Uint8* waterMark
2085 );
2086 static inline void CSL_edma3GetWaterMark
2087 (
2088 CSL_Edma3Handle hModule,
2089 Uint8 eventQueue,
2090 Uint8* waterMark
2091 )
2092 {
2093 /* Extract the watermark from the appropriate event queue. */
2094 *waterMark = CSL_FEXT(hModule->regs->TPCC_QSTAT[eventQueue], TPCC_TPCC_QSTAT0_WM);
2095 return;
2096 }
2098 /** ============================================================================
2099 * @n@b CSL_edma3GetNumberValidEntries
2100 *
2101 * @b Description
2102 * @n The function gets the Number of valid entries for the specific event queue.
2103 *
2104 * @b Arguments
2105 * @verbatim
2106 hModule Module Handle
2107 eventQueue Event queue number for which the watermark is retreived.
2108 numValidEntries This is populated by the API to the number of valid entries
2109 @endverbatim
2110 *
2111 * <b> Return Value </b>
2112 * @n None
2113 *
2114 * <b> Pre Condition </b>
2115 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2116 *
2117 * <b> Post Condition </b>
2118 * @n None
2119 *
2120 * @b Reads
2121 * @n TPCC_TPCC_QSTAT_NUMVAL
2122 *
2123 * @b Example
2124 * @verbatim
2125 CSL_Edma3Handle hModule;
2126 CSL_Edma3Obj edmaObj;
2127 CSL_Edma3Context context;
2128 CSL_Status status;
2129 Uint8 numVal;
2131 // Module Initialization
2132 CSL_edma3Init(&context);
2134 // Module Level Open
2135 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2137 // Get the Number of valid entries in event queue 0.
2138 CSL_edma3GetNumberValidEntries(hModule, 0, &numVal);
2139 ...
2140 @endverbatim
2141 * ===========================================================================
2142 */
2143 /* for misra warnings*/
2144 static inline void CSL_edma3GetNumberValidEntries
2145 (
2146 CSL_Edma3Handle hModule,
2147 Uint8 eventQueue,
2148 Uint8* numValidEntries
2149 );
2150 static inline void CSL_edma3GetNumberValidEntries
2151 (
2152 CSL_Edma3Handle hModule,
2153 Uint8 eventQueue,
2154 Uint8* numValidEntries
2155 )
2156 {
2157 /* Extract the number of valid entries from the appropriate event queue. */
2158 *numValidEntries = CSL_FEXT(hModule->regs->TPCC_QSTAT[eventQueue], TPCC_TPCC_QSTAT0_NUMVAL);
2159 return;
2160 }
2162 /** ============================================================================
2163 * @n@b CSL_edma3GetStartPointer
2164 *
2165 * @b Description
2166 * @n The function gets the Number of valid entries for the specific event queue.
2167 *
2168 * @b Arguments
2169 * @verbatim
2170 hModule Module Handle
2171 eventQueue Event queue number for which the watermark is retreived.
2172 startPtr This is populated by the API to the start pointer
2173 @endverbatim
2174 *
2175 * <b> Return Value </b>
2176 * @n None
2177 *
2178 * <b> Pre Condition </b>
2179 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2180 *
2181 * <b> Post Condition </b>
2182 * @n None
2183 *
2184 * @b Reads
2185 * @n TPCC_TPCC_QSTAT_STRPTR
2186 *
2187 * @b Example
2188 * @verbatim
2189 CSL_Edma3Handle hModule;
2190 CSL_Edma3Obj edmaObj;
2191 CSL_Edma3Context context;
2192 CSL_Status status;
2193 Uint8 startPtr;
2195 // Module Initialization
2196 CSL_edma3Init(&context);
2198 // Module Level Open
2199 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2201 // Get the Number of valid entries in event queue 0.
2202 CSL_edma3GetStartPointer(hModule, 0, &startPtr);
2203 ...
2204 @endverbatim
2205 * ===========================================================================
2206 */
2207 /* for misra warnings*/
2208 static inline void CSL_edma3GetStartPointer
2209 (
2210 CSL_Edma3Handle hModule,
2211 Uint8 eventQueue,
2212 Uint8* startPtr
2213 );
2214 static inline void CSL_edma3GetStartPointer
2215 (
2216 CSL_Edma3Handle hModule,
2217 Uint8 eventQueue,
2218 Uint8* startPtr
2219 )
2220 {
2221 /* Extract the start pointer from the appropriate event queue. */
2222 *startPtr = CSL_FEXT(hModule->regs->TPCC_QSTAT[eventQueue], TPCC_TPCC_QSTAT0_STRPTR);
2223 return;
2224 }
2226 /** ============================================================================
2227 * @n@b CSL_edma3GetThresholdExceeded
2228 *
2229 * @b Description
2230 * @n The function gets the threshold exceeded flag for the specific event queue.
2231 *
2232 * @b Arguments
2233 * @verbatim
2234 hModule Module Handle
2235 eventQueue Event queue number for which the watermark is retreived.
2236 thresholdExceeded This is populated by the API to the threshold exceeded flag
2237 for the specific event queue.
2238 @endverbatim
2239 *
2240 * <b> Return Value </b>
2241 * @n None
2242 *
2243 * <b> Pre Condition </b>
2244 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2245 *
2246 * <b> Post Condition </b>
2247 * @n None
2248 *
2249 * @b Reads
2250 * @n TPCC_TPCC_QSTAT_THRXCD
2251 *
2252 * @b Example
2253 * @verbatim
2254 CSL_Edma3Handle hModule;
2255 CSL_Edma3Obj edmaObj;
2256 CSL_Edma3Context context;
2257 CSL_Status status;
2258 Uint8 thresholdExceeded;
2260 // Module Initialization
2261 CSL_edma3Init(&context);
2263 // Module Level Open
2264 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2266 // Determine if the threshold has been exceeded or not for Queue 1
2267 CSL_edma3GetThresholdExceeded(hModule, 1, &thresholdExceeded);
2268 ...
2269 @endverbatim
2270 * ===========================================================================
2271 */
2272 /* for misra warnings*/
2273 static inline void CSL_edma3GetThresholdExceeded
2274 (
2275 CSL_Edma3Handle hModule,
2276 Uint8 eventQueue,
2277 Bool* thresholdExceeded
2278 );
2279 static inline void CSL_edma3GetThresholdExceeded
2280 (
2281 CSL_Edma3Handle hModule,
2282 Uint8 eventQueue,
2283 Bool* thresholdExceeded
2284 )
2285 {
2286 /* Extract the threshold exceeded from the appropriate event queue. */
2287 *thresholdExceeded = (Bool)CSL_FEXT(hModule->regs->TPCC_QSTAT[eventQueue], TPCC_TPCC_QSTAT0_THRXCD);
2288 return;
2289 }
2291 /** ============================================================================
2292 * @n@b CSL_edma3EventQueueThresholdSet
2293 *
2294 * @b Description
2295 * @n The function configures the queue threshold.
2296 *
2297 * @b Arguments
2298 * @verbatim
2299 hModule Module Handle
2300 eventQueue Event queue for which the threshold is configured
2301 threshold Target threshold value.
2302 @endverbatim
2303 *
2304 * <b> Return Value </b>
2305 * @n None
2306 *
2307 * <b> Pre Condition </b>
2308 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2309 *
2310 * <b> Post Condition </b>
2311 * @n None
2312 *
2313 * @b Writes
2314 * @n TPCC_TPCC_QWMTHRA_Q0;TPCC_TPCC_QWMTHRA_Q1;TPCC_TPCC_QWMTHRA_Q2;
2315 * TPCC_TPCC_QWMTHRA_Q3;
2316 * @n TPCC_TPCC_QWMTHRB_Q4;TPCC_TPCC_QWMTHRB_Q1;TPCC_TPCC_QWMTHRB_Q2;
2317 * TPCC_TPCC_QWMTHRB_Q3
2318 *
2319 * @b Example
2320 * @verbatim
2321 CSL_Edma3Handle hModule;
2322 CSL_Edma3Obj edmaObj;
2323 CSL_Edma3Context context;
2324 CSL_Status status;
2326 // Module Initialization
2327 CSL_edma3Init(&context);
2329 // Module Level Open
2330 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2332 // Set the Queue threshold for Event Queue 0 to be 9
2333 CSL_edma3EventQueueThresholdSet(hModule, 0, 9);
2334 ...
2335 @endverbatim
2336 * ===========================================================================
2337 */
2338 /* for misra warnings*/
2339 static inline void CSL_edma3EventQueueThresholdSet
2340 (
2341 CSL_Edma3Handle hModule,
2342 Uint8 eventQueue,
2343 Uint8 threshold
2344 );
2345 static inline void CSL_edma3EventQueueThresholdSet
2346 (
2347 CSL_Edma3Handle hModule,
2348 Uint8 eventQueue,
2349 Uint8 threshold
2350 )
2351 {
2352 /* Determine which register needs to be configured: QWMTHRA or QWMTHRB */
2353 if (eventQueue < 4U)
2354 {
2355 /* TPCC_QWMTHRA: Set the correct bits with the threshold value. */
2356 CSL_FINSR(hModule->regs->TPCC_QWMTHRA, (8U * eventQueue + 4U), (8U * eventQueue), (Uint32)threshold);
2357 }
2358 else
2359 {
2360 /* TPCC_QWMTHRB: Set the correct bits with the threshold value. */
2361 eventQueue -= 4U;
2362 CSL_FINSR(hModule->regs->TPCC_QWMTHRB, (8U * eventQueue + 4U), (8U * eventQueue), (Uint32)threshold);
2363 }
2364 return;
2365 }
2367 /** ============================================================================
2368 * @n@b CSL_edma3GetActivityStatus
2369 *
2370 * @b Description
2371 * @n Obtains the Channel Controller Activity Status
2372 *
2373 * @b Arguments
2374 * @verbatim
2375 hModule Module Handle
2376 activityStat Activity Status populated by this API.
2377 @endverbatim
2378 *
2379 * <b> Return Value </b>
2380 * @n None
2381 *
2382 * <b> Pre Condition </b>
2383 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2384 *
2385 * <b> Post Condition </b>
2386 * @n None
2387 *
2388 * @b Reads
2389 * @n TPCC_TPCC_CCSTAT_EVTACTV,TPCC_TPCC_CCSTAT_QEVTACTV,TPCC_TPCC_CCSTAT_TRACTV,
2390 * TPCC_TPCC_CCSTAT_ACTV,TPCC_TPCC_CCSTAT_COMP_ACTV
2391 *
2392 * @b Example
2393 * @verbatim
2395 CSL_Edma3Handle hModule;
2396 CSL_Edma3Obj edmaObj;
2397 CSL_Edma3Context context;
2398 CSL_Status status;
2399 CSL_Edma3ActivityStat activityStat;
2401 // Module Initialization
2402 CSL_edma3Init(&context);
2404 // Module Level Open
2405 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2406 ...
2407 // Get the CC activity status.
2408 CSL_edma3GetActivityStatus(hModule,&activityStat);
2409 ...
2410 @endverbatim
2411 * ===========================================================================
2412 */
2413 /* for misra warnings*/
2414 static inline void CSL_edma3GetActivityStatus
2415 (
2416 CSL_Edma3Handle hModule,
2417 CSL_Edma3ActivityStat* activityStat
2418 );
2419 static inline void CSL_edma3GetActivityStatus
2420 (
2421 CSL_Edma3Handle hModule,
2422 CSL_Edma3ActivityStat* activityStat
2423 )
2424 {
2425 Uint32 value = hModule->regs->TPCC_CCSTAT;
2427 /* Populate the activity status structure. */
2428 activityStat->evtActive = (Bool)CSL_FEXT(value, TPCC_TPCC_CCSTAT_EVTACTV);
2429 activityStat->qevtActive = (Bool)CSL_FEXT(value, TPCC_TPCC_CCSTAT_QEVTACTV);
2430 activityStat->trActive = (Bool)CSL_FEXT(value, TPCC_TPCC_CCSTAT_TRACTV);
2431 activityStat->active = (Bool)CSL_FEXT(value, TPCC_TPCC_CCSTAT_ACTV);
2432 activityStat->outstandingTcc = CSL_FEXT(value, TPCC_TPCC_CCSTAT_COMP_ACTV);
2433 activityStat->queActive = CSL_FEXTR(value, 23U,16U);
2434 return;
2435 }
2437 /** ============================================================================
2438 * @n@b CSL_edma3GetMemoryFaultError
2439 *
2440 * @b Description
2441 * @n The function gets the Controllers memory fault error and the error
2442 * attributes.
2443 *
2444 * @b Arguments
2445 * @verbatim
2446 hModule Module Handle
2447 memFault The structure is populated by this API.
2448 @endverbatim
2449 *
2450 * <b> Return Value </b>
2451 * @n None
2452 *
2453 * <b> Pre Condition </b>
2454 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2455 *
2456 * <b> Post Condition </b>
2457 * @n None
2458 *
2459 * @b Reads
2460 * @n TPCC_TPCC_MPFAR_FADDR,TPCC_TPCC_MPFSR_FID,
2461 * TPCC_TPCC_MPFSR_UXE,TPCC_TPCC_MPFSR_UWE,TPCC_TPCC_MPFSR_URE,
2462 * TPCC_TPCC_MPFSR_SXE,TPCC_TPCC_MPFSR_SWE,TPCC_TPCC_MPFSR_SRE,
2463 * TPCC_TPCC_MPFSR_SECE
2464 *
2465 * @b Example
2466 * @verbatim
2468 CSL_Edma3Handle hModule;
2469 CSL_Edma3Obj edmaObj;
2470 CSL_Edma3Context context;
2471 CSL_Status status;
2472 CSL_Edma3MemFaultStat memFault;
2474 // Module Initialization
2475 CSL_edma3Init(&context);
2477 // Module Level Open
2478 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2479 ...
2480 // Get memory protection fault
2481 CSL_edma3GetMemoryFaultError(hModule, &memFault);
2482 ...
2483 @endverbatim
2484 * ===========================================================================
2485 */
2486 /* for misra warnings*/
2487 static inline void CSL_edma3GetMemoryFaultError
2488 (
2489 CSL_Edma3Handle hModule,
2490 CSL_Edma3MemFaultStat* memFault
2491 );
2492 static inline void CSL_edma3GetMemoryFaultError
2493 (
2494 CSL_Edma3Handle hModule,
2495 CSL_Edma3MemFaultStat* memFault
2496 )
2497 {
2498 Uint32 value = hModule->regs->TPCC_MPFSR;
2500 /* Extract the memory fault address. */
2501 memFault->addr = CSL_FEXT(hModule->regs->TPCC_MPFAR, TPCC_TPCC_MPFAR_FADDR);
2503 /* Extract the fault ID */
2504 memFault->fid = CSL_FEXT(value, TPCC_TPCC_MPFSR_FID);
2506 /* Extract the error access bits. */
2507 memFault->error = CSL_FEXTR(value, 8U, 0U);
2508 return;
2509 }
2511 /** ============================================================================
2512 * @n@b CSL_edma3MemFaultClear
2513 *
2514 * @b Description
2515 * @n The function clears the memory fault.
2516 *
2517 * @b Arguments
2518 * @verbatim
2519 hModule Module Handle
2520 @endverbatim
2521 *
2522 * <b> Return Value </b>
2523 * @n None
2524 *
2525 * <b> Pre Condition </b>
2526 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2527 *
2528 * <b> Post Condition </b>
2529 * @n None
2530 *
2531 * @b Writes
2532 * @n TPCC_TPCC_MPFCR_MPFCLR=1
2533 *
2534 * @b Example
2535 * @verbatim
2536 CSL_Edma3Handle hModule;
2537 CSL_Edma3Obj edmaObj;
2538 CSL_Edma3Context context;
2539 CSL_Status status;
2541 // Module Initialization
2542 CSL_edma3Init(&context);
2544 // Module Level Open
2545 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2546 ...
2547 // Clear the memory protection fault
2548 CSL_edma3MemFaultClear(hModule);
2549 ...
2550 @endverbatim
2551 * ===========================================================================
2552 */
2553 static inline void CSL_edma3MemFaultClear (CSL_Edma3Handle hModule);
2554 static inline void CSL_edma3MemFaultClear (CSL_Edma3Handle hModule)
2555 {
2556 /* Write a 1 to clear the memory fault. */
2557 hModule->regs->TPCC_MPFCR = CSL_FMK(TPCC_TPCC_MPFCR_MPFCLR, 1U);
2558 return;
2559 }
2561 /** ============================================================================
2562 * @n@b CSL_edma3GetMemoryProtectionAttrib
2563 *
2564 * @b Description
2565 * @n The function gets the memory access/protection attributes of the
2566 * specific region.
2567 *
2568 * @b Arguments
2569 * @verbatim
2570 hModule Module Handle
2571 region Region being queried.
2572 mppa Memory Access/Protection Attributes populated by this API
2573 @endverbatim
2574 *
2575 * <b> Return Value </b>
2576 * @n None
2577 *
2578 * <b> Pre Condition </b>
2579 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2580 *
2581 * <b> Post Condition </b>
2582 * @n None
2583 *
2584 * @b Reads
2585 * @n TPCC_TPCC_MPPAG;TPCC_TPCC_MPPA
2586 *
2587 * @b Example
2588 * @verbatim
2589 CSL_Edma3Handle hModule;
2590 CSL_Edma3Obj edmaObj;
2591 CSL_Edma3Context context;
2592 CSL_Status status;
2593 CSL_BitMask32 mppa;
2595 // Module Initialization
2596 CSL_edma3Init(&context);
2598 // Module Level Open
2599 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2600 ...
2601 // Get memory protection attributes for the Global Region.
2602 CSL_edma3GetMemoryProtectionAttrib(hModule, -1, &mppa);
2603 ...
2604 // Get memory protection attributes for region 2
2605 CSL_edma3GetMemoryProtectionAttrib(hModule, 2, &mppa);
2606 ...
2607 @endverbatim
2608 * ===========================================================================
2609 */
2610 /* for misra warnings*/
2611 static inline void CSL_edma3GetMemoryProtectionAttrib
2612 (
2613 CSL_Edma3Handle hModule,
2614 Int region,
2615 CSL_BitMask32* mppa
2616 );
2617 static inline void CSL_edma3GetMemoryProtectionAttrib
2618 (
2619 CSL_Edma3Handle hModule,
2620 Int region,
2621 CSL_BitMask32* mppa
2622 )
2623 {
2624 /* Determine which region is being queried. */
2625 if (region < 0)
2626 {
2627 /* Get the Global Memory Protection Attributes */
2628 *mppa = hModule->regs->TPCC_MPPAG;
2629 }
2630 else
2631 {
2632 /* Get the Memory Protection Attributes for the specific region. */
2633 *mppa = hModule->regs->TPCC_MPPA[region];
2634 }
2635 return;
2636 }
2638 /** ============================================================================
2639 * @n@b CSL_edma3SetMemoryProtectionAttrib
2640 *
2641 * @b Description
2642 * @n This API sets the memory protection attributes for the specified region.
2643 *
2644 * @b Arguments
2645 * @verbatim
2646 hModule Module Handle
2647 region Region being configured.
2648 mpa Value to be programmed into the MPPAG/MPPA[0/1/2/../n]
2649 This is a Bitmask of the protection attributes.
2650 @endverbatim
2651 *
2652 * <b> Return Value </b>
2653 * @n None
2654 *
2655 * <b> Pre Condition </b>
2656 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2657 *
2658 * <b> Post Condition </b>
2659 * @n None
2660 *
2661 * @b Writes
2662 * @n TPCC_TPCC_MPPAG;TPCC_TPCC_MPPA
2663 *
2664 * @b Example
2665 * @verbatim
2666 CSL_Edma3Handle hModule;
2667 CSL_Edma3Obj edmaObj;
2668 CSL_Edma3Context context;
2669 CSL_Status status;
2671 // Module Initialization
2672 CSL_edma3Init(&context);
2674 // Module Level Open
2675 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2676 ...
2677 // Set the memory protection attributes of region 0.
2678 CSL_edma3SetMemoryProtectionAttrib (hModule, 0, CSL_EDMA3_MEMACCESS_UX |
2679 CSL_EDMA3_MEMACCESS_UW |
2680 CSL_EDMA3_MEMACCESS_UR |
2681 CSL_EDMA3_MEMACCESS_AID2));
2682 ...
2683 @endverbatim
2684 * ===========================================================================
2685 */
2686 /* for misra warnings*/
2687 static inline void CSL_edma3SetMemoryProtectionAttrib
2688 (
2689 CSL_Edma3Handle hModule,
2690 Int region,
2691 CSL_BitMask32 mppa
2692 );
2693 static inline void CSL_edma3SetMemoryProtectionAttrib
2694 (
2695 CSL_Edma3Handle hModule,
2696 Int region,
2697 CSL_BitMask32 mppa
2698 )
2699 {
2700 /* Determine which region is being configured.*/
2701 if (region < 0)
2702 {
2703 /* Set the Global Memory Protection Attributes */
2704 hModule->regs->TPCC_MPPAG = mppa;
2705 }
2706 else
2707 {
2708 /* Set the Memory Protection Attributes for the specific region. */
2709 hModule->regs->TPCC_MPPA[region] = mppa;
2710 }
2711 return;
2712 }
2714 /** ============================================================================
2715 * @n@b CSL_edma3IsDMAChannelEventPending
2716 *
2717 * @b Description
2718 * @n The function gets the status of the specified DMA channel i.e. if
2719 * there is a pending event on the specific channel.
2720 *
2721 * @b Arguments
2722 * @verbatim
2723 hModule Module Handle
2724 dmaChannel DMA Channel for which status is being inquired.
2725 response Place holder for whether an event is set(TRUE) or not (FALSE)
2726 @endverbatim
2727 *
2728 * <b> Return Value </b>
2729 * @n None.
2730 *
2731 * <b> Pre Condition </b>
2732 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2733 *
2734 * <b> Post Condition </b>
2735 * @n None
2736 *
2737 * @b Reads
2738 * @n TPCC_TPCC_ER_E0;TPCC_TPCC_ER_E1;TPCC_TPCC_ER_E2;TPCC_TPCC_ER_E3;
2739 * TPCC_TPCC_ER_E4;TPCC_TPCC_ER_E5;TPCC_TPCC_ER_E6;TPCC_TPCC_ER_E7;
2740 * TPCC_TPCC_ER_E8;TPCC_TPCC_ER_E9;TPCC_TPCC_ER_E10;TPCC_TPCC_ER_E11;
2741 * TPCC_TPCC_ER_E12;TPCC_TPCC_ER_E13;TPCC_TPCC_ER_E14;TPCC_TPCC_ER_E15;
2742 * TPCC_TPCC_ER_E16;TPCC_TPCC_ER_E17;TPCC_TPCC_ER_E18;TPCC_TPCC_ER_E19;
2743 * TPCC_TPCC_ER_E20;TPCC_TPCC_ER_E21;TPCC_TPCC_ER_E22;TPCC_TPCC_ER_E23;
2744 * TPCC_TPCC_ER_E24;TPCC_TPCC_ER_E25;TPCC_TPCC_ER_E26;TPCC_TPCC_ER_E27;
2745 * TPCC_TPCC_ER_E28;TPCC_TPCC_ER_E29;TPCC_TPCC_ER_E30;TPCC_TPCC_ER_E31;
2746 * @n TPCC_TPCC_ERH_E32;TPCC_TPCC_ERH_E33;TPCC_TPCC_ERH_E34;TPCC_TPCC_ERH_E35;
2747 * TPCC_TPCC_ERH_E36;TPCC_TPCC_ERH_E37;TPCC_TPCC_ERH_E38;TPCC_TPCC_ERH_E39;
2748 * TPCC_TPCC_ERH_E40;TPCC_TPCC_ERH_E41;TPCC_TPCC_ERH_E42;TPCC_TPCC_ERH_E43;
2749 * TPCC_TPCC_ERH_E44;TPCC_TPCC_ERH_E45;TPCC_TPCC_ERH_E46;TPCC_TPCC_ERH_E47;
2750 * TPCC_TPCC_ERH_E48;TPCC_TPCC_ERH_E49;TPCC_TPCC_ERH_E50;TPCC_TPCC_ERH_E51;
2751 * TPCC_TPCC_ERH_E52;TPCC_TPCC_ERH_E53;TPCC_TPCC_ERH_E54;TPCC_TPCC_ERH_E55;
2752 * TPCC_TPCC_ERH_E56;TPCC_TPCC_ERH_E57;TPCC_TPCC_ERH_E58;TPCC_TPCC_ERH_E59;
2753 * TPCC_TPCC_ERH_E60;TPCC_TPCC_ERH_E61;TPCC_TPCC_ERH_E62;TPCC_TPCC_ERH_E63;
2754 *
2755 * @b Example
2756 * @verbatim
2757 CSL_Edma3Handle hModule;
2758 CSL_Edma3Obj edmaObj;
2759 CSL_Edma3Context context;
2760 CSL_Status status;
2761 Bool dmaStatus;
2763 // Module Initialization
2764 CSL_edma3Init(&context);
2766 // Module Level Open
2767 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2768 ...
2769 // Determine if there is an event pending on DMA Channel 0.
2770 CSL_edma3IsDMAChannelEventPending(hModule, 0, &dmaStatus);
2771 ...
2772 @endverbatim
2773 * ===========================================================================
2774 */
2775 /* for misra warnings*/
2776 static inline void CSL_edma3IsDMAChannelEventPending
2777 (
2778 CSL_Edma3Handle hModule,
2779 Uint8 dmaChannel,
2780 Bool* response
2781 );
2782 static inline void CSL_edma3IsDMAChannelEventPending
2783 (
2784 CSL_Edma3Handle hModule,
2785 Uint8 dmaChannel,
2786 Bool* response
2787 )
2788 {
2789 /* Determine which register needs to be looked into. */
2790 if (dmaChannel < 32U)
2791 {
2792 /* ER: Read the specific DMA Channel bits */
2793 if (CSL_FEXTR(hModule->regs->TPCC_ER, (Uint32)dmaChannel, (Uint32)dmaChannel))
2794 {
2795 *response = TRUE;
2796 }
2797 else
2798 {
2799 *response = FALSE;
2800 }
2801 }
2802 else
2803 {
2804 /* ERH: Read the specific DMA Channel bits */
2805 if (CSL_FEXTR(hModule->regs->TPCC_ERH, ((Uint32)(dmaChannel) - 32U), ((Uint32)(dmaChannel) - 32U)))
2806 {
2807 *response = TRUE;
2808 }
2809 else
2810 {
2811 *response = FALSE;
2812 }
2813 }
2814 return;
2815 }
2817 /** ============================================================================
2818 * @n@b CSL_edma3ClearDMAChannelEvent
2819 *
2820 * @b Description
2821 * @n This API clears the event for the specific DMA channel.
2822 *
2823 * @b Arguments
2824 * @verbatim
2825 hModule Module Handle
2826 region Region (Shadow or Global)
2827 dmaChannel DMA Channel for which the event is cleared.
2828 @endverbatim
2829 *
2830 * <b> Return Value </b>
2831 * @n None
2832 *
2833 * <b> Pre Condition </b>
2834 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2835 *
2836 * <b> Post Condition </b>
2837 * @n None
2838 *
2839 * @b Writes
2840 * @n TPCC_TPCC_ECR_E0=1;TPCC_TPCC_ECR_E1=1;TPCC_TPCC_ECR_E2=1;TPCC_TPCC_ECR_E3=1;
2841 * TPCC_TPCC_ECR_E4=1;TPCC_TPCC_ECR_E5=1;TPCC_TPCC_ECR_E6=1;TPCC_TPCC_ECR_E7=1;
2842 * TPCC_TPCC_ECR_E8=1;TPCC_TPCC_ECR_E9=1;TPCC_TPCC_ECR_E10=1;TPCC_TPCC_ECR_E11=1;
2843 * TPCC_TPCC_ECR_E12=1;TPCC_TPCC_ECR_E13=1;TPCC_TPCC_ECR_E14=1;TPCC_TPCC_ECR_E15=1;
2844 * TPCC_TPCC_ECR_E16=1;TPCC_TPCC_ECR_E17=1;TPCC_TPCC_ECR_E18=1;TPCC_TPCC_ECR_E19=1;
2845 * TPCC_TPCC_ECR_E20=1;TPCC_TPCC_ECR_E21=1;TPCC_TPCC_ECR_E22=1;TPCC_TPCC_ECR_E23=1;
2846 * TPCC_TPCC_ECR_E24=1;TPCC_TPCC_ECR_E25=1;TPCC_TPCC_ECR_E26=1;TPCC_TPCC_ECR_E27=1;
2847 * TPCC_TPCC_ECR_E28=1;TPCC_TPCC_ECR_E29=1;TPCC_TPCC_ECR_E30=1;TPCC_TPCC_ECR_E31=1;
2848 * @n TPCC_TPCC_ECRH_E32=1;TPCC_TPCC_ECRH_E33=1;TPCC_TPCC_ECRH_E34=1;TPCC_TPCC_ECRH_E35=1;
2849 * TPCC_TPCC_ECRH_E36=1;TPCC_TPCC_ECRH_E37=1;TPCC_TPCC_ECRH_E38=1;TPCC_TPCC_ECRH_E39=1;
2850 * TPCC_TPCC_ECRH_E40=1;TPCC_TPCC_ECRH_E41=1;TPCC_TPCC_ECRH_E42=1;TPCC_TPCC_ECRH_E43=1;
2851 * TPCC_TPCC_ECRH_E44=1;TPCC_TPCC_ECRH_E45=1;TPCC_TPCC_ECRH_E46=1;TPCC_TPCC_ECRH_E47=1;
2852 * TPCC_TPCC_ECRH_E48=1;TPCC_TPCC_ECRH_E49=1;TPCC_TPCC_ECRH_E50=1;TPCC_TPCC_ECRH_E51=1;
2853 * TPCC_TPCC_ECRH_E52=1;TPCC_TPCC_ECRH_E53=1;TPCC_TPCC_ECRH_E54=1;TPCC_TPCC_ECRH_E55=1;
2854 * TPCC_TPCC_ECRH_E56=1;TPCC_TPCC_ECRH_E57=1;TPCC_TPCC_ECRH_E58=1;TPCC_TPCC_ECRH_E59=1;
2855 * TPCC_TPCC_ECRH_E60=1;TPCC_TPCC_ECRH_E61=1;TPCC_TPCC_ECRH_E62=1;TPCC_TPCC_ECRH_E63=1;
2856 *
2857 * @b Example
2858 * @verbatim
2859 CSL_Edma3Handle hModule;
2860 CSL_Edma3Obj edmaObj;
2861 CSL_Edma3Context context;
2862 CSL_Status status;
2863 Bool dmaStatus;
2865 // Module Initialization
2866 CSL_edma3Init(&context);
2868 // Module Level Open
2869 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2870 ...
2871 // Get DMA Channel 0 Status
2872 CSL_edma3GetDMAChannelEvent(hModule, 0, &dmaStatus);
2873 if (dmaStatus == TRUE)
2874 {
2875 // DMA Channel 0 is active...
2876 ...
2877 // Clear DMA Channel 0.
2878 CSL_edma3ClearDMAChannelEvent (hModule, CSL_EDMA3_REGION_GLOBAL, 0);
2879 }
2880 @endverbatim
2881 * ===========================================================================
2882 */
2883 /* for misra warnings*/
2884 static inline void CSL_edma3ClearDMAChannelEvent
2885 (
2886 CSL_Edma3Handle hModule,
2887 Int region,
2888 Uint8 dmaChannel
2889 );
2890 static inline void CSL_edma3ClearDMAChannelEvent
2891 (
2892 CSL_Edma3Handle hModule,
2893 Int region,
2894 Uint8 dmaChannel
2895 )
2896 {
2897 /* Determine the region for which the event is to be cleared. */
2898 if (region == CSL_EDMA3_REGION_GLOBAL)
2899 {
2900 /* Global: Determine which register needs to be looked into. */
2901 if (dmaChannel < 32U)
2902 {
2903 /* ECR: Write to the specific DMA Channel bits */
2904 CSL_FINSR(hModule->regs->TPCC_ECR, dmaChannel, dmaChannel, 1U);
2905 }
2906 else
2907 {
2908 /* ECRH: Write to the specific DMA Channel bits */
2909 CSL_FINSR(hModule->regs->TPCC_ECRH, dmaChannel - 32U, dmaChannel - 32U, 1U);
2910 }
2911 }
2912 else
2913 {
2914 /* Shadow: Determine which register needs to be looked into. */
2915 if (dmaChannel < 32U)
2916 {
2917 /* ECR: Write to the specific DMA Channel bits */
2918 CSL_FINSR(hModule->regs->SHADOW[region].TPCC_ECR, dmaChannel, dmaChannel, 1U);
2919 }
2920 else
2921 {
2922 /* ECRH: Write to the specific DMA Channel bits */
2923 CSL_FINSR(hModule->regs->SHADOW[region].TPCC_ECRH, dmaChannel - 32U, dmaChannel - 32U, 1U);
2924 }
2925 }
2926 return;
2927 }
2929 /** ============================================================================
2930 * @n@b CSL_edma3SetDMAChannelEvent
2931 *
2932 * @b Description
2933 * @n This API sets the event for the specific DMA channel.
2934 *
2935 * @b Arguments
2936 * @verbatim
2937 hModule Module Handle
2938 region Region (Shadow or Global)
2939 dmaChannel DMA Channel for which the event is to be set
2940 @endverbatim
2941 *
2942 * <b> Return Value </b>
2943 * @n None
2944 *
2945 * <b> Pre Condition </b>
2946 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
2947 *
2948 * <b> Post Condition </b>
2949 * @n None
2950 *
2951 * @b Writes
2952 * @n TPCC_TPCC_ESR_E0=1;TPCC_TPCC_ESR_E1=1;TPCC_TPCC_ESR_E2=1;TPCC_TPCC_ESR_E3=1;
2953 * TPCC_TPCC_ESR_E4=1;TPCC_TPCC_ESR_E5=1;TPCC_TPCC_ESR_E6=1;TPCC_TPCC_ESR_E7=1;
2954 * TPCC_TPCC_ESR_E8=1;TPCC_TPCC_ESR_E9=1;TPCC_TPCC_ESR_E10=1;TPCC_TPCC_ESR_E11=1;
2955 * TPCC_TPCC_ESR_E12=1;TPCC_TPCC_ESR_E13=1;TPCC_TPCC_ESR_E14=1;TPCC_TPCC_ESR_E15=1;
2956 * TPCC_TPCC_ESR_E16=1;TPCC_TPCC_ESR_E17=1;TPCC_TPCC_ESR_E18=1;TPCC_TPCC_ESR_E19=1;
2957 * TPCC_TPCC_ESR_E20=1;TPCC_TPCC_ESR_E21=1;TPCC_TPCC_ESR_E22=1;TPCC_TPCC_ESR_E23=1;
2958 * TPCC_TPCC_ESR_E24=1;TPCC_TPCC_ESR_E25=1;TPCC_TPCC_ESR_E26=1;TPCC_TPCC_ESR_E27=1;
2959 * TPCC_TPCC_ESR_E28=1;TPCC_TPCC_ESR_E29=1;TPCC_TPCC_ESR_E30=1;TPCC_TPCC_ESR_E31=1;
2960 * @n TPCC_TPCC_ESRH_E32=1;TPCC_TPCC_ESRH_E33=1;TPCC_TPCC_ESRH_E34=1;TPCC_TPCC_ESRH_E35=1;
2961 * TPCC_TPCC_ESRH_E36=1;TPCC_TPCC_ESRH_E37=1;TPCC_TPCC_ESRH_E38=1;TPCC_TPCC_ESRH_E39=1;
2962 * TPCC_TPCC_ESRH_E40=1;TPCC_TPCC_ESRH_E41=1;TPCC_TPCC_ESRH_E42=1;TPCC_TPCC_ESRH_E43=1;
2963 * TPCC_TPCC_ESRH_E44=1;TPCC_TPCC_ESRH_E45=1;TPCC_TPCC_ESRH_E46=1;TPCC_TPCC_ESRH_E47=1;
2964 * TPCC_TPCC_ESRH_E48=1;TPCC_TPCC_ESRH_E49=1;TPCC_TPCC_ESRH_E50=1;TPCC_TPCC_ESRH_E51=1;
2965 * TPCC_TPCC_ESRH_E52=1;TPCC_TPCC_ESRH_E53=1;TPCC_TPCC_ESRH_E54=1;TPCC_TPCC_ESRH_E55=1;
2966 * TPCC_TPCC_ESRH_E56=1;TPCC_TPCC_ESRH_E57=1;TPCC_TPCC_ESRH_E58=1;TPCC_TPCC_ESRH_E59=1;
2967 * TPCC_TPCC_ESRH_E60=1;TPCC_TPCC_ESRH_E61=1;TPCC_TPCC_ESRH_E62=1;TPCC_TPCC_ESRH_E63=1;
2968 *
2969 * @b Example
2970 * @verbatim
2971 CSL_Edma3Handle hModule;
2972 CSL_Edma3Obj edmaObj;
2973 CSL_Edma3Context context;
2974 CSL_Status status;
2976 // Module Initialization
2977 CSL_edma3Init(&context);
2979 // Module Level Open
2980 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
2981 ...
2982 // Set the DMA Channel 0 Event for the Global Region.
2983 CSL_edma3SetDMAChannelEvent(hModule, CSL_EDMA3_REGION_GLOBAL, 0);
2984 ...
2985 @endverbatim
2986 * ===========================================================================
2987 */
2988 /* for misra warnings*/
2989 static inline void CSL_edma3SetDMAChannelEvent
2990 (
2991 CSL_Edma3Handle hModule,
2992 Int region,
2993 Uint8 dmaChannel
2994 );
2995 static inline void CSL_edma3SetDMAChannelEvent
2996 (
2997 CSL_Edma3Handle hModule,
2998 Int region,
2999 Uint8 dmaChannel
3000 )
3001 {
3002 /* Determine the region for which the event is to be set. */
3003 if (region == CSL_EDMA3_REGION_GLOBAL)
3004 {
3005 /* Global: Determine which register needs to be looked into. */
3006 if (dmaChannel < 32U)
3007 {
3008 /* ESR: Write to the specific DMA Channel bits */
3009 hModule->regs->TPCC_ESR = CSL_FMKR(dmaChannel, dmaChannel, 1U);
3010 }
3011 else
3012 {
3013 /* ESRH: Write to the specific DMA Channel bits */
3014 hModule->regs->TPCC_ESRH = CSL_FMKR(dmaChannel - 32U, dmaChannel - 32U, 1U);
3015 }
3016 }
3017 else
3018 {
3019 /* Shadow: Determine which register needs to be looked into. */
3020 if (dmaChannel < 32U)
3021 {
3022 /* ESR: Write to the specific DMA Channel bits */
3023 hModule->regs->SHADOW[region].TPCC_ESR = CSL_FMKR(dmaChannel, dmaChannel, 1U);
3024 }
3025 else
3026 {
3027 /* ESRH: Write to the specific DMA Channel bits */
3028 hModule->regs->SHADOW[region].TPCC_ESRH = CSL_FMKR(dmaChannel - 32U, dmaChannel - 32U, 1U);
3029 }
3030 }
3031 return;
3032 }
3034 /** ============================================================================
3035 * @n@b CSL_edma3DMAChannelDisable
3036 *
3037 * @b Description
3038 * @n This API disables the specified DMA Channel.
3039 *
3040 * @b Arguments
3041 * @verbatim
3042 hModule Module Handle
3043 region Region (Shadow or Global)
3044 dmaChannel DMA Channel to be disabled.
3045 @endverbatim
3046 *
3047 * <b> Return Value </b>
3048 * @n None
3049 *
3050 * <b> Pre Condition </b>
3051 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
3052 *
3053 * <b> Post Condition </b>
3054 * @n None
3055 *
3056 * @b Writes
3057 * @n TPCC_TPCC_EECR_E0=1;TPCC_TPCC_EECR_E1=1;TPCC_TPCC_EECR_E2=1;
3058 * TPCC_TPCC_EECR_E3=1;TPCC_TPCC_EECR_E4=1;TPCC_TPCC_EECR_E5=1;
3059 * TPCC_TPCC_EECR_E6=1;TPCC_TPCC_EECR_E7=1;TPCC_TPCC_EECR_E8=1;
3060 * TPCC_TPCC_EECR_E9=1;TPCC_TPCC_EECR_E10=1;TPCC_TPCC_EECR_E11=1;
3061 * TPCC_TPCC_EECR_E12=1;TPCC_TPCC_EECR_E13=1;TPCC_TPCC_EECR_E14=1;
3062 * TPCC_TPCC_EECR_E15=1;TPCC_TPCC_EECR_E16=1;TPCC_TPCC_EECR_E17=1;
3063 * TPCC_TPCC_EECR_E18=1;TPCC_TPCC_EECR_E19=1;TPCC_TPCC_EECR_E20=1;
3064 * TPCC_TPCC_EECR_E21=1;TPCC_TPCC_EECR_E22=1;TPCC_TPCC_EECR_E23=1;
3065 * TPCC_TPCC_EECR_E24=1;TPCC_TPCC_EECR_E25=1;TPCC_TPCC_EECR_E26=1;
3066 * TPCC_TPCC_EECR_E27=1;TPCC_TPCC_EECR_E28=1;TPCC_TPCC_EECR_E29=1;
3067 * TPCC_TPCC_EECR_E30=1;TPCC_TPCC_EECR_E31=1;
3068 * @n TPCC_TPCC_EECRH_E32=1;TPCC_TPCC_EECRH_E33=1;TPCC_TPCC_EECRH_E34=1;
3069 * TPCC_TPCC_EECRH_E35=1;TPCC_TPCC_EECRH_E36=1;TPCC_TPCC_EECRH_E37=1;
3070 * TPCC_TPCC_EECRH_E38=1;TPCC_TPCC_EECRH_E39=1;TPCC_TPCC_EECRH_E40=1;
3071 * TPCC_TPCC_EECRH_E41=1;TPCC_TPCC_EECRH_E42=1;TPCC_TPCC_EECRH_E43=1;
3072 * TPCC_TPCC_EECRH_E44=1;TPCC_TPCC_EECRH_E45=1;TPCC_TPCC_EECRH_E46=1;
3073 * TPCC_TPCC_EECRH_E47=1;TPCC_TPCC_EECRH_E48=1;TPCC_TPCC_EECRH_E49=1;
3074 * TPCC_TPCC_EECRH_E50=1;TPCC_TPCC_EECRH_E51=1;TPCC_TPCC_EECRH_E52=1;
3075 * TPCC_TPCC_EECRH_E53=1;TPCC_TPCC_EECRH_E54=1;TPCC_TPCC_EECRH_E55=1;
3076 * TPCC_TPCC_EECRH_E56=1;TPCC_TPCC_EECRH_E57=1;TPCC_TPCC_EECRH_E58=1;
3077 * TPCC_TPCC_EECRH_E59=1;TPCC_TPCC_EECRH_E60=1;TPCC_TPCC_EECRH_E61=1;
3078 * TPCC_TPCC_EECRH_E62=1;TPCC_TPCC_EECRH_E63=1;
3079 *
3080 * @b Example
3081 * @verbatim
3082 CSL_Edma3Handle hModule;
3083 CSL_Edma3Obj edmaObj;
3084 CSL_Edma3Context context;
3085 CSL_Status status;
3087 // Module Initialization
3088 CSL_edma3Init(&context);
3090 // Module Level Open
3091 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
3093 // Disables DMA Channel 0
3094 CSL_edma3DMAChannelDisable(hModule, 0);
3095 ...
3096 @endverbatim
3097 * ===========================================================================
3098 */
3099 /* for misra warnings*/
3100 static inline void CSL_edma3DMAChannelDisable
3101 (
3102 CSL_Edma3Handle hModule,
3103 Int region,
3104 Uint8 dmaChannel
3105 );
3106 static inline void CSL_edma3DMAChannelDisable
3107 (
3108 CSL_Edma3Handle hModule,
3109 Int region,
3110 Uint8 dmaChannel
3111 )
3112 {
3113 /* Determine the region for which the DMA channel is to be disabled. */
3114 if (region == CSL_EDMA3_REGION_GLOBAL)
3115 {
3116 /* Global: Determine which register needs to be looked into. */
3117 if (dmaChannel < 32U)
3118 {
3119 /* EECR: Write to the specific DMA Channel bits */
3120 CSL_FINSR(hModule->regs->TPCC_EECR, dmaChannel, dmaChannel, 1U);
3121 }
3122 else
3123 {
3124 /* EECRH: Write to the specific DMA Channel bits */
3125 CSL_FINSR(hModule->regs->TPCC_EECRH, dmaChannel - 32U, dmaChannel - 32U, 1U);
3126 }
3127 }
3128 else
3129 {
3130 /* Shadow: Determine which register needs to be looked into. */
3131 if (dmaChannel < 32U)
3132 {
3133 /* EECR: Write to the specific DMA Channel bits */
3134 CSL_FINSR(hModule->regs->SHADOW[region].TPCC_EECR, dmaChannel, dmaChannel, 1U);
3135 }
3136 else
3137 {
3138 /* EECRH: Write to the specific DMA Channel bits */
3139 CSL_FINSR(hModule->regs->SHADOW[region].TPCC_EECRH, dmaChannel - 32U, dmaChannel - 32U, 1U);
3140 }
3141 }
3142 return;
3143 }
3145 /** ============================================================================
3146 * @n@b CSL_edma3DMAChannelEnable
3147 *
3148 * @b Description
3149 * @n This API enables the specified DMA Channel.
3150 *
3151 * @b Arguments
3152 * @verbatim
3153 hModule Module Handle
3154 region Region (Shadow or Global)
3155 dmaChannel DMA Channel to be enabled.
3156 @endverbatim
3157 *
3158 * <b> Return Value </b>
3159 * @n None
3160 *
3161 * <b> Pre Condition </b>
3162 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
3163 *
3164 * <b> Post Condition </b>
3165 * @n None
3166 *
3167 * @b Writes
3168 * @n TPCC_TPCC_EESR_E0=1;TPCC_TPCC_EESR_E1=1;TPCC_TPCC_EESR_E2=1;
3169 * TPCC_TPCC_EESR_E3=1;TPCC_TPCC_EESR_E4=1;TPCC_TPCC_EESR_E5=1;
3170 * TPCC_TPCC_EESR_E6=1;TPCC_TPCC_EESR_E7=1;TPCC_TPCC_EESR_E8=1;
3171 * TPCC_TPCC_EESR_E9=1;TPCC_TPCC_EESR_E10=1;TPCC_TPCC_EESR_E11=1;
3172 * TPCC_TPCC_EESR_E12=1;TPCC_TPCC_EESR_E13=1;TPCC_TPCC_EESR_E14=1;
3173 * TPCC_TPCC_EESR_E15=1;TPCC_TPCC_EESR_E16=1;TPCC_TPCC_EESR_E17=1;
3174 * TPCC_TPCC_EESR_E18=1;TPCC_TPCC_EESR_E19=1;TPCC_TPCC_EESR_E20=1;
3175 * TPCC_TPCC_EESR_E21=1;TPCC_TPCC_EESR_E22=1;TPCC_TPCC_EESR_E23=1;
3176 * TPCC_TPCC_EESR_E24=1;TPCC_TPCC_EESR_E25=1;TPCC_TPCC_EESR_E26=1;
3177 * TPCC_TPCC_EESR_E27=1;TPCC_TPCC_EESR_E28=1;TPCC_TPCC_EESR_E29=1;
3178 * TPCC_TPCC_EESR_E30=1;TPCC_TPCC_EESR_E31=1;
3179 * @n TPCC_TPCC_EESRH_E32=1;TPCC_TPCC_EESRH_E33=1;TPCC_TPCC_EESRH_E34=1;
3180 * TPCC_TPCC_EESRH_E35=1;TPCC_TPCC_EESRH_E36=1;TPCC_TPCC_EESRH_E37=1;
3181 * TPCC_TPCC_EESRH_E38=1;TPCC_TPCC_EESRH_E39=1;TPCC_TPCC_EESRH_E40=1;
3182 * TPCC_TPCC_EESRH_E41=1;TPCC_TPCC_EESRH_E42=1;TPCC_TPCC_EESRH_E43=1;
3183 * TPCC_TPCC_EESRH_E44=1;TPCC_TPCC_EESRH_E45=1;TPCC_TPCC_EESRH_E46=1;
3184 * TPCC_TPCC_EESRH_E47=1;TPCC_TPCC_EESRH_E48=1;TPCC_TPCC_EESRH_E49=1;
3185 * TPCC_TPCC_EESRH_E50=1;TPCC_TPCC_EESRH_E51=1;TPCC_TPCC_EESRH_E52=1;
3186 * TPCC_TPCC_EESRH_E53=1;TPCC_TPCC_EESRH_E54=1;TPCC_TPCC_EESRH_E55=1;
3187 * TPCC_TPCC_EESRH_E56=1;TPCC_TPCC_EESRH_E57=1;TPCC_TPCC_EESRH_E58=1;
3188 * TPCC_TPCC_EESRH_E59=1;TPCC_TPCC_EESRH_E60=1;TPCC_TPCC_EESRH_E61=1;
3189 * TPCC_TPCC_EESRH_E62=1;TPCC_TPCC_EESRH_E63=1;
3190 *
3191 * @b Example
3192 * @verbatim
3193 CSL_Edma3Handle hModule;
3194 CSL_Edma3Obj edmaObj;
3195 CSL_Edma3Context context;
3196 CSL_Status status;
3198 // Module Initialization
3199 CSL_edma3Init(&context);
3201 // Module Level Open
3202 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
3204 // Enables DMA Channel 0 for the global region.
3205 CSL_edma3DMAChannelEnable(hModule, CSL_EDMA3_REGION_GLOBAL, 0);
3206 ...
3207 @endverbatim
3208 * ===========================================================================
3209 */
3210 /* for misra warnings*/
3211 static inline void CSL_edma3DMAChannelEnable
3212 (
3213 CSL_Edma3Handle hModule,
3214 Int region,
3215 Uint8 dmaChannel
3216 );
3217 static inline void CSL_edma3DMAChannelEnable
3218 (
3219 CSL_Edma3Handle hModule,
3220 Int region,
3221 Uint8 dmaChannel
3222 )
3223 {
3224 /* Determine the region for which the DMA channel is to be enabled. */
3225 if (region == CSL_EDMA3_REGION_GLOBAL)
3226 {
3227 /* Global: Determine which register needs to be looked into. */
3228 if (dmaChannel < 32U)
3229 {
3230 /* EESR: Write to the specific DMA Channel bits */
3231 hModule->regs->TPCC_EESR = CSL_FMKR(dmaChannel, dmaChannel, 1U);
3232 }
3233 else
3234 {
3235 /* EESRH: Write to the specific DMA Channel bits */
3236 hModule->regs->TPCC_EESRH = CSL_FMKR(dmaChannel - 32U, dmaChannel - 32U, 1U);
3237 }
3238 }
3239 else
3240 {
3241 /* Shadow: Determine which register needs to be looked into. */
3242 if (dmaChannel < 32U)
3243 {
3244 /* EESR: Write to the specific DMA Channel bits */
3245 hModule->regs->SHADOW[region].TPCC_EESR = CSL_FMKR(dmaChannel, dmaChannel, 1U);
3246 }
3247 else
3248 {
3249 /* EESRH: Write to the specific DMA Channel bits */
3250 hModule->regs->SHADOW[region].TPCC_EESRH = CSL_FMKR(dmaChannel - 32U, dmaChannel - 32U, 1U);
3251 }
3252 }
3253 return;
3254 }
3256 /** ============================================================================
3257 * @n@b CSL_edma3GetDMASecondaryEvents
3258 *
3259 * @b Description
3260 * @n This API gets the DMA secondary events
3261 *
3262 * @b Arguments
3263 * @verbatim
3264 hModule Module Handle
3265 secEventLo Lower order 32 bits of secondary events populated by the API
3266 secEventHi Higher order 32 bits of secondary events populated by the API
3267 @endverbatim
3268 *
3269 * <b> Return Value </b>
3270 * @n None
3271 *
3272 * <b> Pre Condition </b>
3273 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
3274 *
3275 * <b> Post Condition </b>
3276 * @n None
3277 *
3278 * @b Reads
3279 * @n TPCC_TPCC_SER,TPCC_TPCC_SERH
3280 *
3281 * @b Example
3282 * @verbatim
3283 CSL_Edma3Handle hModule;
3284 CSL_Edma3Obj edmaObj;
3285 CSL_Edma3Context context;
3286 CSL_Status status;
3287 CSL_BitMask32 secEventLo;
3288 CSL_BitMask32 secEventHi;
3290 // Module Initialization
3291 CSL_edma3Init(&context);
3293 // Module Level Open
3294 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
3296 // Get the DMA Secondary Events.
3297 CSL_edma3GetDMASecondaryEvents(hModule, &secEventLo, &secEventHi);
3298 ...
3299 @endverbatim
3300 * ===========================================================================
3301 */
3302 /* for misra warnings*/
3303 static inline void CSL_edma3GetDMASecondaryEvents
3304 (
3305 CSL_Edma3Handle hModule,
3306 CSL_BitMask32* secEventLo,
3307 CSL_BitMask32* secEventHi
3308 );
3309 static inline void CSL_edma3GetDMASecondaryEvents
3310 (
3311 CSL_Edma3Handle hModule,
3312 CSL_BitMask32* secEventLo,
3313 CSL_BitMask32* secEventHi
3314 )
3315 {
3316 /* Read the Secondary Events */
3317 *secEventLo = hModule->regs->TPCC_SER;
3318 *secEventHi = hModule->regs->TPCC_SERH;
3319 return;
3320 }
3322 /** ============================================================================
3323 * @n@b CSL_edma3IsDMAChannelSecondaryEventSet
3324 *
3325 * @b Description
3326 * @n This API is used to determine if the secondary Event for a specific DMA
3327 * channel is set or not?
3328 *
3329 * @b Arguments
3330 * @verbatim
3331 hModule Module Handle
3332 dmaChannel DMA Channel for which secondary Events are being checked
3333 response Status of the check populated by the API (TRUE if event
3334 is missed else FALSE)
3335 @endverbatim
3336 *
3337 * <b> Return Value </b>
3338 * @n None
3339 *
3340 * <b> Pre Condition </b>
3341 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
3342 *
3343 * <b> Post Condition </b>
3344 * @n None
3345 *
3346 * @b Reads
3347 * @n TPCC_TPCC_SER_SER0;TPCC_TPCC_SER_SER1;TPCC_TPCC_SER_SER2;
3348 * TPCC_TPCC_SER_SER3;TPCC_TPCC_SER_SER4;TPCC_TPCC_SER_SER5;
3349 * TPCC_TPCC_SER_SER6;TPCC_TPCC_SER_SER7;TPCC_TPCC_SER_SER8;
3350 * TPCC_TPCC_SER_SER9;TPCC_TPCC_SER_SER10;TPCC_TPCC_SER_SER11;
3351 * TPCC_TPCC_SER_SER12;TPCC_TPCC_SER_SER13;TPCC_TPCC_SER_SER14;
3352 * TPCC_TPCC_SER_SER15;TPCC_TPCC_SER_SER16;TPCC_TPCC_SER_SER17;
3353 * TPCC_TPCC_SER_SER18;TPCC_TPCC_SER_SER19;TPCC_TPCC_SER_SER20;
3354 * TPCC_TPCC_SER_SER21;TPCC_TPCC_SER_SER22;TPCC_TPCC_SER_SER23;
3355 * TPCC_TPCC_SER_SER24;TPCC_TPCC_SER_SER25;TPCC_TPCC_SER_SER26;
3356 * TPCC_TPCC_SER_SER27;TPCC_TPCC_SER_SER28;TPCC_TPCC_SER_SER29;
3357 * TPCC_TPCC_SER_SER30;TPCC_TPCC_SER_SER31;
3358 * @n TPCC_TPCC_SERH_SER32;TPCC_TPCC_SERH_SER33;TPCC_TPCC_SERH_SER34;
3359 * TPCC_TPCC_SERH_SER35;TPCC_TPCC_SERH_SER36;TPCC_TPCC_SERH_SER37;
3360 * TPCC_TPCC_SERH_SER38;TPCC_TPCC_SERH_SER39;TPCC_TPCC_SERH_SER40;
3361 * TPCC_TPCC_SERH_SER41;TPCC_TPCC_SERH_SER42;TPCC_TPCC_SERH_SER43;
3362 * TPCC_TPCC_SERH_SER44;TPCC_TPCC_SERH_SER45;TPCC_TPCC_SERH_SER46;
3363 * TPCC_TPCC_SERH_SER47;TPCC_TPCC_SERH_SER48;TPCC_TPCC_SERH_SER49;
3364 * TPCC_TPCC_SERH_SER50;TPCC_TPCC_SERH_SER51;TPCC_TPCC_SERH_SER52;
3365 * TPCC_TPCC_SERH_SER53;TPCC_TPCC_SERH_SER54;TPCC_TPCC_SERH_SER55;
3366 * TPCC_TPCC_SERH_SER56;TPCC_TPCC_SERH_SER57;TPCC_TPCC_SERH_SER58;
3367 * TPCC_TPCC_SERH_SER59;TPCC_TPCC_SERH_SER60;TPCC_TPCC_SERH_SER61;
3368 * TPCC_TPCC_SERH_SER62;TPCC_TPCC_SERH_SER63;
3369 *
3370 * @b Example
3371 * @verbatim
3372 CSL_Edma3Handle hModule;
3373 CSL_Edma3Obj edmaObj;
3374 CSL_Edma3Context context;
3375 CSL_Status status;
3376 Bool response;
3378 // Module Initialization
3379 CSL_edma3Init(&context);
3381 // Module Level Open
3382 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
3384 // Check if the DMA Channel 1 Secondary Event is set or not?
3385 CSL_edma3IsDMAChannelSecondaryEventSet(hModule, 1, &response);
3386 ...
3387 @endverbatim
3388 * ===========================================================================
3389 */
3390 /* for misra warnings*/
3391 static inline void CSL_edma3IsDMAChannelSecondaryEventSet
3392 (
3393 CSL_Edma3Handle hModule,
3394 Uint8 dmaChannel,
3395 Bool* response
3396 );
3397 static inline void CSL_edma3IsDMAChannelSecondaryEventSet
3398 (
3399 CSL_Edma3Handle hModule,
3400 Uint8 dmaChannel,
3401 Bool* response
3402 )
3403 {
3404 /* Determine which register needs to be looked into. */
3405 if (dmaChannel < 32U)
3406 {
3407 /* EMR: Extract the appropriate bit. */
3408 if (CSL_FEXTR(hModule->regs->TPCC_SER, (Uint32)dmaChannel, (Uint32)dmaChannel))
3409 {
3410 *response = TRUE;
3411 }
3412 else
3413 {
3414 *response = FALSE;
3415 }
3416 }
3417 else
3418 {
3419 /* EMRH: Extract the appropriate bit. */
3420 if (CSL_FEXTR(hModule->regs->TPCC_SERH, ((Uint32)(dmaChannel)-32U), ((Uint32)(dmaChannel)-32U)))
3421 {
3422 *response = TRUE;
3423 }
3424 else
3425 {
3426 *response = FALSE;
3427 }
3428 }
3429 return;
3430 }
3432 /** ============================================================================
3433 * @n@b CSL_edma3ClearDMASecondaryEvents
3434 *
3435 * @b Description
3436 * @n This API clears the DMA secondary events
3437 *
3438 * @b Arguments
3439 * @verbatim
3440 hModule Module Handle
3441 secEventLo Lower order 32 bits of secondary events to be cleared
3442 secEventHi Higher order 32 bits of secondary events to be cleared
3443 @endverbatim
3444 *
3445 * <b> Return Value </b>
3446 * @n None
3447 *
3448 * <b> Pre Condition </b>
3449 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
3450 *
3451 * <b> Post Condition </b>
3452 * @n None
3453 *
3454 * @b Writes
3455 * @n TPCC_TPCC_SECR,TPCC_TPCC_SECRH
3456 *
3457 * @b Example
3458 * @verbatim
3459 CSL_Edma3Handle hModule;
3460 CSL_Edma3Obj edmaObj;
3461 CSL_Edma3Context context;
3462 CSL_Status status;
3463 CSL_BitMask32 secEventLo;
3464 CSL_BitMask32 secEventHi;
3466 // Module Initialization
3467 CSL_edma3Init(&context);
3469 // Module Level Open
3470 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
3472 // Get the DMA Secondary Events.
3473 CSL_edma3GetDMASecondaryEvents(hModule, &secEventLo, &secEventHi);
3474 ...
3475 // Clear the DMA Secondary Events
3476 CSL_edma3ClearDMASecondaryEvents(hModule, secEventLo, secEventHi);
3477 @endverbatim
3478 * ===========================================================================
3479 */
3480 /* for misra warnings*/
3481 static inline void CSL_edma3ClearDMASecondaryEvents
3482 (
3483 CSL_Edma3Handle hModule,
3484 CSL_BitMask32 secEventLo,
3485 CSL_BitMask32 secEventHi
3486 );
3487 static inline void CSL_edma3ClearDMASecondaryEvents
3488 (
3489 CSL_Edma3Handle hModule,
3490 CSL_BitMask32 secEventLo,
3491 CSL_BitMask32 secEventHi
3492 )
3493 {
3494 /* Clear the Secondary Events */
3495 hModule->regs->TPCC_SECR = secEventLo;
3496 hModule->regs->TPCC_SECRH = secEventHi;
3497 return;
3498 }
3500 /** ============================================================================
3501 * @n@b CSL_edma3ClearDMAChannelSecondaryEvents
3502 *
3503 * @b Description
3504 * @n This API clears the DMA Secondary Event for a specific DMA Channel.
3505 *
3506 * @b Arguments
3507 * @verbatim
3508 hModule Module Handle
3509 qdmaChannel DMA Channel for which the secondary event is to be cleared.
3510 @endverbatim
3511 *
3512 * <b> Return Value </b>
3513 * @n None
3514 *
3515 * <b> Pre Condition </b>
3516 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
3517 *
3518 * <b> Post Condition </b>
3519 * @n None
3520 *
3521 * @b Writes
3522 * @n TPCC_TPCC_SECR_SECR0=1;TPCC_TPCC_SECR_SECR1=1;TPCC_TPCC_SECR_SECR2=1;
3523 * TPCC_TPCC_SECR_SECR3=1;TPCC_TPCC_SECR_SECR4=1;TPCC_TPCC_SECR_SECR5=1;
3524 * TPCC_TPCC_SECR_SECR6=1;TPCC_TPCC_SECR_SECR7=1;TPCC_TPCC_SECR_SECR8=1;
3525 * TPCC_TPCC_SECR_SECR9=1;TPCC_TPCC_SECR_SECR10=1;TPCC_TPCC_SECR_SECR11=1;
3526 * TPCC_TPCC_SECR_SECR12=1;TPCC_TPCC_SECR_SECR13=1;TPCC_TPCC_SECR_SECR14=1;
3527 * TPCC_TPCC_SECR_SECR15=1;TPCC_TPCC_SECR_SECR16=1;TPCC_TPCC_SECR_SECR17=1;
3528 * TPCC_TPCC_SECR_SECR18=1;TPCC_TPCC_SECR_SECR19=1;TPCC_TPCC_SECR_SECR20=1;
3529 * TPCC_TPCC_SECR_SECR21=1;TPCC_TPCC_SECR_SECR22=1;TPCC_TPCC_SECR_SECR23=1;
3530 * TPCC_TPCC_SECR_SECR24=1;TPCC_TPCC_SECR_SECR25=1;TPCC_TPCC_SECR_SECR26=1;
3531 * TPCC_TPCC_SECR_SECR27=1;TPCC_TPCC_SECR_SECR28=1;TPCC_TPCC_SECR_SECR29=1;
3532 * TPCC_TPCC_SECR_SECR30=1;TPCC_TPCC_SECR_SECR31=1;
3533 * @n TPCC_TPCC_SECRH_SECR32=1;TPCC_TPCC_SECRH_SECR33=1;TPCC_TPCC_SECRH_SECR34=1;
3534 * TPCC_TPCC_SECRH_SECR35=1;TPCC_TPCC_SECRH_SECR36=1;TPCC_TPCC_SECRH_SECR37=1;
3535 * TPCC_TPCC_SECRH_SECR38=1;TPCC_TPCC_SECRH_SECR39=1;TPCC_TPCC_SECRH_SECR40=1;
3536 * TPCC_TPCC_SECRH_SECR41=1;TPCC_TPCC_SECRH_SECR42=1;TPCC_TPCC_SECRH_SECR43=1;
3537 * TPCC_TPCC_SECRH_SECR44=1;TPCC_TPCC_SECRH_SECR45=1;TPCC_TPCC_SECRH_SECR46=1;
3538 * TPCC_TPCC_SECRH_SECR47=1;TPCC_TPCC_SECRH_SECR48=1;TPCC_TPCC_SECRH_SECR49=1;
3539 * TPCC_TPCC_SECRH_SECR50=1;TPCC_TPCC_SECRH_SECR51=1;TPCC_TPCC_SECRH_SECR52=1;
3540 * TPCC_TPCC_SECRH_SECR53=1;TPCC_TPCC_SECRH_SECR54=1;TPCC_TPCC_SECRH_SECR55=1;
3541 * TPCC_TPCC_SECRH_SECR56=1;TPCC_TPCC_SECRH_SECR57=1;TPCC_TPCC_SECRH_SECR58=1;
3542 * TPCC_TPCC_SECRH_SECR59=1;TPCC_TPCC_SECRH_SECR60=1;TPCC_TPCC_SECRH_SECR61=1;
3543 * TPCC_TPCC_SECRH_SECR62=1;TPCC_TPCC_SECRH_SECR63=1;
3544 *
3545 * @b Example
3546 * @verbatim
3547 CSL_Edma3Handle hModule;
3548 CSL_Edma3Obj edmaObj;
3549 CSL_Edma3Context context;
3550 Uint32 qdmaSecEvent;
3552 // Module Initialization
3553 CSL_edma3Init(&context);
3555 // Module Level Open
3556 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
3557 ...
3558 // Clear the DMA Secondary Event for DMA channel 1
3559 CSL_edma3ClearDMAChannelSecondaryEvents(hModule, 1);
3560 ...
3561 @endverbatim
3562 * ===========================================================================
3563 */
3564 /* for misra warnings*/
3565 static inline void CSL_edma3ClearDMAChannelSecondaryEvents
3566 (
3567 CSL_Edma3Handle hModule,
3568 Uint8 dmaChannel
3569 );
3570 static inline void CSL_edma3ClearDMAChannelSecondaryEvents
3571 (
3572 CSL_Edma3Handle hModule,
3573 Uint8 dmaChannel
3574 )
3575 {
3576 /* Determine which register needs to be looked into. */
3577 if (dmaChannel < 32U)
3578 {
3579 /* SECR: Write to the appropriate channel. */
3580 hModule->regs->TPCC_SECR = CSL_FMKR (dmaChannel, dmaChannel, 1U);
3581 }
3582 else
3583 {
3584 /* SECRH: Write to the appropriate channel. */
3585 dmaChannel = dmaChannel - 32U;
3586 hModule->regs->TPCC_SECRH = CSL_FMKR (dmaChannel, dmaChannel, 1U);
3587 }
3588 }
3590 /** ============================================================================
3591 * @n@b CSL_edma3InterruptLoDisable
3592 *
3593 * @b Description
3594 * @n The API disables the specified low interrupt Number.
3595 *
3596 * @b Arguments
3597 * @verbatim
3598 hModule Module Handle
3599 region Region (Shadow or Global)
3600 intrLo Interrupt 0-31 (BitMask32) to be disabled
3601 @endverbatim
3602 *
3603 * <b> Return Value </b>
3604 * @n None
3605 *
3606 * <b> Pre Condition </b>
3607 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
3608 *
3609 * <b> Post Condition </b>
3610 * @n None
3611 *
3612 * @b Writes
3613 * @n TPCC_TPCC_IECR_IECR0=1;TPCC_TPCC_IECR_IECR1=1;TPCC_TPCC_IECR_IECR2=1;
3614 * TPCC_TPCC_IECR_IECR3=1;TPCC_TPCC_IECR_IECR4=1;TPCC_TPCC_IECR_IECR5=1;
3615 * TPCC_TPCC_IECR_IECR6=1;TPCC_TPCC_IECR_IECR7=1;TPCC_TPCC_IECR_IECR8=1;
3616 * TPCC_TPCC_IECR_IECR9=1;TPCC_TPCC_IECR_IECR10=1;TPCC_TPCC_IECR_IECR11=1;
3617 * TPCC_TPCC_IECR_IECR12=1;TPCC_TPCC_IECR_IECR13=1;TPCC_TPCC_IECR_IECR14=1;
3618 * TPCC_TPCC_IECR_IECR15=1;TPCC_TPCC_IECR_IECR16=1;TPCC_TPCC_IECR_IECR17=1;
3619 * TPCC_TPCC_IECR_IECR18=1;TPCC_TPCC_IECR_IECR19=1;TPCC_TPCC_IECR_IECR20=1;
3620 * TPCC_TPCC_IECR_IECR21=1;TPCC_TPCC_IECR_IECR22=1;TPCC_TPCC_IECR_IECR23=1;
3621 * TPCC_TPCC_IECR_IECR24=1;TPCC_TPCC_IECR_IECR25=1;TPCC_TPCC_IECR_IECR26=1;
3622 * TPCC_TPCC_IECR_IECR27=1;TPCC_TPCC_IECR_IECR28=1;TPCC_TPCC_IECR_IECR29=1;
3623 * TPCC_TPCC_IECR_IECR30=1;TPCC_TPCC_IECR_IECR31=1;
3624 *
3625 * @b Example
3626 * @verbatim
3627 CSL_Edma3Handle hModule;
3628 CSL_Edma3Obj edmaObj;
3629 CSL_Edma3Context context;
3630 CSL_Status status;
3632 // Module Initialization
3633 CSL_edma3Init(&context);
3635 // Module Level Open
3636 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
3638 // Interrupts 5-7 disabled for Global Region.
3639 CSL_edma3InterruptLoDisable(hModule, CSL_EDMA3_REGION_GLOBAL, 0x000000E0);
3640 ...
3641 @endverbatim
3642 * ===========================================================================
3643 */
3644 /* for misra warnings*/
3645 static inline void CSL_edma3InterruptLoDisable
3646 (
3647 CSL_Edma3Handle hModule,
3648 Int region,
3649 CSL_BitMask32 intrLo
3650 );
3651 static inline void CSL_edma3InterruptLoDisable
3652 (
3653 CSL_Edma3Handle hModule,
3654 Int region,
3655 CSL_BitMask32 intrLo
3656 )
3657 {
3658 /* Disable the interrupts depending on the region. */
3659 if (region != CSL_EDMA3_REGION_GLOBAL)
3660 {
3661 /* Shadow Region */
3662 hModule->regs->SHADOW[region].TPCC_IECR |= intrLo;
3663 }
3664 else
3665 {
3666 /* Global Region */
3667 hModule->regs->TPCC_IECR |= intrLo;
3668 }
3669 return;
3670 }
3672 /** ============================================================================
3673 * @n@b CSL_edma3InterruptHiDisable
3674 *
3675 * @b Description
3676 * @n The API disables the specified high interrupt Number.
3677 *
3678 * @b Arguments
3679 * @verbatim
3680 hModule Module Handle
3681 region Region (Shadow or Global)
3682 intrHi Interrupt 32-63 (BitMask32) to be disabled
3683 @endverbatim
3684 *
3685 * <b> Return Value </b>
3686 * @n None
3687 *
3688 * <b> Pre Condition </b>
3689 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
3690 *
3691 * <b> Post Condition </b>
3692 * @n None
3693 *
3694 * @b Writes
3695 * @n TPCC_TPCC_IECRH_IECR32=1;TPCC_TPCC_IECRH_IECR33=1;TPCC_TPCC_IECRH_IECR34=1;
3696 * TPCC_TPCC_IECRH_IECR35=1;TPCC_TPCC_IECRH_IECR36=1;TPCC_TPCC_IECRH_IECR37=1;
3697 * TPCC_TPCC_IECRH_IECR38=1;TPCC_TPCC_IECRH_IECR39=1;TPCC_TPCC_IECRH_IECR40=1;
3698 * TPCC_TPCC_IECRH_IECR41=1;TPCC_TPCC_IECRH_IECR42=1;TPCC_TPCC_IECRH_IECR43=1;
3699 * TPCC_TPCC_IECRH_IECR44=1;TPCC_TPCC_IECRH_IECR45=1;TPCC_TPCC_IECRH_IECR46=1;
3700 * TPCC_TPCC_IECRH_IECR47=1;TPCC_TPCC_IECRH_IECR48=1;TPCC_TPCC_IECRH_IECR49=1;
3701 * TPCC_TPCC_IECRH_IECR50=1;TPCC_TPCC_IECRH_IECR51=1;TPCC_TPCC_IECRH_IECR52=1;
3702 * TPCC_TPCC_IECRH_IECR53=1;TPCC_TPCC_IECRH_IECR54=1;TPCC_TPCC_IECRH_IECR55=1;
3703 * TPCC_TPCC_IECRH_IECR56=1;TPCC_TPCC_IECRH_IECR57=1;TPCC_TPCC_IECRH_IECR58=1;
3704 * TPCC_TPCC_IECRH_IECR59=1;TPCC_TPCC_IECRH_IECR60=1;TPCC_TPCC_IECRH_IECR61=1;
3705 * TPCC_TPCC_IECRH_IECR62=1;TPCC_TPCC_IECRH_IECR63=1;
3706 *
3707 * @b Example
3708 * @verbatim
3709 CSL_Edma3Handle hModule;
3710 CSL_Edma3Obj edmaObj;
3711 CSL_Edma3Context context;
3712 CSL_Status status;
3714 // Module Initialization
3715 CSL_edma3Init(&context);
3717 // Module Level Open
3718 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
3720 // Interrupts 32 disabled for Global Region.
3721 CSL_edma3InterruptHiDisable(hModule, CSL_EDMA3_REGION_GLOBAL, 0x1);
3722 ...
3723 @endverbatim
3724 * ===========================================================================
3725 */
3726 /* for misra warnings*/
3727 static inline void CSL_edma3InterruptHiDisable
3728 (
3729 CSL_Edma3Handle hModule,
3730 Int region,
3731 CSL_BitMask32 intrHi
3732 );
3733 static inline void CSL_edma3InterruptHiDisable
3734 (
3735 CSL_Edma3Handle hModule,
3736 Int region,
3737 CSL_BitMask32 intrHi
3738 )
3739 {
3740 /* Disable the interrupts depending on the region. */
3741 if (region != CSL_EDMA3_REGION_GLOBAL)
3742 {
3743 /* Shadow Region */
3744 hModule->regs->SHADOW[region].TPCC_IECRH |= intrHi;
3745 }
3746 else
3747 {
3748 /* Global Region */
3749 hModule->regs->TPCC_IECRH |= intrHi;
3750 }
3751 return;
3752 }
3754 /** ============================================================================
3755 * @n@b CSL_edma3InterruptLoEnable
3756 *
3757 * @b Description
3758 * @n The API enables the specific lower interrupts
3759 *
3760 * @b Arguments
3761 * @verbatim
3762 hModule Module Handle
3763 region Region (Shadow or Global)
3764 intrLo Interrupt 0-31 (BitMask32) to be enabled
3765 @endverbatim
3766 *
3767 * <b> Return Value </b>
3768 * @n None
3769 *
3770 * <b> Pre Condition </b>
3771 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
3772 *
3773 * <b> Post Condition </b>
3774 * @n None
3775 *
3776 * @b Writes
3777 * @n TPCC_TPCC_IESR_IESR0=1;TPCC_TPCC_IESR_IESR1=1;TPCC_TPCC_IESR_IESR2=1;
3778 * TPCC_TPCC_IESR_IESR3=1;TPCC_TPCC_IESR_IESR4=1;TPCC_TPCC_IESR_IESR5=1;
3779 * TPCC_TPCC_IESR_IESR6=1;TPCC_TPCC_IESR_IESR7=1;TPCC_TPCC_IESR_IESR8=1;
3780 * TPCC_TPCC_IESR_IESR9=1;TPCC_TPCC_IESR_IESR10=1;TPCC_TPCC_IESR_IESR11=1;
3781 * TPCC_TPCC_IESR_IESR12=1;TPCC_TPCC_IESR_IESR13=1;TPCC_TPCC_IESR_IESR14=1;
3782 * TPCC_TPCC_IESR_IESR15=1;TPCC_TPCC_IESR_IESR16=1;TPCC_TPCC_IESR_IESR17=1;
3783 * TPCC_TPCC_IESR_IESR18=1;TPCC_TPCC_IESR_IESR19=1;TPCC_TPCC_IESR_IESR20=1;
3784 * TPCC_TPCC_IESR_IESR21=1;TPCC_TPCC_IESR_IESR22=1;TPCC_TPCC_IESR_IESR23=1;
3785 * TPCC_TPCC_IESR_IESR24=1;TPCC_TPCC_IESR_IESR25=1;TPCC_TPCC_IESR_IESR26=1;
3786 * TPCC_TPCC_IESR_IESR27=1;TPCC_TPCC_IESR_IESR28=1;TPCC_TPCC_IESR_IESR29=1;
3787 * TPCC_TPCC_IESR_IESR30=1;TPCC_TPCC_IESR_IESR31=1;
3788 *
3789 * @b Example
3790 * @verbatim
3791 CSL_Edma3Handle hModule;
3792 CSL_Edma3Obj edmaObj;
3793 CSL_Edma3Context context;
3794 CSL_Status status;
3796 // Module Initialization
3797 CSL_edma3Init(&context);
3799 // Module Level Open
3800 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
3802 // Interrupts 5-7 enabled for the global region.
3803 CSL_edma3InterruptLoEnable(hModule,CSL_EDMA3_REGION_GLOBAL, 0x000000E0);
3804 ...
3805 @endverbatim
3806 * ===========================================================================
3807 */
3808 static inline void CSL_edma3InterruptLoEnable
3809 (
3810 CSL_Edma3Handle hModule,
3811 Int region,
3812 CSL_BitMask32 intrLo
3813 );
3814 static inline void CSL_edma3InterruptLoEnable
3815 (
3816 CSL_Edma3Handle hModule,
3817 Int region,
3818 CSL_BitMask32 intrLo
3819 )
3820 {
3821 /* Enable the interrupts depending on the region. */
3822 if (region != CSL_EDMA3_REGION_GLOBAL)
3823 {
3824 /* Shadow Region */
3825 hModule->regs->SHADOW[region].TPCC_IESR |= intrLo;
3826 }
3827 else
3828 {
3829 /* Global Region */
3830 hModule->regs->TPCC_IESR |= intrLo;
3831 }
3832 return;
3833 }
3835 /** ============================================================================
3836 * @n@b CSL_edma3InterruptHiEnable
3837 *
3838 * @b Description
3839 * @n The API enables the specific High interrupt.
3840 *
3841 * @b Arguments
3842 * @verbatim
3843 hModule Module Handle
3844 region Region (Shadow or Global)
3845 intrHi Interrupt 32-63 (BitMask32) to be enabled
3846 @endverbatim
3847 *
3848 * <b> Return Value </b>
3849 * @n None
3850 *
3851 * <b> Pre Condition </b>
3852 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
3853 *
3854 * <b> Post Condition </b>
3855 * @n None
3856 *
3857 * @b Writes
3858 * @n TPCC_TPCC_IESRH_IESR32=1;TPCC_TPCC_IESRH_IESR33=1;TPCC_TPCC_IESRH_IESR34=1;
3859 * TPCC_TPCC_IESRH_IESR35=1;TPCC_TPCC_IESRH_IESR36=1;TPCC_TPCC_IESRH_IESR37=1;
3860 * TPCC_TPCC_IESRH_IESR38=1;TPCC_TPCC_IESRH_IESR39=1;TPCC_TPCC_IESRH_IESR40=1;
3861 * TPCC_TPCC_IESRH_IESR41=1;TPCC_TPCC_IESRH_IESR42=1;TPCC_TPCC_IESRH_IESR43=1;
3862 * TPCC_TPCC_IESRH_IESR44=1;TPCC_TPCC_IESRH_IESR45=1;TPCC_TPCC_IESRH_IESR46=1;
3863 * TPCC_TPCC_IESRH_IESR47=1;TPCC_TPCC_IESRH_IESR48=1;TPCC_TPCC_IESRH_IESR49=1;
3864 * TPCC_TPCC_IESRH_IESR50=1;TPCC_TPCC_IESRH_IESR51=1;TPCC_TPCC_IESRH_IESR52=1;
3865 * TPCC_TPCC_IESRH_IESR53=1;TPCC_TPCC_IESRH_IESR54=1;TPCC_TPCC_IESRH_IESR55=1;
3866 * TPCC_TPCC_IESRH_IESR56=1;TPCC_TPCC_IESRH_IESR57=1;TPCC_TPCC_IESRH_IESR58=1;
3867 * TPCC_TPCC_IESRH_IESR59=1;TPCC_TPCC_IESRH_IESR60=1;TPCC_TPCC_IESRH_IESR61=1;
3868 * TPCC_TPCC_IESRH_IESR62=1;TPCC_TPCC_IESRH_IESR63=1;
3869 *
3870 * @b Example
3871 * @verbatim
3872 CSL_Edma3Handle hModule;
3873 CSL_Edma3Obj edmaObj;
3874 CSL_Edma3Context context;
3875 CSL_Status status;
3877 // Module Initialization
3878 CSL_edma3Init(&context);
3880 // Module Level Open
3881 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
3883 // Interrupts 32 enabled for the global region.
3884 CSL_edma3InterruptHiEnable(hModule,CSL_EDMA3_REGION_GLOBAL, 0x1);
3885 ...
3886 @endverbatim
3887 * ===========================================================================
3888 */
3889 static inline void CSL_edma3InterruptHiEnable
3890 (
3891 CSL_Edma3Handle hModule,
3892 Int region,
3893 CSL_BitMask32 intrHi
3894 );
3895 static inline void CSL_edma3InterruptHiEnable
3896 (
3897 CSL_Edma3Handle hModule,
3898 Int region,
3899 CSL_BitMask32 intrHi
3900 )
3901 {
3902 /* Enable the interrupts depending on the region. */
3903 if (region != CSL_EDMA3_REGION_GLOBAL)
3904 {
3905 /* Shadow Region */
3906 hModule->regs->SHADOW[region].TPCC_IESRH |= intrHi;
3907 }
3908 else
3909 {
3910 /* Global Region */
3911 hModule->regs->TPCC_IESRH |= intrHi;
3912 }
3913 return;
3914 }
3916 /** ============================================================================
3917 * @n@b CSL_edma3GetLoPendingInterrupts
3918 *
3919 * @b Description
3920 * @n The API gets a bitmask of all low pending interrupts.
3921 *
3922 * @b Arguments
3923 * @verbatim
3924 hModule Module Handle
3925 region Region (Shadown Region or Global)
3926 intrLo Status 0-31 of the interrupts
3927 @endverbatim
3928 *
3929 * <b> Return Value </b>
3930 * @n None
3931 *
3932 * <b> Pre Condition </b>
3933 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
3934 *
3935 * <b> Post Condition </b>
3936 * @n None
3937 *
3938 * @b Reads
3939 * @n TPCC_TPCC_IPR
3940 *
3941 * @b Example
3942 * @verbatim
3943 CSL_Edma3Handle hModule;
3944 CSL_Edma3Obj edmaObj;
3945 CSL_Edma3Context context;
3946 CSL_Status status;
3947 CSL_BitMask32 edmaIntrLo;
3949 // Module Initialization
3950 CSL_edma3Init(&context);
3952 // Module Level Open
3953 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
3954 ...
3955 // Get all low pending interrupts for the global region.
3956 CSL_edma3GetLoPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, &edmaIntrLo);
3957 ...
3958 @endverbatim
3959 * ===========================================================================
3960 */
3961 /* for misra warnings*/
3962 static inline void CSL_edma3GetLoPendingInterrupts
3963 (
3964 CSL_Edma3Handle hModule,
3965 Int region,
3966 CSL_BitMask32* intrLo
3967 );
3968 static inline void CSL_edma3GetLoPendingInterrupts
3969 (
3970 CSL_Edma3Handle hModule,
3971 Int region,
3972 CSL_BitMask32* intrLo
3973 )
3974 {
3975 /* Get the pending interrupts depending on the region */
3976 if (region != CSL_EDMA3_REGION_GLOBAL)
3977 {
3978 /* Shadow Region. */
3979 *intrLo = hModule->regs->SHADOW[region].TPCC_IPR;
3980 }
3981 else
3982 {
3983 /* Global Region. */
3984 *intrLo = hModule->regs->TPCC_IPR;
3985 }
3986 return;
3987 }
3989 /** ============================================================================
3990 * @n@b CSL_edma3GetHiPendingInterrupts
3991 *
3992 * @b Description
3993 * @n The API gets a bitmask of all high pending interrupts.
3994 *
3995 * @b Arguments
3996 * @verbatim
3997 hModule Module Handle
3998 region Region (Shadown Region or Global)
3999 intrHi Status 32-63 of the interrupts
4000 @endverbatim
4001 *
4002 * <b> Return Value </b>
4003 * @n None
4004 *
4005 * <b> Pre Condition </b>
4006 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
4007 *
4008 * <b> Post Condition </b>
4009 * @n None
4010 *
4011 * @b Reads
4012 * @n TPCC_TPCC_IPRH
4013 *
4014 * @b Example
4015 * @verbatim
4016 CSL_Edma3Handle hModule;
4017 CSL_Edma3Obj edmaObj;
4018 CSL_Edma3Context context;
4019 CSL_Status status;
4020 CSL_BitMask32 edmaIntrHi;
4022 // Module Initialization
4023 CSL_edma3Init(&context);
4025 // Module Level Open
4026 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
4027 ...
4028 // Get all the high pending interrupts for the global region.
4029 CSL_edma3GetHiPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, &edmaIntrHi);
4030 ...
4031 @endverbatim
4032 * ===========================================================================
4033 */
4034 /* for misra warnings*/
4035 static inline void CSL_edma3GetHiPendingInterrupts
4036 (
4037 CSL_Edma3Handle hModule,
4038 Int region,
4039 CSL_BitMask32* intrHi
4040 );
4041 static inline void CSL_edma3GetHiPendingInterrupts
4042 (
4043 CSL_Edma3Handle hModule,
4044 Int region,
4045 CSL_BitMask32* intrHi
4046 )
4047 {
4048 /* Get the pending interrupts depending on the region */
4049 if (region != CSL_EDMA3_REGION_GLOBAL)
4050 {
4051 /* Shadow Region. */
4052 *intrHi = hModule->regs->SHADOW[region].TPCC_IPRH;
4053 }
4054 else
4055 {
4056 /* Global Region. */
4057 *intrHi = hModule->regs->TPCC_IPRH;
4058 }
4059 return;
4060 }
4062 /** ============================================================================
4063 * @n@b CSL_edma3ClearLoPendingInterrupts
4064 *
4065 * @b Description
4066 * @n This API clears the low pending interrupts using the interrupt bitmasks
4067 * provided
4068 *
4069 * @b Arguments
4070 * @verbatim
4071 hModule Module Handle
4072 region Region (Shadown Region or Global)
4073 intrLo Interrupt 0-31 (BitMask32) to be cleared
4074 @endverbatim
4075 *
4076 * <b> Return Value </b>
4077 * @n None
4078 *
4079 * <b> Pre Condition </b>
4080 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
4081 *
4082 * <b> Post Condition </b>
4083 * @n None
4084 *
4085 * @b Writes
4086 * @n TPCC_TPCC_ICR
4087 *
4088 * @b Example
4089 * @verbatim
4090 CSL_Edma3Handle hModule;
4091 CSL_Edma3Obj edmaObj;
4092 CSL_Edma3Context context;
4093 CSL_Status status;
4094 CSL_BitMask32 edmaIntrLo;
4096 // Module Initialization
4097 CSL_edma3Init(&context);
4099 // Module Level Open
4100 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
4101 ...
4102 // Get all the pending interrupts for the global region.
4103 CSL_edma3GetLoPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, &edmaIntrLo);
4104 ...
4105 // Clear the pending interrupts for the global region.
4106 CSL_edma3ClearLoPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, edmaIntrLo);
4107 @endverbatim
4108 * ===========================================================================
4109 */
4110 static inline void CSL_edma3ClearLoPendingInterrupts
4111 (
4112 CSL_Edma3Handle hModule,
4113 Int region,
4114 CSL_BitMask32 intrLo
4115 );
4116 static inline void CSL_edma3ClearLoPendingInterrupts
4117 (
4118 CSL_Edma3Handle hModule,
4119 Int region,
4120 CSL_BitMask32 intrLo
4121 )
4122 {
4123 /* Clear the pending interrupts depending on the region. */
4124 if (region != CSL_EDMA3_REGION_GLOBAL)
4125 {
4126 /* Shadow Region */
4127 hModule->regs->SHADOW[region].TPCC_ICR = intrLo;
4128 }
4129 else
4130 {
4131 /* Global Region */
4132 hModule->regs->TPCC_ICR = intrLo;
4133 }
4134 return;
4135 }
4137 /** ============================================================================
4138 * @n@b CSL_edma3ClearHiPendingInterrupts
4139 *
4140 * @b Description
4141 * @n This API clears the High pending interrupts using the interrupt bitmasks
4142 * provided
4143 *
4144 * @b Arguments
4145 * @verbatim
4146 hModule Module Handle
4147 region Region (Shadown Region or Global)
4148 intrHi Interrupt 32-63 (BitMask32) to be cleared
4149 @endverbatim
4150 *
4151 * <b> Return Value </b>
4152 * @n None
4153 *
4154 * <b> Pre Condition </b>
4155 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
4156 *
4157 * <b> Post Condition </b>
4158 * @n None
4159 *
4160 * @b Writes
4161 * @n TPCC_TPCC_ICRH
4162 *
4163 * @b Example
4164 * @verbatim
4165 CSL_Edma3Handle hModule;
4166 CSL_Edma3Obj edmaObj;
4167 CSL_Edma3Context context;
4168 CSL_Status status;
4169 CSL_BitMask32 edmaIntrHi;
4171 // Module Initialization
4172 CSL_edma3Init(&context);
4174 // Module Level Open
4175 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
4176 ...
4177 // Get all the pending interrupts for the global region.
4178 CSL_edma3GetHiPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, &edmaIntrHi);
4179 ...
4180 // Clear the pending interrupts for the global region.
4181 CSL_edma3ClearHiPendingInterrupts(hModule, CSL_EDMA3_REGION_GLOBAL, edmaIntrHi);
4182 @endverbatim
4183 * ===========================================================================
4184 */
4185 static inline void CSL_edma3ClearHiPendingInterrupts
4186 (
4187 CSL_Edma3Handle hModule,
4188 Int region,
4189 CSL_BitMask32 intrHi
4190 );
4191 static inline void CSL_edma3ClearHiPendingInterrupts
4192 (
4193 CSL_Edma3Handle hModule,
4194 Int region,
4195 CSL_BitMask32 intrHi
4196 )
4197 {
4198 /* Clear the pending interrupts depending on the region. */
4199 if (region != CSL_EDMA3_REGION_GLOBAL)
4200 {
4201 /* Shadow Region */
4202 hModule->regs->SHADOW[region].TPCC_ICRH = intrHi;
4203 }
4204 else
4205 {
4206 /* Global Region */
4207 hModule->regs->TPCC_ICRH = intrHi;
4208 }
4209 return;
4210 }
4212 /** ============================================================================
4213 * @n@b CSL_edma3InterruptEval
4214 *
4215 * @b Description
4216 * @n The API is used to set the EVAL bit which will cause an interrupt to be
4217 * generated if any enabled interrupts are still pending.
4218 *
4219 * @b Arguments
4220 * @verbatim
4221 hModule Module Handle
4222 region Region (Shadown Region or Global)
4223 @endverbatim
4224 *
4225 * <b> Return Value </b>
4226 * @n None
4227 *
4228 * <b> Pre Condition </b>
4229 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
4230 *
4231 * <b> Post Condition </b>
4232 * @n None
4233 *
4234 * @b Writes
4235 * @n TPCC_TPCC_IEVAL_EVAL=1
4236 *
4237 * @b Example
4238 * @verbatim
4239 CSL_Edma3Handle hModule;
4240 CSL_Edma3Obj edmaObj;
4241 CSL_Edma3Context context;
4242 CSL_Status status;
4243 CSL_BitMask32 edmaIntrLo;
4244 CSL_BitMask32 edmaIntrHi;
4246 // Module Initialization
4247 CSL_edma3Init(&context);
4249 // Module Level Open
4250 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
4251 ...
4252 // Interrupt Evaluate for Global Region.
4253 status = CSL_edma3InterruptEval(hModule, CSL_EDMA3_REGION_GLOBAL);
4254 ...
4255 @endverbatim
4256 * ===========================================================================
4257 */
4258 static inline void CSL_edma3InterruptEval
4259 (
4260 CSL_Edma3Handle hModule,
4261 Int region
4262 );
4263 static inline void CSL_edma3InterruptEval
4264 (
4265 CSL_Edma3Handle hModule,
4266 Int region
4267 )
4268 {
4269 /* Determine the region for which the interrupt evaluate needs to be done. */
4270 if (region != CSL_EDMA3_REGION_GLOBAL)
4271 {
4272 /* Shadow Region. */
4273 hModule->regs->SHADOW[region].TPCC_IEVAL = CSL_FMK(TPCC_TPCC_IEVAL_EVAL, 1U);
4274 }
4275 else
4276 {
4277 /* Global Region. */
4278 hModule->regs->TPCC_IEVAL = CSL_FMK(TPCC_TPCC_IEVAL_EVAL, 1U);
4279 }
4280 return;
4281 }
4283 /** ============================================================================
4284 * @n@b CSL_edma3IsQDMAChannelEventPending
4285 *
4286 * @b Description
4287 * @n The function gets the status of the specified QDMA channel i.e. if
4288 * there is a pending event on the specific channel.
4289 *
4290 * @b Arguments
4291 * @verbatim
4292 hModule Module Handle
4293 qdmaChannel QDMA Channel for which status is being inquired.
4294 response Place holder for whether an event is set(TRUE) or not (FALSE)
4295 @endverbatim
4296 *
4297 * <b> Return Value </b>
4298 * @n None.
4299 *
4300 * <b> Pre Condition </b>
4301 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
4302 *
4303 * <b> Post Condition </b>
4304 * @n None
4305 *
4306 * @b Reads
4307 * @n TPCC_TPCC_QER_QER0;TPCC_TPCC_QER_QER1;TPCC_TPCC_QER_QER2;TPCC_TPCC_QER_QER3;
4308 * TPCC_TPCC_QER_QER4;TPCC_TPCC_QER_QER5;TPCC_TPCC_QER_QER6;TPCC_TPCC_QER_QER7
4309 *
4310 * @b Example
4311 * @verbatim
4312 CSL_Edma3Handle hModule;
4313 CSL_Edma3Obj edmaObj;
4314 CSL_Edma3Context context;
4315 CSL_Status status;
4316 Bool qdmaStatus;
4318 // Module Initialization
4319 CSL_edma3Init(&context);
4321 // Module Level Open
4322 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
4323 ...
4324 // Is QDMA Channel 1 event pending.
4325 CSL_edma3IsQDMAChannelEventPending(hModule, 1, &qdmaStatus);
4326 ...
4327 @endverbatim
4328 * ===========================================================================
4329 */
4330 /* for misra warnings*/
4331 static inline void CSL_edma3IsQDMAChannelEventPending
4332 (
4333 CSL_Edma3Handle hModule,
4334 Uint8 qdmaChannel,
4335 Bool* response
4336 );
4337 static inline void CSL_edma3IsQDMAChannelEventPending
4338 (
4339 CSL_Edma3Handle hModule,
4340 Uint8 qdmaChannel,
4341 Bool* response
4342 )
4343 {
4344 /* Read the specific QDMA channel bits. */
4345 if (CSL_FEXTR(hModule->regs->TPCC_QER, (Uint32)qdmaChannel, (Uint32)qdmaChannel))
4346 {
4347 *response = TRUE;
4348 }
4349 else
4350 {
4351 *response = FALSE;
4352 }
4353 return;
4354 }
4356 /** ============================================================================
4357 * @n@b CSL_edma3QDMAChannelEnable
4358 *
4359 * @b Description
4360 * @n This API enables the specified QDMA Channel.
4361 *
4362 * @b Arguments
4363 * @verbatim
4364 hModule Module Handle
4365 region Region (Shadown Region or Global)
4366 qdmaChannel QDMA Channel to be enabled.
4367 @endverbatim
4368 *
4369 * <b> Return Value </b>
4370 * @n None
4371 *
4372 * <b> Pre Condition </b>
4373 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
4374 *
4375 * <b> Post Condition </b>
4376 * @n None
4377 *
4378 * @b Writes
4379 * @n TPCC_TPCC_QEESR_QEESR0=1;TPCC_TPCC_QEESR_QEESR1=1;TPCC_TPCC_QEESR_QEESR2=1;
4380 * TPCC_TPCC_QEESR_QEESR3=1;TPCC_TPCC_QEESR_QEESR4=1;TPCC_TPCC_QEESR_QEESR5=1;
4381 * TPCC_TPCC_QEESR_QEESR6=1;TPCC_TPCC_QEESR_QEESR7=1;
4382 *
4383 * @b Example
4384 * @verbatim
4385 CSL_Edma3Handle hModule;
4386 CSL_Edma3Obj edmaObj;
4387 CSL_Edma3Context context;
4388 CSL_Status status;
4390 // Module Initialization
4391 CSL_edma3Init(&context);
4393 // Module Level Open
4394 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
4396 // Enables QDMA Channel 1 for Global Region.
4397 CSL_edma3QDMAChannelEnable(hModule, CSL_EDMA3_REGION_GLOBAL, 1);
4398 ...
4399 @endverbatim
4400 * ===========================================================================
4401 */
4402 /* for misra warnings*/
4403 static inline void CSL_edma3QDMAChannelEnable
4404 (
4405 CSL_Edma3Handle hModule,
4406 Int region,
4407 Uint8 qdmaChannel
4408 );
4409 static inline void CSL_edma3QDMAChannelEnable
4410 (
4411 CSL_Edma3Handle hModule,
4412 Int region,
4413 Uint8 qdmaChannel
4414 )
4415 {
4416 /* Determine the region for which the QDMA channel is to be enabled. */
4417 if (region == CSL_EDMA3_REGION_GLOBAL)
4418 {
4419 /* Global: Write to the specific QDMA Channel bits */
4420 hModule->regs->TPCC_QEESR = CSL_FMKR(qdmaChannel, qdmaChannel, 1U);
4421 }
4422 else
4423 {
4424 /* Shadow: Write to the specific QDMA Channel bits. */
4425 hModule->regs->SHADOW[region].TPCC_QEESR = CSL_FMKR(qdmaChannel, qdmaChannel, 1U);
4426 }
4427 return;
4428 }
4430 /** ============================================================================
4431 * @n@b CSL_edma3QDMAChannelDisable
4432 *
4433 * @b Description
4434 * @n This API disables the specified QDMA Channel.
4435 *
4436 * @b Arguments
4437 * @verbatim
4438 hModule Module Handle
4439 region Region (Shadown Region or Global)
4440 qdmaChannel QDMA Channel to be disabled.
4441 @endverbatim
4442 *
4443 * <b> Return Value </b>
4444 * @n None
4445 *
4446 * <b> Pre Condition </b>
4447 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
4448 *
4449 * <b> Post Condition </b>
4450 * @n None
4451 *
4452 * @b Writes
4453 * @n TPCC_TPCC_QEECR_QEECR0=1;TPCC_TPCC_QEECR_QEECR1=1;TPCC_TPCC_QEECR_QEECR2=1;
4454 * TPCC_TPCC_QEECR_QEECR3=1;TPCC_TPCC_QEECR_QEECR4=1;TPCC_TPCC_QEECR_QEECR5=1;
4455 * TPCC_TPCC_QEECR_QEECR6=1;TPCC_TPCC_QEECR_QEECR7=1;
4456 *
4457 * @b Example
4458 * @verbatim
4459 CSL_Edma3Handle hModule;
4460 CSL_Edma3Obj edmaObj;
4461 CSL_Edma3Context context;
4462 CSL_Status status;
4464 // Module Initialization
4465 CSL_edma3Init(&context);
4467 // Module Level Open
4468 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
4470 // Disables QDMA Channel 0
4471 CSL_edma3QDMAChannelDisable(hModule, 0);
4472 ...
4473 @endverbatim
4474 * ===========================================================================
4475 */
4476 /* for misra warnings*/
4477 static inline void CSL_edma3QDMAChannelDisable
4478 (
4479 CSL_Edma3Handle hModule,
4480 Int region,
4481 Uint8 qdmaChannel
4482 );
4483 static inline void CSL_edma3QDMAChannelDisable
4484 (
4485 CSL_Edma3Handle hModule,
4486 Int region,
4487 Uint8 qdmaChannel
4488 )
4489 {
4490 /* Determine the region for which the QDMA channel is to be disabled. */
4491 if (region == CSL_EDMA3_REGION_GLOBAL)
4492 {
4493 /* Global: Write to the specific QDMA Channel bits */
4494 CSL_FINSR(hModule->regs->TPCC_QEECR, qdmaChannel, qdmaChannel, 1U);
4495 }
4496 else
4497 {
4498 /* Shadow: Write to the specific QDMA Channel bits. */
4499 CSL_FINSR(hModule->regs->SHADOW[region].TPCC_QEECR, qdmaChannel, qdmaChannel, 1U);
4500 }
4501 return;
4502 }
4504 /** ============================================================================
4505 * @n@b CSL_edma3GetQDMASecondaryEvents
4506 *
4507 * @b Description
4508 * @n This API reads the QDMA Secondary Event.
4509 *
4510 * @b Arguments
4511 * @verbatim
4512 hModule Module Handle
4513 qdmaSecEvent QDMA Secondary Event which is populated by this API
4514 @endverbatim
4515 *
4516 * <b> Return Value </b>
4517 * @n None
4518 *
4519 * <b> Pre Condition </b>
4520 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
4521 *
4522 * <b> Post Condition </b>
4523 * @n None
4524 *
4525 * @b Reads
4526 * @n TPCC_TPCC_QSER
4527 *
4528 * @b Example
4529 * @verbatim
4530 CSL_Edma3Handle hModule;
4531 CSL_Edma3Obj edmaObj;
4532 CSL_Edma3Context context;
4533 Uint32 qdmaSecEvent;
4535 // Module Initialization
4536 CSL_edma3Init(&context);
4538 // Module Level Open
4539 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
4540 ...
4541 // Get the QDMA Secondary Event
4542 CSL_edma3GetQDMASecondaryEvents(hModule, &qdmaSecEvent);
4543 ...
4544 @endverbatim
4545 * ===========================================================================
4546 */
4547 /* for misra warnings*/
4548 static inline void CSL_edma3GetQDMASecondaryEvents
4549 (
4550 CSL_Edma3Handle hModule,
4551 Uint32* qdmaSecEvent
4552 );
4553 static inline void CSL_edma3GetQDMASecondaryEvents
4554 (
4555 CSL_Edma3Handle hModule,
4556 Uint32* qdmaSecEvent
4557 )
4558 {
4559 /* Read the QDMA Secondary Event. */
4560 *qdmaSecEvent = hModule->regs->TPCC_QSER;
4561 return;
4562 }
4564 /** ============================================================================
4565 * @n@b CSL_edma3IsDMAChannelSecondaryEventSet
4566 *
4567 * @b Description
4568 * @n This API is used to determine if the secondary Event for a specific DMA
4569 * channel is set or not?
4570 *
4571 * @b Arguments
4572 * @verbatim
4573 hModule Module Handle
4574 qdmaChannel QDMA Channel for which secondary Events are being checked
4575 response Status of the check populated by the API (TRUE if event
4576 is missed else FALSE)
4577 @endverbatim
4578 *
4579 * <b> Return Value </b>
4580 * @n None
4581 *
4582 * <b> Pre Condition </b>
4583 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
4584 *
4585 * <b> Post Condition </b>
4586 * @n None
4587 *
4588 * @b Reads
4589 * @n TPCC_TPCC_QSER_QSER0;TPCC_TPCC_QSER_QSER1;TPCC_TPCC_QSER_QSER2;
4590 * TPCC_TPCC_QSER_QSER3;TPCC_TPCC_QSER_QSER4;TPCC_TPCC_QSER_QSER5;
4591 * TPCC_TPCC_QSER_QSER6;TPCC_TPCC_QSER_QSER7;
4592 *
4593 * @b Example
4594 * @verbatim
4595 CSL_Edma3Handle hModule;
4596 CSL_Edma3Obj edmaObj;
4597 CSL_Edma3Context context;
4598 CSL_Status status;
4599 Bool response;
4601 // Module Initialization
4602 CSL_edma3Init(&context);
4604 // Module Level Open
4605 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
4607 // Check if the QDMA Channel 1 Secondary Event is set or not?
4608 CSL_edma3IsQDMAChannelSecondaryEventSet(hModule, 1, &response);
4609 ...
4610 @endverbatim
4611 * ===========================================================================
4612 */
4613 /* for misra warnings*/
4614 static inline void CSL_edma3IsQDMAChannelSecondaryEventSet
4615 (
4616 CSL_Edma3Handle hModule,
4617 Uint8 qdmaChannel,
4618 Bool* response
4619 );
4620 static inline void CSL_edma3IsQDMAChannelSecondaryEventSet
4621 (
4622 CSL_Edma3Handle hModule,
4623 Uint8 qdmaChannel,
4624 Bool* response
4625 )
4626 {
4627 /* Check if the QDMA channel bit is set or not? */
4628 if (CSL_FEXTR(hModule->regs->TPCC_QSER, (Uint32)qdmaChannel, (Uint32)qdmaChannel))
4629 {
4630 *response = TRUE;
4631 }
4632 else
4633 {
4634 *response = FALSE;
4635 }
4636 return;
4637 }
4639 /** ============================================================================
4640 * @n@b CSL_edma3ClearQDMASecondaryEvents
4641 *
4642 * @b Description
4643 * @n This API clears the QDMA Secondary Event.
4644 *
4645 * @b Arguments
4646 * @verbatim
4647 hModule Module Handle
4648 qdmaSecEvent QDMA Secondary Event to be cleared.
4649 @endverbatim
4650 *
4651 * <b> Return Value </b>
4652 * @n None
4653 *
4654 * <b> Pre Condition </b>
4655 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
4656 *
4657 * <b> Post Condition </b>
4658 * @n None
4659 *
4660 * @b Writes
4661 * @n TPCC_TPCC_QSECR
4662 *
4663 * @b Example
4664 * @verbatim
4665 CSL_Edma3Handle hModule;
4666 CSL_Edma3Obj edmaObj;
4667 CSL_Edma3Context context;
4668 Uint32 qdmaSecEvent;
4670 // Module Initialization
4671 CSL_edma3Init(&context);
4673 // Module Level Open
4674 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
4675 ...
4676 // Get the QDMA Secondary Event
4677 CSL_edma3GetQDMASecondaryEvents(hModule, &qdmaSecEvent);
4678 ...
4679 // Clear the QDMA Secondary Event
4680 CSL_edma3ClearQDMASecondaryEvents(hModule, qdmaSecEvent);
4681 ...
4682 @endverbatim
4683 * ===========================================================================
4684 */
4685 /* for misra warnings*/
4686 static inline void CSL_edma3ClearQDMASecondaryEvents
4687 (
4688 CSL_Edma3Handle hModule,
4689 Uint32 qdmaSecEvent
4690 );
4691 static inline void CSL_edma3ClearQDMASecondaryEvents
4692 (
4693 CSL_Edma3Handle hModule,
4694 Uint32 qdmaSecEvent
4695 )
4696 {
4697 /* Clears the QDMA Secondary Event. */
4698 hModule->regs->TPCC_QSECR = qdmaSecEvent;
4699 }
4701 /** ============================================================================
4702 * @n@b CSL_edma3ClearQDMAChannelSecondaryEvents
4703 *
4704 * @b Description
4705 * @n This API clears the QDMA Secondary Event for a specific QDMA Channel.
4706 *
4707 * @b Arguments
4708 * @verbatim
4709 hModule Module Handle
4710 qdmaChannel QDMA Channel for which the secondary event is to be cleared.
4711 @endverbatim
4712 *
4713 * <b> Return Value </b>
4714 * @n None
4715 *
4716 * <b> Pre Condition </b>
4717 * @n Both @a CSL_edma3Init() and @a CSL_edma3Open() must be called.
4718 *
4719 * <b> Post Condition </b>
4720 * @n None
4721 *
4722 * @b Writes
4723 * @n TPCC_TPCC_QSECR_QSECR0=1;TPCC_TPCC_QSECR_QSECR1=1;TPCC_TPCC_QSECR_QSECR2=1;
4724 * TPCC_TPCC_QSECR_QSECR3=1;TPCC_TPCC_QSECR_QSECR4=1;TPCC_TPCC_QSECR_QSECR5=1;
4725 * TPCC_TPCC_QSECR_QSECR6=1;TPCC_TPCC_QSECR_QSECR7=1;
4726 *
4727 * @b Example
4728 * @verbatim
4729 CSL_Edma3Handle hModule;
4730 CSL_Edma3Obj edmaObj;
4731 CSL_Edma3Context context;
4732 Uint32 qdmaSecEvent;
4734 // Module Initialization
4735 CSL_edma3Init(&context);
4737 // Module Level Open
4738 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
4739 ...
4740 // Clear the QDMA Secondary Event for QDMA channel 1
4741 CSL_edma3ClearQDMAChannelSecondaryEvents(hModule, 1);
4742 ...
4743 @endverbatim
4744 * ===========================================================================
4745 */
4746 /* for misra warnings*/
4747 static inline void CSL_edma3ClearQDMAChannelSecondaryEvents
4748 (
4749 CSL_Edma3Handle hModule,
4750 Uint8 qdmaChannel
4751 );
4752 static inline void CSL_edma3ClearQDMAChannelSecondaryEvents
4753 (
4754 CSL_Edma3Handle hModule,
4755 Uint8 qdmaChannel
4756 )
4757 {
4758 /* Clears the QDMA Secondary Event. */
4759 CSL_FINSR (hModule->regs->TPCC_QSECR, qdmaChannel, qdmaChannel, 1U);
4760 }
4762 /**
4763 @}
4764 */
4766 #endif /* CSL_EDMA3AUX_H */