[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_1_eng / packages / ti / csl / csl_idmaAux.h
1 /* ============================================================================
2 * Copyright (c) Texas Instruments Incorporated 2008, 2009
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
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17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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31 *
32 */
34 /**
35 * @file csl_idmaAux.h
36 *
37 * @brief
38 * API Auxilary header file for IDMA CSL. It gives the definitions of the
39 * query, status & control functions.
40 *
41 * \par
42 * ============================================================================
43 * @n (C) Copyright 2008, 2009, Texas Instruments, Inc.
44 * @n Use of this software is controlled by the terms and conditions found
45 * @n in the license agreement under which this software has been supplied.
46 * ===========================================================================
47 * \par
48 */
50 #ifndef CSL_IDMAAUX_H_
51 #define CSL_IDMAAUX_H_
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
57 #include <ti/csl/csl_idma.h>
59 /** @addtogroup CSL_IDMA_FUNCTION
60 @{ */
62 /** ============================================================================
63 * @n@b CSL_IDMA_chan0TransferData
64 *
65 * @b Description
66 * @n This function configures IMDA Channel 0 to perform a transfer between
67 * Internal Memory (L1P, L1D, L2) and Configuration Space(CFG) based on the
68 * inputs to the function. This API initiates a transfer and if needed waits
69 * till the transfer completes based on the "bWaitToCompletion" flag value passed.
70 *
71 * @b Arguments
72 @verbatim
73 idmaChan0Config CSL_IDMA_IDMA0CONFIG structure pointer that holds
74 information relevant to perform a IDMA Channel 0 configuration
75 space transfer.
76 bWaitToCompletion Boolean flag that indicates if this function should
77 wait till the transfer is completed or should
78 just return after initiating one. When set to 1, this
79 API waits and returns after requested transfer is
80 complete. Otherwise, returns immediately after configuring
81 appropriate registers.
82 @endverbatim
83 *
84 * <b> Return Value </b>
85 * @n None
86 *
87 * <b> Pre Condition </b>
88 * @n None.
89 *
90 * <b> Post Condition </b>
91 * @n The appropriate IDMA Channel 0 registers are configured to initiate the
92 * CFG space transfer operation. Furthermore, if bWaitToCompletion argument is set
93 * to 1, the API polls on the IDMA0 Status register to wait until the
94 * transfer completes.
95 *
96 * @b Writes
97 * @n CGEM_IDMA0_MASK_MASK,
98 * CGEM_IDMA0_SOURCE_SOURCEADDR,
99 * CGEM_IDMA0_DEST_DESTADDR,
100 * CGEM_IDMA0_COUNT_INT,
101 * CGEM_IDMA0_COUNT_COUNT
102 *
103 * @b Example
104 * @verbatim
106 #define MASK 0xFFFFFF0F
108 // Align various arrays to a word address, in internal L2
109 #pragma DATA_SECTION(src, "ISRAM");
110 #pragma DATA_ALIGN(src, 32);
111 #pragma DATA_ALIGN(dst2, 32);
113 // Static 128 byte array of data in "src" with known test pattern.
114 unsigned int src[32] = {
115 0xDEADBEEF, 0xFADE0003, 0x5AA51C3A, 0x03036BA3,
116 0x0000ABCD, 0x00001234, 0x00005670, 0x00005678,
117 0x000003BE, 0x0000760F, 0x9675A800, 0xABCDEF12,
118 0xEEEECDEA, 0x01234567, 0x00000000, 0xFEEDFADE,
119 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
120 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
121 } ;
123 // EDMA MMR Space Address
124 unsigned int * dst2 = (unsigned int *)0x02704000;
126 CSL_IDMA_IDMA0CONFIG idmaChan0Config;
127 Uint32 bWaitEnable = 1;
129 mask = MASK;
130 idmaChan0Config.mask = mask;
131 idmaChan0Config.source = src;
132 idmaChan0Config.destn = dst2;
133 idmaChan0Config.count = 0; // transfer one 32-byte window
134 idmaChan0Config.intEnable = 1; // Enable CPU interrupt on completion.
135 CSL_IDMA_chan0TransferData (&idmaChan0Config, bWaitEnable);
137 @endverbatim
138 * =============================================================================
139 */
140 static inline void CSL_IDMA_chan0TransferData (
141 CSL_IDMA_IDMA0CONFIG* idmaChan0Config,
142 Uint32 bWaitToCompletion
143 )
144 {
145 volatile Uint32 pend;
147 if( bWaitToCompletion )
148 {
149 /* Make sure that there are no pending transfers before using
150 * this channel. This is done by reading bit "1" of the status
151 * register.
152 */
153 while( (pend = ( CSL_FEXT(hIdma->IDMA0_STAT, CGEM_IDMA0_STAT_PEND) |
154 CSL_FEXT(hIdma->IDMA0_STAT, CGEM_IDMA0_STAT_ACTV)
155 )
156 )
157 );
158 }
160 /* Poke in "mask", "src", "dst" and "count" with the correct
161 * count and interrupt flag on.
162 */
163 CSL_FINS (hIdma->IDMA0_MASK, CGEM_IDMA0_MASK_MASK, idmaChan0Config->mask);
164 hIdma->IDMA0_SOURCE = (Uint32)idmaChan0Config->source;
165 hIdma->IDMA0_DEST = (Uint32)idmaChan0Config->destn;
166 hIdma->IDMA0_COUNT = CSL_FMK (CGEM_IDMA0_COUNT_INT, idmaChan0Config->intEnable) |
167 CSL_FMK (CGEM_IDMA0_COUNT_COUNT, idmaChan0Config->count);
169 /* Wait till the transfer is complete. */
170 if( bWaitToCompletion )
171 {
172 while( (pend = ( CSL_FEXT(hIdma->IDMA0_STAT, CGEM_IDMA0_STAT_PEND) |
173 CSL_FEXT(hIdma->IDMA0_STAT, CGEM_IDMA0_STAT_ACTV)
174 )
175 )
176 );
178 }
180 return;
181 }
183 /** ============================================================================
184 * @n@b CSL_IDMA_chan0Wait
185 *
186 * @b Description
187 * @n This function waits until all previous transfers for IDMA Channel
188 * 0 have been completed by making sure that both active and pend
189 * bits are zero. These are the two least significant bits of the
190 * status register for the channel.
191 *
192 * Waits until previous transfers have completed for IDMA channel 0
193 * before returning.
194 *
195 * @b Arguments
196 * @n None
197 *
198 * <b> Return Value </b>
199 * @n None
200 *
201 * <b> Pre Condition </b>
202 * @n @a CSL_IDMA_chan0TransferData(bWaitToCompletion=0) must be called
203 * to setup an IDMA Channel 0 data transfer before this API is called.
204 *
205 * <b> Post Condition </b>
206 * @n None
207 *
208 * @b Reads
209 * @n CGEM_IDMA0_STAT_PEND,
210 * CGEM_IDMA0_STAT_ACTV
211 *
212 * @b Affects
213 * @n CGEM_IDMA0_STAT_PEND=0,
214 * CGEM_IDMA0_STAT_ACTV=0
215 *
216 * @b Example
217 * @verbatim
219 #define MASK 0xFFFFFF0F
221 // Align various arrays to a word address, in internal L2
222 #pragma DATA_SECTION(src, "ISRAM");
223 #pragma DATA_ALIGN(src, 32);
224 #pragma DATA_ALIGN(dst2, 32);
226 // Static 128 byte array of data in "src" with known test pattern.
227 unsigned int src[32] = {
228 0xDEADBEEF, 0xFADE0003, 0x5AA51C3A, 0x03036BA3,
229 0x0000ABCD, 0x00001234, 0x00005670, 0x00005678,
230 0x000003BE, 0x0000760F, 0x9675A800, 0xABCDEF12,
231 0xEEEECDEA, 0x01234567, 0x00000000, 0xFEEDFADE,
232 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
233 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
234 } ;
236 // EDMA MMR Space Address
237 unsigned int * dst2 = (unsigned int *)0x02704000;
239 CSL_IDMA_IDMA0CONFIG idmaChan0Config;
240 Uint32 bWaitEnable = 1;
242 mask = MASK;
243 idmaChan0Config.mask = mask;
244 idmaChan0Config.source = src;
245 idmaChan0Config.destn = dst2;
246 idmaChan0Config.count = 0; // transfer one 32-byte window
247 idmaChan0Config.intEnable = 1; // Enable CPU interrupt on completion.
248 CSL_IDMA_chan0TransferData (&idmaChan0Config, bWaitEnable);
250 CSL_IDMA_chan0Wait ();
252 ...
254 @endverbatim
255 * =============================================================================
256 */
257 static inline void CSL_IDMA_chan0Wait (
258 void
259 )
260 {
261 volatile Uint32 pend;
263 while( (pend = ( CSL_FEXT(hIdma->IDMA0_STAT, CGEM_IDMA0_STAT_PEND) |
264 CSL_FEXT(hIdma->IDMA0_STAT, CGEM_IDMA0_STAT_ACTV)
265 )
266 )
267 );
269 return;
270 }
273 /** ============================================================================
274 * @n@b CSL_IDMA_chan0GetStatus
275 *
276 * @b Description
277 * @n This function waits until all previous transfers for IDMA Channel
278 * 0 have been completed by making sure that both active and pend
279 * bits are zero. These are the two least significant bits of the
280 * status register for the channel.
281 *
282 * Waits until previous transfers have completed for IDMA channel 1
283 * before returning.
284 *
285 * @b Arguments
286 @verbatim
287 idmaChanStatus CSL_IDMA_STATUS structure pointer that needs to
288 be populated with iDMA Channel 0 transfer status.
289 @endverbatim
290 *
291 * <b> Return Value </b>
292 * @n None
293 *
294 * <b> Pre Condition </b>
295 * @n None.
296 *
297 * <b> Post Condition </b>
298 * @n None
299 *
300 * @b Reads
301 * @n CGEM_IDMA0_STAT_PEND,
302 * CGEM_IDMA0_STAT_ACTV
303 *
304 * @b Example
305 * @verbatim
307 CSL_IDMA_STATUS idma1Status;
309 CSL_IDMA_chan0GetStatus (&idma1Status);
311 @endverbatim
312 * =============================================================================
313 */
314 static inline void CSL_IDMA_chan0GetStatus (
315 CSL_IDMA_STATUS* idmaChanStatus
316 )
317 {
318 idmaChanStatus->isPending = CSL_FEXT(hIdma->IDMA0_STAT, CGEM_IDMA0_STAT_PEND);
319 idmaChanStatus->isActive = CSL_FEXT(hIdma->IDMA0_STAT, CGEM_IDMA0_STAT_ACTV);
321 return;
322 }
325 /** ============================================================================
326 * @n@b CSL_IDMA_chan1TransferData
327 *
328 * @b Description
329 * @n This function initiates a GEM local memory "block transfer" operation
330 * using the IDMA Channel 1. This API assumes that the source and destination
331 * addresses passed in the "idmaChan1Config" argument are both in GEM's internal
332 * memory, i.e., L1P, L1D, L2 or CFG memories. Transfers from addresses
333 * that are not in the internal memory will raise an exception. This API
334 * initiates a block transfer and if needed waits till the transfer completes
335 * based on the "bWaitToCompletion" flag value passed.
336 *
337 * @b Arguments
338 @verbatim
339 idmaChan1Config CSL_IDMA_IDMA1CONFIG structure pointer that holds
340 information relevant to perform a IDMA Channel 1 block
341 transfer.
342 bWaitToCompletion Boolean flag that indicates if this function should
343 wait till the block transfer is completed or should
344 just return after initiating one. When set to 1, this
345 API waits and returns after requested block transfer is
346 complete. Otherwise, returns immediately after configuring
347 appropriate registers.
348 @endverbatim
349 *
350 * <b> Return Value </b>
351 * @n None
352 *
353 * <b> Pre Condition </b>
354 * @n None.
355 *
356 * <b> Post Condition </b>
357 * @n The appropriate IDMA Channel 1 registers are configured to initiate the
358 * data transfer operation. Furthermore, if bWaitToCompletion argument is set
359 * to 1, the API polls on the IDMA1 Status register to wait until the
360 * transfer completes.
361 *
362 * @b Writes
363 * @n CGEM_IDMA1_SOURCE_SOURCEADDR,
364 * CGEM_IDMA1_DEST_DESTADDR,
365 * CGEM_IDMA1_COUNT_PRI,
366 * CGEM_IDMA1_COUNT_INT,
367 * CGEM_IDMA1_COUNT_FILL,
368 * CGEM_IDMA1_COUNT_COUNT
369 *
370 * @b Example
371 * @verbatim
373 #pragma DATA_ALIGN(src1, 8);
374 #pragma DATA_ALIGN(dst1, 8);
376 // Static 80 byte array of data in "src1" with known test pattern
377 Uint32 src1[20] =
378 {
379 0xDEADBEEF, 0xFADEBABE, 0x5AA51C3A, 0xD4536BA3,
380 0x5E69BA23, 0x4884A01F, 0x9265ACDA, 0xFFFF0123,
381 0xBEADDABE, 0x234A76B2, 0x9675ABCD, 0xABCDEF12,
382 0xEEEECDEA, 0x01234567, 0x00000000, 0xFEEDFADE,
383 0x0A1B2C3D, 0x4E5F6B7C, 0x5AA5ECCE, 0xFABEFACE
384 };
385 Uint32 dst1[20];
386 CSL_IDMA_IDMA1CONFIG idmaChan1Config;
387 Uint32 bWaitEnable = 1;
389 idmaChan1Config.source = src1;
390 idmaChan1Config.destn = dst1;
391 idmaChan1Config.intEnable = 1;
392 idmaChan1Config.priority = IDMA_PRI_7;
393 idmaChan1Config.count = DATA_COUNT_BYTES;
395 CSL_IDMA_chan1TransferData (&idmaChan1Config, bWaitEnable);
396 @endverbatim
397 * =============================================================================
398 */
399 static inline void CSL_IDMA_chan1TransferData (
400 CSL_IDMA_IDMA1CONFIG* idmaChan1Config,
401 Uint32 bWaitToCompletion
402 )
403 {
404 volatile Uint32 pend;
406 if( bWaitToCompletion )
407 {
408 /* Make sure that there are no pending transfers before using
409 * this channel. This is done by reading bit "1" of the status
410 * register.
411 */
412 while( (pend = ( CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_PEND) |
413 CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_ACTV)
414 )
415 )
416 );
417 }
419 /* Poke in "src", "dst" and "count" with the correct
420 * priority and interrupt flags on. Also disable the "fill" bit
421 * since this is a block transfer.
422 */
423 hIdma->IDMA1_SOURCE = (Uint32)idmaChan1Config->source;
424 hIdma->IDMA1_DEST = (Uint32)idmaChan1Config->destn;
425 hIdma->IDMA1_COUNT = CSL_FMK(CGEM_IDMA1_COUNT_PRI, idmaChan1Config->priority) |
426 CSL_FMK(CGEM_IDMA1_COUNT_INT, idmaChan1Config->intEnable) |
427 CSL_FMK(CGEM_IDMA1_COUNT_FILL, ZERO) |
428 CSL_FMK(CGEM_IDMA1_COUNT_COUNT, idmaChan1Config->count);
430 /* Wait till the transfer is complete. */
431 if( bWaitToCompletion )
432 {
433 while( (pend = ( CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_PEND) |
434 CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_ACTV)
435 )
436 )
437 );
438 }
440 return;
441 }
443 /** ============================================================================
444 * @n@b CSL_IDMA_chan1FillData
445 *
446 * @b Description
447 * @n This function initiates a GEM local memory "block fill" operation
448 * using the IDMA Channel 1. Given a fill value in Channel configuration structure's
449 * source address, a valid destination address and the number of bytes to fill, this
450 * API fills the destination with the fill value specified. This API initiates a
451 * block fill and if needed waits till the transfer completes based on the
452 * "bWaitToCompletion" flag value passed.
453 *
454 * @b Arguments
455 @verbatim
456 idmaChan1Config CSL_IDMA_IDMA1CONFIG structure pointer that holds
457 information relevant to perform a IDMA Channel 1 block
458 fill operation.
459 bWaitToCompletion Boolean flag that indicates if this function should
460 wait till the block fill is completed or should
461 just return after initiating one. When set to 1, this
462 API waits and returns after requested block transfer is
463 complete. Otherwise, returns immediately after configuring
464 appropriate registers.
465 @endverbatim
466 *
467 * <b> Return Value </b>
468 * @n None
469 *
470 * <b> Pre Condition </b>
471 * @n None.
472 *
473 * <b> Post Condition </b>
474 * @n The appropriate IDMA Channel 1 registers are configured to initiate the
475 * block fill operation. Furthermore, if bWaitToCompletion argument is set
476 * to 1, the API polls on the IDMA1 Status register to wait until the
477 * fill operation completes.
478 *
479 * @b Writes
480 * @n CGEM_IDMA1_SOURCE_SOURCEADDR,
481 * CGEM_IDMA1_DEST_DESTADDR,
482 * CGEM_IDMA1_COUNT_PRI,
483 * CGEM_IDMA1_COUNT_INT,
484 * CGEM_IDMA1_COUNT_FILL,
485 * CGEM_IDMA1_COUNT_COUNT
486 *
487 * @b Example
488 * @verbatim
490 #pragma DATA_ALIGN(dst1, 8);
491 Uint32 dst1[20];
492 CSL_IDMA_IDMA1CONFIG idmaChan1Config;
493 Uint32 bWaitEnable = 1;
495 // Fill the destination with a value of "0xAAAABABA"
496 idmaChan1Config.source = (Uint32 *) (0xAAAABABA);
497 idmaChan1Config.destn = dst1;
498 idmaChan1Config.intEnable = 1;
499 idmaChan1Config.priority = IDMA_PRI_7;
500 idmaChan1Config.count = 20;
502 CSL_IDMA_chan1FillData (&idmaChan1Config, bWaitEnable);
504 @endverbatim
505 * =============================================================================
506 */
507 static inline void CSL_IDMA_chan1FillData (
508 CSL_IDMA_IDMA1CONFIG* idmaChan1Config,
509 Uint32 bWaitToCompletion
510 )
511 {
512 volatile Uint32 pend;
514 if( bWaitToCompletion )
515 {
516 /* Make sure that there are no pending transfers before using
517 * this channel. This is done by reading bit "1" of the status
518 * register.
519 */
520 while( (pend = ( CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_PEND) |
521 CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_ACTV)
522 )
523 )
524 );
525 }
527 /* Poke in "src", "dst" and "count" with the correct
528 * priority and interrupt flags on. Also enable the "fill" bit
529 * since this is a block fill operation.
530 */
531 hIdma->IDMA1_SOURCE = (Uint32)idmaChan1Config->source;
532 hIdma->IDMA1_DEST = (Uint32)idmaChan1Config->destn;
533 hIdma->IDMA1_COUNT = CSL_FMK(CGEM_IDMA1_COUNT_PRI, idmaChan1Config->priority) |
534 CSL_FMK(CGEM_IDMA1_COUNT_INT, idmaChan1Config->intEnable) |
535 CSL_FMK(CGEM_IDMA1_COUNT_FILL, ONE) |
536 CSL_FMK(CGEM_IDMA1_COUNT_COUNT, idmaChan1Config->count);
538 /* Wait till the transfer is complete. */
539 if( bWaitToCompletion )
540 {
541 while( (pend = ( CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_PEND) |
542 CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_ACTV)
543 )
544 )
545 );
546 }
548 return;
549 }
551 /** ============================================================================
552 * @n@b CSL_IDMA_chan1Wait
553 *
554 * @b Description
555 * @n This function waits until all previous transfers for IDMA Channel
556 * 1 have been completed by making sure that both active and pend
557 * bits are zero. These are the two least significant bits of the
558 * status register for the channel.
559 *
560 * Waits until previous transfers have completed for IDMA channel 1
561 * before returning.
562 *
563 * @b Arguments
564 * @n None
565 *
566 * <b> Return Value </b>
567 * @n None
568 *
569 * <b> Pre Condition </b>
570 * @n @a CSL_IDMA_chan1TransferData(bWaitToCompletion = 0) or
571 * @a CSL_IDMA_chan1FillData(bWaitToCompletion = 0) must be called to
572 * setup IDMA Channel 1 data transfer before this API is called.
573 *
574 * <b> Post Condition </b>
575 * @n None
576 *
577 * @b Reads
578 * @n CGEM_IDMA1_STAT_PEND,
579 * CGEM_IDMA1_STAT_ACTV
580 *
581 * @b Affects
582 * @n CGEM_IDMA1_STAT_PEND=0,
583 * CGEM_IDMA1_STAT_ACTV=0
584 *
585 * @b Example
586 * @verbatim
588 #pragma DATA_ALIGN(src1, 8);
589 #pragma DATA_ALIGN(dst1, 8);
591 // Static 80 byte array of data in "src1" with known test pattern
592 Uint32 src1[20] =
593 {
594 0xDEADBEEF, 0xFADEBABE, 0x5AA51C3A, 0xD4536BA3,
595 0x5E69BA23, 0x4884A01F, 0x9265ACDA, 0xFFFF0123,
596 0xBEADDABE, 0x234A76B2, 0x9675ABCD, 0xABCDEF12,
597 0xEEEECDEA, 0x01234567, 0x00000000, 0xFEEDFADE,
598 0x0A1B2C3D, 0x4E5F6B7C, 0x5AA5ECCE, 0xFABEFACE
599 };
600 Uint32 dst1[20];
601 CSL_IDMA_IDMA1CONFIG idmaChan1Config;
602 Uint32 bWaitEnable = 0;
604 idmaChan1Config.source = src1;
605 idmaChan1Config.destn = dst1;
606 idmaChan1Config.intEnable = 1;
607 idmaChan1Config.priority = IDMA_PRI_7;
608 idmaChan1Config.count = DATA_COUNT_BYTES;
610 CSL_IDMA_chan1TransferData (&idmaChan1Config, bWaitEnable);
612 CSL_IDMA_chan1Wait();
614 ...
616 @endverbatim
617 * =============================================================================
618 */
619 static inline void CSL_IDMA_chan1Wait (
620 void
621 )
622 {
623 volatile Uint32 pend;
625 while( (pend = ( CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_PEND) |
626 CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_ACTV)
627 )
628 )
629 );
631 return;
632 }
635 /** ============================================================================
636 * @n@b CSL_IDMA_chan1GetStatus
637 *
638 * @b Description
639 * @n This function waits until all previous transfers for IDMA Channel
640 * 1 have been completed by making sure that both active and pend
641 * bits are zero. These are the two least significant bits of the
642 * status register for the channel.
643 *
644 * Waits until previous transfers have completed for IDMA channel 1
645 * before returning.
646 *
647 * @b Arguments
648 @verbatim
649 idmaChanStatus CSL_IDMA_STATUS structure pointer that needs to
650 be populated with iDMA Channel 1 transfer status.
651 @endverbatim
652 *
653 * <b> Return Value </b>
654 * @n None
655 *
656 * <b> Pre Condition </b>
657 * @n None.
658 *
659 * <b> Post Condition </b>
660 * @n None
661 *
662 * @b Reads
663 * @n CGEM_IDMA1_STAT_PEND,
664 * CGEM_IDMA1_STAT_ACTV
665 *
666 * @b Example
667 * @verbatim
668 CSL_IDMA_STATUS idma1Status;
670 CSL_IDMA_chan1GetStatus (&idma1Status);
672 @endverbatim
673 * =============================================================================
674 */
675 static inline void CSL_IDMA_chan1GetStatus (
676 CSL_IDMA_STATUS* idmaChanStatus
677 )
678 {
679 idmaChanStatus->isPending = CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_PEND);
680 idmaChanStatus->isActive = CSL_FEXT(hIdma->IDMA1_STAT, CGEM_IDMA1_STAT_ACTV);
682 return;
683 }
686 #ifdef __cplusplus
687 }
688 #endif
690 /** @} */
692 #endif /*CSL_IDMAAUX_H_*/