[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_2_eng / packages / ti / board / diag / hdmi / src / evmk2g_dss.h
1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 * \file evmk2g_dss.h
36 *
37 * \brief This file contains DSS specific structure, typedefs, function
38 * prototypes.
39 *
40 */
42 #ifndef _EVMK2G_DSS_H_
43 #define _EVMK2G_DSS_H_
45 /*******************************************************************************
46 * MACRO DEFINITIONS
47 *******************************************************************************/
48 /*****************************************************************************/
50 #undef DISPLAY_LOGO
52 /** Return values */
53 #define DSS_RET_OK (0)
54 #define DSS_RET_FAILED (1)
57 /** Predefined constants*/
59 /** Base address of the DSS module, 0x02540000 for Galileo */
60 #define DSS_BASE_ADDRESS (CSL_DSSUL_0_CFG_REGS)
62 /** Base address of the remote frame buffer (RFBI) registers */
63 #define DSS_RFBI_BASE_ADDRESS (DSS_BASE_ADDRESS + 0x6000)
65 /** Base address of the common display controller (DISPC) registers */
66 #define DSS_DISPC_BASE_ADDRESS (DSS_BASE_ADDRESS + 0x10000)
68 /** Base address of the video pipeline (VID) registers */
69 #define DSS_VID_BASE_ADDRESS (DSS_BASE_ADDRESS + 0x17000)
71 /** Base address of the overlay manager (OVR) registers */
72 #define DSS_OVR_BASE_ADDRESS (DSS_BASE_ADDRESS + 0x1A800)
74 /** Base address of the cursor pipeline (VP) registers */
75 #define DSS_VP_BASE_ADDRESS (DSS_BASE_ADDRESS + 0x1AC00)
77 /** Base address of the chip level register */
78 #define CHIP_LEVEL_REG (0x02620000)
80 #define KICK0_BASE_ADDRESS (CHIP_LEVEL_REG + 0x0038)
81 #define KICK1_BASE_ADDRESS (CHIP_LEVEL_REG + 0x003C)
82 #define KICK0_UNLOCK (0x83E70B13)
83 #define KICK1_UNLOCK (0x95A4F1E0)
84 #define KICK_LOCK (0)
86 /** Initiator Priority Register */
87 #define INITIATOR_PRIORITY_1_OFFSET (0x158)
88 #define DSS_INITIATOR_LOPRI_SHIFT (0)
89 #define DSS_INITIATOR_LOPRI_MASK (0x00000007)
90 #define DSS_INITIATOR_HIPRI_SHIFT (4)
91 #define DSS_INITIATOR_HIPRI_MASK (0x00000070)
93 /** ARMPLL definitions */
94 #define SEC_PLLCTL0_PLLM_OFFSET (6)
95 #define SEC_PLLCTL0_PLLM_MASK (0xFFFF003F)
96 #define SEC_PLLCTL0_BWADJ_OFFSET (24)
97 #define SEC_PLLCTL0_BWADJ_MASK (0x00FFFFFF)
98 #define SEC_PLLCTL0_OD_OFFSET (19)
99 #define SEC_PLLCTL0_OD_MASK (0xFF87FFFF)
100 #define SEC_PLLCTL0_BYPASS_OFFSET (23)
101 #define SEC_PLLCTL0_BYPASS_MASK (0xFF7FFFFF)
102 #define SEC_PLLCTL1_RESET_OFFSET (14)
103 #define SEC_PLLCTL1_RESET_MASK (0xFFFFBFFF)
104 #define SEC_PLLCTL1_PWRDWN_OFFSET (15)
105 #define SEC_PLLCTL1_PWRDWN_MASK (0xFFFF7FFF)
106 #define SEC_PLLCTL1_ENSTAT_OFFSET (6)
107 #define SEC_PLLCTL1_ENSTAT_MASK (0xFFFFFFBF)
109 #define DSS_PLL_CTL0_BYPASS_EN (1)
110 #define DSS_PLL_CTL0_BYPASS_DIS (0)
111 #define DSS_PLL_CTL0_BYPASS_SHIFT (23)
112 #define DSS_PLL_CTL0_BYPASS_MASK (0x00000000)
113 #define DSS_PLL_CTL0_CLKOD_SHIFT (19)
114 #define DSS_PLL_CTL0_CLKOD_MASK (0x00780000)
115 #define DSS_PLL_CTL0_PLLM_SHIFT (6)
116 #define DSS_PLL_CTL0_PLLM_MASK (0x0007FFC0)
117 #define DSS_PLL_CTL0_PLLD_SHIFT (0)
118 #define DSS_PLL_CTL0_PLLD_MASK (0x0000003F)
120 #define DSS_DISPC_VID_BUFFER0 (0)
121 #define DSS_DISPC_VID_BUFFER1 (1)
123 /** 4096 possible*/
124 #define DSS_DISPC_VID_WINDOW_XPOS_MAX (1920)
126 /** 4096 possible*/
127 #define DSS_DISPC_VID_WINDOW_YPOS_MAX (1080)
129 #define DSS_DISPC_VID_SIZE_X_MIN (1)
130 #define DSS_DISPC_VID_SIZE_X_MAX (4096)
131 #define DSS_DISPC_VID_SIZE_Y_MIN (1)
132 #define DSS_DISPC_VID_SIZE_Y_MAX (4096)
134 #define DSS_DISPC_VID_NIBBLE_MODE_DISABLE (0)
135 #define DSS_DISPC_VID_NIBBLE_MODE_ENABLE (1)
137 #define DSS_DISPC_VID_FMT_RGBA32U (0x09)
138 #define DSS_DISPC_VID_FMT_RGB24U (0x0B)
139 #define DSS_DISPC_VID_FMT_RGB32U (0x27)
140 #define DSS_DISPC_VID_FMT_BGRA32U (0x0A)
141 #define DSS_DISPC_VID_FMT_ABGR32U (0x08)
143 #define DSS_LCD_TYPE_PASSIVE (0)
144 #define DSS_LCD_TYPE_ACTIVE (1)
145 #define DSS_LCD_DISPLAY_MONO (1)
147 /** The max is really 4096 but recommended to stay below 512 for low jitter*/
148 #define DSS_PLL_MULTIPLIER_MAX (512)
149 #define DSS_PLL_REF_DIVIDER_MAX (64)
150 #define DSS_PLL_OUTPUT_DIVIDER_MAX (16)
152 #define DSS_PROG_LINE_NUMBER (100)
154 #define MAX_LCD_WIDTH (1920)
155 #define MAX_LCD_HEIGHT (1080)
157 #define CSL_ARM_GIC_DSS_INT (0x000000F7)
158 #define CSL_CIC_DSS_INT (0x0000005F)
160 /** IMAGE GENERATION SPECIFIC */
161 #define RGB888_CONSTANT (0x00000001)
162 #define RGB888_GENERATE (0x00000002)
163 #define RGB888_ADDRESS (0x00000003)
164 #if 0
165 #define BLACK (0x00000000)
166 #define WHITE (0x00FFFFFF)
167 #define BLUE (0x000000FF)
168 #define GREEN (0x0000FF00)
169 #define RED (0x00FF0000)
170 #define PURPLE (0x00A020F0)
171 #define PINK (0x00FFC0CB)
172 #define YELLOW (0x00FFFF00)
173 #else
174 #define BLACK (0x00000000)
175 #define WHITE (0x00FFFFFF)
176 #define BLUE (0x00FF0000)
177 #define GREEN (0x0000FF00)
178 #define RED (0x000000FF)
179 #define PURPLE (0x00F020A0)
180 #define PINK (0x00CBC0FF)
181 #define YELLOW (0x0000FFFF)
182 #endif
183 /** Frame address */
184 #define DDR_FRAME_ADDRESS_START (0x88000000)
185 #define DDR_FRAME_ADDRESS_END (0x88FFFFFF)
187 /** CSL Definitions for VPCFG */
188 #define CSL_DSSVP_CONTROL_LCDEN_SHIFT (0u)
189 #define CSL_DSSVP_CONTROL_LCDEN_MASK (0x00000001u)
190 #define CSL_DSSVP_CONTROL_LCDEN_RESETVAL (0x00000000u)
191 #define CSL_DSSCOMMON_DISPC_SYSCONFIG_SOFTRESET (1)
193 /** Display Video priority macros */
194 #define DSS_DISPC_VID_PRIORITY_NORMAL (0)
195 #define DSS_DISPC_VID_PRIORITY_HIGH (1)
198 /*---------------------------------------------------------------------------*/
199 /* Data Structure */
200 /*---------------------------------------------------------------------------*/
201 /*
202 * Configuration parameters specific to each LCD panel
203 */
204 typedef struct _lcdCfg_t
205 {
206 Uint32 LcdWidth; /**< Pixels per line (PPL) */
207 Uint32 LcdHeight; /**< Lines per panel (LPP) */
208 Uint32 LcdPclk; /**< Pixel clock (PCLK) */
209 Uint32 HsyncWidth; /**< Horizontal Sync Width (HSW) */
210 Uint32 HFrontPorch; /**< Horizontal front porch (HFP)*/
211 Uint32 HBackPorch; /**< Horizontal back porch (HBP)*/
212 Uint32 VsyncWidth; /**< Vertical sync width (VSW) */
213 Uint32 VFrontPorch; /**< Vertical front porch (VFP) */
214 Uint32 VBackPorch; /**< Vertical back porch (VBP) */
215 }lcdCfg_t;
217 /*
218 * Configuration parameters for the Display Controller (DISPC)
219 */
220 typedef struct _dispCfg_t
221 {
222 Uint32 displayType; /**< Active or Passive display? */
223 Uint32 colorMode; /**< Monochrome or Color? */
224 Uint32 dataLines; /**< How many LCD data lines? */
225 Uint32 mono8Bit;
227 }dispCfg_t;
229 /*
230 * Control signal configuration parameters
231 */
232 typedef struct _tmgCfg_t
233 {
234 Uint32 hsyncPolarity;
235 Uint32 vsyncPolarity;
236 Uint32 outputEnablePolarity;
237 Uint32 syncEdge;
238 Uint32 syncEdgeCtrl;
239 Uint32 pclkPolarity;
240 Uint32 acbFrequency;
241 Uint32 acbi;
242 Uint32 hsyncGated;
243 Uint32 vsyncGated;
244 Uint32 acbGated;
245 Uint32 pixelClkGated;
246 }tmgCfg_t;
248 /*
249 * Video pipeline DMA configuration
250 */
251 typedef struct _dmaCfg_t
252 {
253 Uint32 fifoLoThr;
254 Uint32 fifoHiThr;
255 Uint32 pixelInc;
256 Uint32 rowInc;
257 Uint32 preloadSelect;
258 Uint32 mflagLoThr;
259 Uint32 mflagHiThr;
260 Uint32 mflagAttrControl;
261 Uint32 mflagAttrStart;
262 Uint32 dssInitiatorPri_Hi;
263 Uint32 dssInitiatorPri_Lo;
264 }dmaCfg_t;
266 /*
267 * Video pipeline DMA configuration
268 */
269 typedef struct _dssInfo_t
270 {
271 lcdCfg_t lcdCfg;
272 dispCfg_t dispCfg;
273 tmgCfg_t tmgCfg;
274 dmaCfg_t vidDmaCfg;
276 }dssInfo_t;
278 /*---------------------------------------------------------------------------*/
279 /* Global Variables */
280 /*---------------------------------------------------------------------------*/
282 /** Type of the Return value for the functions */
283 typedef uint16_t DSS_RET;
285 /*---------------------------------------------------------------------------*/
286 /* Function Prototypes */
287 /*---------------------------------------------------------------------------*/
289 /**
290 * \brief Configures panel specific timing parameters
291 *
292 * This function configures the DSS Initiator priority
293 *
294 * \param baseAddr [IN] base address of DSSUL Video port register
295 * \param pLcdCfg [IN] pointer to LCD configuration
296 *
297 * \return
298 * DSS_RET_OK - if configuration is success
299 * DSS_RET_FAILED - if configuration is failed
300 */
301 DSS_RET dssDispcLcdPanelCfg(Uint32 baseAddr, lcdCfg_t *pCfg);
303 /**
304 * \brief Configures LCD color attributes
305 *
306 * This function configures the LCD color attributes
307 *
308 * \param baseAddr [IN] base address of DSSUL Video port register
309 * \param pDispCfg [IN] pointer to LCD configuration
310 *
311 * \return
312 * DSS_RET_OK - if configuration is success
313 * DSS_RET_FAILED - if configuration is failed
314 */
315 DSS_RET dssDispcLcdDisplayAttribCfg(Uint32 baseAddr,
316 dispCfg_t *pCfg);
318 /**
319 * \brief Configures control signal polarities
320 *
321 * This function configures the control signal polarities
322 *
323 * \param baseAddr [IN] base address of DSSUL Video port register
324 * \param pTmgCfg [IN] pointer to timing configuration
325 *
326 * \return
327 * DSS_RET_OK - if configuration is success
328 * DSS_RET_FAILED - if configuration is failed
329 */
330 DSS_RET dssDispcLcdTimingCfg(Uint32 baseAddr,
331 tmgCfg_t *pCfg);
333 /**
334 * \brief Initialize the Frame buffer
335 *
336 * This function performs initialization of frame buffer, loading of color bar
337 * information to the frame buffer or loading a constant value to the frame
338 * buffer.
339 *
340 * \param mode [IN] mode of operation for frame buffer
341 * \param height [IN] height of the frame buffer
342 * \param width [IN] width of the frame buffer
343 *
344 * \return NONE
345 */
346 void dssInitFrameBuffer(Uint32 mode, Uint32 width, Uint32 height);
348 /**
349 * \brief Puts the given color to the frame buffer
350 *
351 * This function puts the color passed as parameter to the
352 * frame buffer to display the given color. This function is
353 * used to test the LCD, frame buffer by passing any desired
354 * color.
355 *
356 * \param plcdCfg [IN] pointer to lcdCfg to get height and width
357 * \param color [IN] color to be displayed on the Display panel
358 *
359 * \return NONE
360 */
361 void dssFrameBufferColor(lcdCfg_t *pCfg, Uint32 color);
363 #ifdef DISPLAY_LOGO
364 void dssFillFrameBuffer(void);
365 #endif
367 /**
368 * \brief Disables ST Dithering
369 *
370 * This function Disables ST Dithering
371 *
372 * \param baseAddr [IN] base address of DSSUL register
373 *
374 * \return
375 * NONE
376 */
377 void dssDispcSTDitheringDisable(Uint32 baseAddr);
379 /**
380 * \brief Bypasses RFBI mode
381 *
382 * This function bypasses RFBI mode
383 *
384 * \param baseAddr [IN] base address of DSSUL register
385 *
386 * \return
387 * NONE
388 */
389 void dssDispcRfbiModeBypass(Uint32 baseAddr);
391 /**
392 * \brief Clear existing interrupts
393 *
394 * This function clears the interrupt status
395 *
396 * \param baseAddr [IN] base address of DSSUL register
397 * \param intFlag [IN] interrupt flag to be cleared
398 *
399 * \return
400 * NONE
401 */
402 void dssDispcIntStatusClearEx(Uint32 baseAddr, Uint32 intFlag);
404 /**
405 * \brief Configures the line number that generates interrupt
406 *
407 * This function configures the line number that generates interrupt
408 *
409 * \param baseAddr [IN] base address of DSSUL register
410 * \param lineNumber [IN] line number that generates interrupt
411 *
412 * \return
413 * NONE
414 */
415 void dssDispcProgLineNumberSet(Uint32 baseAddr, Uint32 lineNumber);
417 /**
418 * \brief Enable/Disable DPI Control
419 *
420 * This function enables/disables DPI interface from the registers
421 *
422 * \param baseAddr [IN] base address of DSSUL register
423 * \param enableFlag [IN] flag to indicate enable/disable
424 *
425 * \return
426 * NONE
427 */
428 void dssDpiCtrl(Uint32 baseAddr, Uint32 enableFlag);
430 /**
431 * \brief Update shadow registers, set the Go bit
432 *
433 * This function updates shadow registers and sets the GO bit
434 *
435 * \param baseAddr [IN] base address of Video Port register
436 *
437 * \return
438 * NONE
439 */
440 void dssDispcShadowCfgEnable(Uint32 baseAddr);
442 /**
443 * \brief Enable LCD output
444 *
445 * This function enables/disables LCD output
446 *
447 * \param baseAddr [IN] base address of Video Port register
448 * \param enableFlag [IN] flag to indicate enable/disable
449 *
450 * \return
451 * NONE
452 */
453 void dssDispcLcdOutputEnableCtrl(Uint32 baseAddr, Uint32 enableFlag);
455 /**
456 * \brief Performs software reset of the Display Controller
457 *
458 * This function performs software reset of the display controller.
459 *
460 * \param baseAddr [IN] base address of Video Port register
461 *
462 * \return
463 * NONE
464 */
465 void dssDispcSoftReset(Uint32 baseAddr);
467 /**
468 * \brief Enable/Disable the auto-idle function
469 *
470 * This function enables/disables the auto idle function of the Display controller
471 *
472 * \param baseAddr [IN] base address of Video Port register
473 * \param enableFlag [IN] flag to indicate enable/disable
474 *
475 * \return
476 * NONE
477 */
478 void dssDispcAutoIdleEnableCtrl(Uint32 baseAddr, Uint32 enableFlag);
480 /**
481 * \brief Configures DISPC_GLOBAL_MFLAG_ATTRIBUTE Register
482 *
483 * This function configures the Mflag attribute configuratin
484 *
485 * \param baseAddr [IN] base address of DSSUL Video config register
486 * \param lo_threshold [IN] value of low threshold
487 * \param hi_threshold [IN] value of high threshold
488 *
489 * \return
490 * DSS_RET_OK - if configuration is success
491 * DSS_RET_FAILED - if configuration is failed
492 */
493 DSS_RET dssDispcMflagThresholdCfg(Uint32 baseAddr, Uint32 lo_threshold,
494 Uint32 hi_threshold);
496 /**
497 * \brief Configures DISPC_GLOBAL_MFLAG_ATTRIBUTE Register
498 *
499 * This function configures the Mflag attribute configuratin
500 *
501 * \param baseAddr [IN] base address of DSSUL Common cfg register
502 * \param start [IN] value of MFlag START to be configured
503 * \param control [IN] value of MFlag control to be configured
504 *
505 * \return
506 * DSS_RET_OK - if configuration is success
507 * DSS_RET_FAILED - if configuration is failed
508 *
509 */
510 DSS_RET dssDispcMflagAttributeCfg(Uint32 baseAddr, Uint32 start, Uint32 control);
512 /**
513 * \brief Configures the DSS initiator priority
514 *
515 * This function configures the DSS Initiator priority
516 *
517 * \param baseAddr [IN] base address of DSSUL Video config register
518 * \param lo_threshold [IN] value of low threshold
519 * \param hi_threshold [IN] value of high threshold
520 *
521 * \return
522 * DSS_RET_OK - if configuration is success
523 * DSS_RET_FAILED - if configuration is failed
524 */
525 DSS_RET dssInitiatorPriorityCfg(Uint32 baseAddr, Uint32 lo_priority,
526 Uint32 hi_priority);
528 /**
529 * \brief Configure video pipeline DMA specific parameters
530 *
531 * This function configures video pipeline DMA specific parameters
532 *
533 * \param baseAddr [IN] base address of Video Port register
534 * \param pDmaCfg [IN] pointer to DMA configuration
535 *
536 * \return
537 * DSS_RET_OK - if configuration is success
538 * DSS_RET_FAILED - if configuration is failed
539 */
540 DSS_RET dssDispcVidDMAConfig(Uint32 baseAddr, dmaCfg_t *pCfg);
542 /**
543 * \brief Video pipeline interrupt enable
544 *
545 * This function enables video pipeline interrupt
546 *
547 * \param baseAddr [IN] base address of Video pipeline register
548 * \param intFlag [IN] interrupt flag to enable
549 *
550 * \return
551 * NONE
552 */
553 void dssDispcVidIntEnable(Uint32 baseAddr, Uint32 intFlag);
555 /**
556 * \brief Video pipeline interrupt disable
557 *
558 * This function disables video pipeline interrupt
559 *
560 * \param baseAddr [IN] base address of Video pipeline register
561 * \param intFlag [IN] interrupt flag to disable
562 *
563 * \return
564 * NONE
565 */
566 void dssDispcVidIntDisable(Uint32 baseAddr, Uint32 intFlag);
568 /**
569 * \brief Enable the video pipeline
570 *
571 * This function enables/disables the video pipeline
572 *
573 * \param baseAddr [IN] base address of Video Port register
574 * \param enableFlag [IN] flag to indicate enable/disable
575 *
576 * \return
577 * NONE
578 */
579 void dssDispcVidEnableCtrl(Uint32 baseAddr, Uint32 enableFlag);
581 /**
582 * \brief VP interrupt enable
583 *
584 * This function enables VP interrupt
585 *
586 * \param baseAddr [IN] base address of Video Port register
587 * \param intFlag [IN] interrupt flag to be enabled
588 *
589 * \return
590 * NONE
591 */
592 void dssDispcVPIntEnable(Uint32 baseAddr, Uint32 intFlag);
594 /**
595 * \brief VP interrupt disable
596 *
597 * This function disables VP interrupt
598 *
599 * \param baseAddr [IN] base address of Video Port register
600 * \param intFlag [IN] interrupt flag to be disabled
601 *
602 * \return
603 * NONE
604 */
605 void dssDispcVPIntDisable(Uint32 baseAddr, Uint32 intFlag);
607 /**
608 * \brief Enable interrupts to VID or VP
609 *
610 * This function enables interrupts to VID or VP
611 *
612 * \param baseAddr [IN] base address of Video Port register
613 * \param intFlag [IN] interrupt flag to be enabled
614 *
615 * \return
616 * NONE
617 */
618 void dssDispcCommonIntEnable(Uint32 baseAddr, Uint32 intFlag);
620 /**
621 * \brief Update shadow registers, set the Go bit
622 *
623 * This function updates shadow registers and sets the GO bit
624 *
625 * \param baseAddr [IN] base address of Video Port register
626 *
627 * \return
628 * NONE
629 */
630 void dssDispcShadowCfgEnable(Uint32 baseAddr);
632 /**
633 * \brief Erase frame buffer
634 *
635 * \param baseAddr [IN] base address of Video Port register
636 * \param enableFlag [IN] flag to indicate enable/disable
637 *
638 * \return
639 * NONE
640 */
641 void dssEraseBuffer(lcdCfg_t *pCfg);
643 /**
644 * \brief Set priority of Vid DMA
645 *
646 * This function set the priority of Video DMA
647 *
648 * \param baseAddr [IN] base address of Video Port register
649 * \param priorityFlag [IN] flag to indicate priority
650 *
651 * \return
652 * NONE
653 */
654 void dssDispcVidPrioritySet(Uint32 baseAddr, Uint32 priorityFlag);
656 /**
657 * \brief Enable/Disable self refresh
658 *
659 * This function enables/disables the self refresh
660 *
661 * \param baseAddr [IN] base address of Video Port register
662 * \param enableFlag [IN] flag to indicate enable/disable
663 *
664 * \return
665 * NONE
666 */
667 void dssDispcVidSelfRefEnableCtrl(Uint32 baseAddr, Uint32 enableFlag);
669 /**
670 * \brief Configure base address of frame buffer
671 *
672 * This function configures the base address of frame buffer
673 *
674 * \param baseAddr [IN] base address of Video Port register
675 * \param bufAddr [IN] buffer address
676 * \param bufSelectFlag [IN] buffer select flag
677 *
678 * \return
679 * NONE
680 */
681 void dssDispcVidSetBufAddr(Uint32 baseAddr, Uint32 bufAddr,
682 Uint32 bufSelectFlag);
684 /**
685 * \brief Configure video window position
686 *
687 * This function configures the video window position
688 *
689 * \param baseAddr [IN] base address of Video Port register
690 * \param xPos [IN] X position of video window
691 * \param yPos [IN] Y position of video window
692 *
693 * \return
694 * DSS_RET_OK - if configuration is success
695 * DSS_RET_FAILED - if configuration is failed
696 */
697 DSS_RET dssDispcVidOvlyPositionCfg(Uint32 baseAddr, Uint32 xPos, Uint32 yPos);
699 /**
700 * \brief Configure video window size
701 *
702 * This function configures the video window size
703 *
704 * \param baseAddr [IN] base address of Video Port register
705 * \param width [IN] Video width
706 * \param height [IN] Video height
707 *
708 * \return
709 * DSS_RET_OK - if configuration is success
710 * DSS_RET_FAILED - if configuration is failed
711 */
712 DSS_RET dssDispcVidSizeCfg(Uint32 baseAddr, Uint32 width, Uint32 height);
714 /**
715 * \brief Configure video window data format
716 *
717 * This function configures the video window data format
718 *
719 * \param baseAddr [IN] base address of Video Port register
720 * \param format [IN] format to be configured
721 * \param nibbleModen [IN] Nibble mode
722 *
723 * \return
724 * NONE
725 */
726 void dssDispcVidFormatSet(Uint32 baseAddr, Uint32 format, Uint32 nibbleModen);
728 #if (PLATFORM_DEBUG)
729 /**
730 * \brief DSS Register Dump
731 *
732 * This function dumps the DSS module register values
733 *
734 * \param dssInfo [IN] dssInfo structure passed from LCD panel init
735 *
736 * \return none
737 *
738 */
739 void dssDumpReg(dssInfo_t *dssInfo);
740 /**
741 * \brief DSS Initialization
742 *
743 * This function initializes the DSS module with the given LCD panel
744 * information, Timing configuration, Display configuration and DMA
745 * configuration.
746 *
747 * \param dssInfo [IN] dssInfo structure passed from LCD panel init
748 *
749 * \return
750 * DSS_RET_OK - status to indicate success
751 * DSS_RET_FAILED - if DSS failed to initialize, returns failure.
752 *
753 */
754 #endif
755 DSS_RET dssInit(dssInfo_t *dssInfo);
757 #endif // _EVMK2G_DSS_H_