[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_2_eng / packages / ti / board / diag / qspi / src / qspi_diag.c
2 /*
3 * Copyright (c) 2014, Texas Instruments Incorporated
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * * Neither the name of Texas Instruments Incorporated nor the names of
18 * its contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
23 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
25 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
26 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
31 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
34 /* TI-RTOS Header files */
35 #include <ti/drv/uart/UART.h>
36 #include <ti/drv/uart/UART_stdio.h>
37 #if !defined (SOC_K2G)
38 #include <ti/csl/soc/am572x/src/cslr_control_core_pad_io.h>
39 #endif
40 #include <stdlib.h>
42 #if defined(SOC_K2G)
43 #include <ti/csl/soc.h>
44 #include <ti/drv/spi/SPI.h>
45 #include <ti/drv/spi/soc/SPI_soc.h>
46 #else
47 #include <ti/drv/spi/SPI.h>
48 #include <ti/drv/spi/soc/QSPI_v1.h>
49 #include <ti/drv/spi/soc/SPI_v1.h>
50 #include <ti/drv/spi/soc/QSPI_v1.h>
51 #endif
53 /* Flash header file */
54 #if defined(SOC_K2G)
55 #include "qspi_nor.h"
56 #else
57 #include "qspi_flash.h"
58 #endif
60 #include "board.h"
61 #include "board_cfg.h"
63 #if !defined(SOC_K2G)
64 /**********************************************************************
65 ************************** Macros ************************************
66 **********************************************************************/
67 /* control module register definitions */
68 #define SOC_CORE_PAD_IO_REGISTERS_BASE (0x4a003400U)
69 #define CTRL_CORE_PAD_GPMC_A13 (0x74U) //QSPI_RTCLK
70 #define CTRL_CORE_PAD_GPMC_A14 (0x78U) //QSPI_D3
71 #define CTRL_CORE_PAD_GPMC_A15 (0x7CU) //QSPI_D2
72 #define CTRL_CORE_PAD_GPMC_A16 (0x80U) //QSPI_D0
73 #define CTRL_CORE_PAD_GPMC_A17 (0x84U) //QSPI_D1
74 #define CTRL_CORE_PAD_GPMC_A18 (0x88U) //QSPI_CLK
75 #define CTRL_CORE_PAD_GPMC_CS2 (0xB8U) //QSPI_CSn
76 #define CTRL_CORE_PAD_GPMC_CS3 (0xBCU) //QSPI_CSn
77 #define CTRL_CORE_PAD_GPMC_A3 (0x4CU) //QSPI_CSn
78 #define CTRL_CORE_PAD_GPMC_A4 (0x50U) //QSPI_CSn
80 #define CTRL_CORE_PAD_GPMC_A14_PULLUP_RX_MODE_1 (0x00060001U)
81 #define CTRL_CORE_PAD_GPMC_A15_PULLUP_RX_MODE_1 (0x00060001U)
82 #define CTRL_CORE_PAD_GPMC_A16_PULLUP_RX_MODE_1 (0x00060001U)
83 #define CTRL_CORE_PAD_GPMC_A17_PULLUP_RX_MODE_1 (0x00060001U)
84 #define CTRL_CORE_PAD_GPMC_A18_PULLUP_MODE_1 (0x00020001U)
85 #define CTRL_CORE_PAD_GPMC_CS2_PULLUP_MODE_1 (0x00020001U)
86 #define CTRL_CORE_PAD_GPMC_A13_PULLUP_MODE_1 (0x00020001U)
87 #define CTRL_CORE_PAD_GPMC_CS3_PULLUP_MODE_1 (0x00020001U)
88 #define CTRL_CORE_PAD_GPMC_A3_PULLUP_MODE_1 (0x00020001U)
89 #define CTRL_CORE_PAD_GPMC_A4_PULLUP_MODE_1 (0x00020001U)
90 #endif
92 #define HW_WR_REG32(addr, data) *(unsigned int*)(addr) =(unsigned int)(data)
95 /* Board specific definitions */
96 #define QSPI_FLSASH_INSTANCE (0U)
97 #define QSPI_PER_CNT (1U)
99 #define QSPI_INSTANCE (1U)
100 #define QSPI_OFFSET (4U)
102 #define CSL_MCSPI_PER_CNT (4U)
103 #define CSL_QSPI_PER_CNT 1U
105 /**********************************************************************
106 ************************** Internal functions ************************
107 **********************************************************************/
109 extern void PinmuxConfig(void);
111 /* Function to generate known data */
112 static void GeneratePattern(uint8_t *txBuf, uint8_t *rxBuf, uint32_t length);
114 /* Data compare function */
115 bool VerifyData(unsigned char *expData,
116 unsigned char *rxData,
117 unsigned int length);
120 /**********************************************************************
121 ************************** Global Variables **************************
122 **********************************************************************/
124 /* Buffer containing the known data that needs to be written to flash */
125 unsigned int txBuf[1024];
127 /* Buffer containing the received data */
128 unsigned int rxBuf[1024];
130 /* Flash offset address to which data write/read has to be performed */
131 unsigned int addrValue = 0x000000U;
133 extern const SPI_Config SPI_config[];
135 /* transfer length */
136 uint32_t transferLength = 0;
138 /*
139 * ======== test function ========
140 */
141 #if defined (SOC_K2G)
142 int spi_test()
143 {
144 SPI_Params spiParams; /* SPI params structure */
145 FLASH_HANDLE flashHandle; /* Flash handle */
146 unsigned int blockNumber = 0U; /* Block number */
147 SPI_Handle handle; /* SPI handle */
148 bool retVal = false; /* return value */
149 uint32_t addressValue; /* address parameter */
150 int i;
151 uint8_t idCode[4]; /* Buffer to hold flash ID */
153 for (i=0; i<CSL_SPI_CNT; i++)
154 {
155 ((SPI_v0_HWAttrs *)SPI_config[i].hwAttrs)->enableIntr = false;
156 }
158 for (i=CSL_SPI_CNT; i<CSL_SPI_CNT+CSL_QSPI_PER_CNT; i++)
159 {
160 ((QSPI_v0_HwAttrs *)SPI_config[i].hwAttrs)->intrEnable = false;
161 }
163 /* Init SPI driver */
164 flashHandle = qspiNorInit(0, NULL);
166 /* Print flash Id */
167 qspiNorReadId(flashHandle, idCode);
169 /* Erase block, to which data has to be written */
170 qspiNorErase(flashHandle, blockNumber);
172 /* Set the transfer length in number of 32 bit words */
173 transferLength = 50;
175 /* Generate the data */
176 GeneratePattern((uint8_t *)&txBuf[0], (uint8_t *)&rxBuf[0], transferLength);
178 /* Write buffer to flash */
179 retVal = qspiNorWrite(flashHandle, blockNumber, transferLength, txBuf, QSPI_FLASH_QUAD_PAGE_PROG);
181 /* Read data from flash */
182 retVal = qspiNorRead(flashHandle, blockNumber, transferLength, rxBuf, QSPI_FLASH_QUAD_PAGE_PROG);
184 /* Verify Data */
185 retVal = VerifyData((unsigned char *)&txBuf[0], (unsigned char *)&rxBuf[0],
186 transferLength);
188 qspiNorClose(flashHandle);
190 if(true == retVal)
191 {
192 UART_printf("Test PASSED! \n");
193 return 0;
194 }
195 else
196 {
197 UART_printf("Data Mismatch\n");
198 UART_printf("Test Failed!\n");
199 return -1;
200 }
201 }
202 #else
203 int spi_test()
204 {
205 SPI_Params spiParams; /* SPI params structure */
206 S25FL_Handle flashHandle; /* Flash handle */
207 unsigned int blockNumber = 0U; /* Block number */
208 S25FL_Transaction flashTransaction; /* Flash transaction structure */
209 SPI_Handle handle; /* SPI handle */
210 QSPI_HwAttrs *hwAttrs; /* QSPI hardware attributes */
211 bool retVal = false; /* return value */
212 uint32_t addressValue; /* address parameter */
213 int i;
215 for (i=0; i<CSL_MCSPI_PER_CNT; i++)
216 {
217 ((SPI_v1_HWAttrs *)SPI_config[i].hwAttrs)->enableIntr = false;
218 }
220 for (i=CSL_MCSPI_PER_CNT; i<CSL_MCSPI_PER_CNT+CSL_QSPI_PER_CNT; i++)
221 {
222 ((QSPI_HwAttrs *)SPI_config[i].hwAttrs)->intrEnable = false;
223 }
226 /* Init SPI driver */
227 SPI_init();
229 /* Default SPI configuration parameters */
230 SPI_Params_init(&spiParams);
232 /* Open QSPI driver */
233 //flashHandle = SF25FL_open(0, &spiParams);
234 flashHandle = SF25FL_open(((QSPI_INSTANCE - 1)+(QSPI_OFFSET)), &spiParams);
236 /* Extract hardware attributes */
237 handle = flashHandle->spiHandle;
238 hwAttrs = (QSPI_HwAttrs *)handle->hwAttrs;
240 /* Print flash Id */
241 FlashPrintId(flashHandle);
243 /* Erase block, to which data has to be written */
244 S25FLFlash_BlockErase(flashHandle, blockNumber);
246 /* Set the transfer length in number of 32 bit words */
247 transferLength = 50;
249 /* Generate the data */
250 GeneratePattern((uint8_t *)&txBuf[0], (uint8_t *)&rxBuf[0], transferLength);
252 /* Update target address based on the modes. For config mode pass the
253 address of the variable containing the flash offset value.
254 For memory mapped mode directly pass the flash offset value. */
255 addressValue = (QSPI_OPER_MODE_CFG == hwAttrs->operMode) ?
256 (uint32_t)&addrValue: addrValue;
258 /* Update transaction parameters */
259 flashTransaction.data = (uint8_t *)&txBuf[0];
260 flashTransaction.address = addressValue;
261 flashTransaction.dataSize = transferLength * 4; /* In bytes */
263 /* Write buffer to flash */
264 retVal = SF25FL_bufferWrite(flashHandle, &flashTransaction);
266 if(QSPI_RX_LINES_QUAD == hwAttrs->rxLines)
267 {
268 S25FLFlash_QuadModeEnable(flashHandle);
269 }
271 /* Update transaction parameters */
272 flashTransaction.data = (uint8_t *)&rxBuf[0];
273 flashTransaction.address = addressValue;
274 flashTransaction.dataSize = transferLength * 4; /* In bytes */
276 /* Read data from flash */
277 retVal = SF25FL_bufferRead(flashHandle, &flashTransaction);
279 /* Verify Data */
280 retVal = VerifyData((unsigned char *)&txBuf[0], (unsigned char *)&rxBuf[0],
281 transferLength);
283 SF25FL_close(flashHandle);
285 if(true == retVal)
286 {
287 UART_printf("Test PASSED! \n");
288 return 0;
289 }
290 else
291 {
292 UART_printf("Data Mismatch\n");
293 UART_printf("Test Failed!\n");
294 return -1;
295 }
296 }
297 #endif
299 /*
300 * ======== CompareData ========
301 */
302 bool VerifyData(unsigned char *expData,
303 unsigned char *rxData,
304 unsigned int length)
305 {
306 unsigned int idx = 0;
307 unsigned int match = 1;
308 bool retVal = false;
309 #ifdef SOC_K2G
310 unsigned int lenInBytes = length;
311 #else
312 unsigned int lenInBytes = length * 4;
313 #endif
316 for(idx = 0; ((idx < lenInBytes) && (match != 0)); idx++)
317 {
318 if(*expData != *rxData) match = 0;
319 expData++;
320 rxData++;
321 }
323 if(match == 1) retVal = true;
325 return retVal;
326 }
328 /*
329 * ======== GeneratePattern ========
330 */
331 static void GeneratePattern(uint8_t *txBuf, uint8_t *rxBuf, uint32_t length)
332 {
333 unsigned int idx;
334 unsigned int lenInBytes = length * 4;
336 for(idx = 0; idx < lenInBytes; idx++)
337 {
338 txBuf[idx] = (uint8_t)idx;
339 rxBuf[idx] = (uint8_t)0U;
340 }
341 }
343 int qspi_test()
344 {
345 UART_printf("\n*********************************************\n");
346 UART_printf ("* QSPI Test *\n");
347 UART_printf ("*********************************************\n");
349 UART_printf("\nTesting QSPI read/write...\n");
351 return spi_test();
352 }
354 /*
355 * ======== main ========
356 */
357 int main(void)
358 {
359 Board_initCfg boardCfg;
360 #ifdef PDK_RAW_BOOT
361 boardCfg = BOARD_INIT_PINMUX_CONFIG |
362 BOARD_INIT_UART_STDIO;
363 #else
364 boardCfg = BOARD_INIT_UART_STDIO;
365 #endif
366 Board_init(boardCfg);
368 return qspi_test();
369 }