[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_2_eng / packages / ti / board / src / evmC6678 / evmC6678_ddr.c
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2 * Copyright (c) 2010-2015 Texas Instruments Incorporated - http://www.ti.com
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32 *****************************************************************************/
34 #include <ti/csl/csl_bootcfgAux.h>
35 #include <ti/csl/cslr_device.h>
36 #include <ti/csl/csl_xmcAux.h>
37 #include <ti/csl/csl_emif4fAux.h>
38 #include <ti/csl/hw_types.h>
40 #include "board_internal.h"
42 extern void BOARD_delay(uint32_t usecs);
44 static void xmc_add_emif_cfg_region()
45 {
46 /* mapping for ddr emif registers XMPAX*2 */
47 CSL_XMC_XMPAXL mpaxl;
48 CSL_XMC_XMPAXH mpaxh;
50 /* base addr + seg size (64KB)*/ //"1B"-->"B" by xj */
51 mpaxh.bAddr = (0x2100000B >> 12);
52 mpaxh.segSize = (0x2100000B & 0x0000001F);
54 /* replacement addr + perm*/
55 mpaxl.rAddr = 0x100000;
56 mpaxl.sr = 1;
57 mpaxl.sw = 1;
58 mpaxl.sx = 1;
59 mpaxl.ur = 1;
60 mpaxl.uw = 1;
61 mpaxl.ux = 1;
63 /* set the xmpax for index2 */
64 CSL_XMC_setXMPAXH(2, &mpaxh);
65 CSL_XMC_setXMPAXL(2, &mpaxl);
66 }
68 /* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
69 Board_STATUS Board_DDR3Init()
70 {
71 Board_STATUS status = BOARD_SOK;
72 uint32_t ddr3config, ddrPhyCtrl;
73 uint8_t ddrPHYReadLatency;
74 EMIF4F_TIMING1_CONFIG sdram_tim1;
75 EMIF4F_TIMING2_CONFIG sdram_tim2;
76 EMIF4F_TIMING3_CONFIG sdram_tim3;
77 EMIF4F_OUTPUT_IMP_CONFIG zqcfg;
78 EMIF4F_PWR_MGMT_CONFIG pwrmgmtcfg;
79 EMIF4F_SDRAM_CONFIG sdramcfg;
81 xmc_add_emif_cfg_region();
83 CSL_BootCfgUnlockKicker();
85 /**************** 3.3 Leveling Register Configuration ********************/
86 CSL_BootCfgGetDDRConfig(0, &ddr3config);
87 ddr3config &= ~(0x007FE000); // clear ctrl_slave_ratio field
88 CSL_BootCfgSetDDRConfig(0, ddr3config);
90 CSL_BootCfgGetDDRConfig(0, &ddr3config);
91 ddr3config |= 0x00200000; // set ctrl_slave_ratio to 0x100
92 CSL_BootCfgSetDDRConfig(0, ddr3config);
94 CSL_BootCfgGetDDRConfig(12, &ddr3config);
95 ddr3config |= 0x08000000; // Set invert_clkout = 1
96 CSL_BootCfgSetDDRConfig(12, ddr3config);
98 CSL_BootCfgGetDDRConfig(0, &ddr3config);
99 ddr3config |= 0xF; // set dll_lock_diff to 15
100 CSL_BootCfgSetDDRConfig(0, ddr3config);
102 CSL_BootCfgGetDDRConfig(23, &ddr3config);
103 ddr3config |= 0x00000200; // See section 4.2.1, set for partial automatic levelling
104 CSL_BootCfgSetDDRConfig(23, ddr3config);
106 /**************** 3.3 Partial Automatic Leveling ********************/
107 ddr3config = 0x0000005E;
108 CSL_BootCfgSetDDRConfig(2, ddr3config);
109 ddr3config = 0x0000005E;
110 CSL_BootCfgSetDDRConfig(3, ddr3config);
111 ddr3config = 0x0000005E;
112 CSL_BootCfgSetDDRConfig(4, ddr3config);
113 ddr3config = 0x00000051;
114 CSL_BootCfgSetDDRConfig(5, ddr3config);
115 ddr3config = 0x00000038;
116 CSL_BootCfgSetDDRConfig(6, ddr3config);
117 ddr3config = 0x0000003A;
118 CSL_BootCfgSetDDRConfig(7, ddr3config);
119 ddr3config = 0x00000024;
120 CSL_BootCfgSetDDRConfig(8, ddr3config);
121 ddr3config = 0x00000020;
122 CSL_BootCfgSetDDRConfig(9, ddr3config);
123 ddr3config = 0x00000044;
124 CSL_BootCfgSetDDRConfig(10, ddr3config);
126 ddr3config = 0x000000DD;
127 CSL_BootCfgSetDDRConfig(14, ddr3config);
128 ddr3config = 0x000000DD;
129 CSL_BootCfgSetDDRConfig(15, ddr3config);
130 ddr3config = 0x000000BE;
131 CSL_BootCfgSetDDRConfig(16, ddr3config);
132 ddr3config = 0x000000CA;
133 CSL_BootCfgSetDDRConfig(17, ddr3config);
134 ddr3config = 0x000000A9;
135 CSL_BootCfgSetDDRConfig(18, ddr3config);
136 ddr3config = 0x000000A7;
137 CSL_BootCfgSetDDRConfig(19, ddr3config);
138 ddr3config = 0x0000009E;
139 CSL_BootCfgSetDDRConfig(20, ddr3config);
140 ddr3config = 0x000000A1;
141 CSL_BootCfgSetDDRConfig(21, ddr3config);
142 ddr3config = 0x000000BA;
143 CSL_BootCfgSetDDRConfig(22, ddr3config);
145 /*Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0 */
146 CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
147 ddrPhyCtrl &= ~(0x00008000);
148 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
150 CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
151 ddrPhyCtrl |= (0x00008000);
152 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
154 CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
155 ddrPhyCtrl &= ~(0x00008000);
156 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
158 /***************** 3.4 Basic Controller and DRAM configuration ************/
159 /* enable configuration */
160 /* hEmif->SDRAM_REF_CTRL = 0x00005162; */
161 CSL_EMIF4F_EnableInitRefresh();
162 CSL_EMIF4F_SetRefreshRate(0x5162);
164 /* hEmif->SDRAM_TIM_1 = 0x1113783C; */
165 sdram_tim1.t_wtr = 4;
166 sdram_tim1.t_rrd = 7;
167 sdram_tim1.t_rc = 0x20;
168 sdram_tim1.t_ras = 0x17;
169 sdram_tim1.t_wr = 9;
170 sdram_tim1.t_rcd = 8;
171 sdram_tim1.t_rp = 8;
172 CSL_EMIF4F_SetTiming1Config(&sdram_tim1);
174 /* hEmif->SDRAM_TIM_2 = 0x30717FE3; */
175 sdram_tim2.t_cke = 3;
176 sdram_tim2.t_rtp = 4;
177 sdram_tim2.t_xsrd = 0x1FF;
178 sdram_tim2.t_xsnr = 0x071;
179 sdram_tim2.t_xp = 3;
180 sdram_tim2.t_odt = 0;
181 CSL_EMIF4F_SetTiming2Config(&sdram_tim2);
183 /* hEmif->SDRAM_TIM_3 = 0x559F86AF; */
184 sdram_tim3.t_rasMax = 0xF;
185 sdram_tim3.t_rfc = 0x06A;
186 sdram_tim3.t_tdqsckmax = 0;
187 sdram_tim3.zq_zqcs = 0x3F;
188 sdram_tim3.t_ckesr = 4;
189 sdram_tim3.t_csta = 0x5;
190 sdram_tim3.t_pdll_ul = 0x5;
191 CSL_EMIF4F_SetTiming3Config(&sdram_tim3);
193 /* hEmif->DDR_PHY_CTRL_1 = 0x0010010F; */
194 ddrPHYReadLatency = 0x0F;
195 ddrPhyCtrl = (0x08008);
196 CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);
198 /* hEmif->ZQ_CONFIG = 0x70073214; */
199 zqcfg.zqRefInterval = 0x3214;
200 zqcfg.zqZQCLMult = 3;
201 zqcfg.zqZQCLInterval = 1;
202 zqcfg.zqSFEXITEn = 1;
203 zqcfg.zqDualCSEn = 1;
204 zqcfg.zqCS0En = 1;
205 zqcfg.zqCS1En = 0;
206 CSL_EMIF4F_SetOutputImpedanceConfig(&zqcfg);
208 /* hEmif->PWR_MGMT_CTRL = 0x0; */
209 pwrmgmtcfg.csTime = 0;
210 pwrmgmtcfg.srTime = 0;
211 pwrmgmtcfg.lpMode = 0;
212 pwrmgmtcfg.dpdEnable = 0;
213 pwrmgmtcfg.pdTime = 0;
214 CSL_EMIF4F_SetPowerMgmtConfig(&pwrmgmtcfg);
216 /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 */
217 /* hEmif->SDRAM_CONFIG = 0x63062A32; */
218 CSL_EMIF4F_GetSDRAMConfig(&sdramcfg);
219 sdramcfg.pageSize = 2;
220 sdramcfg.eBank = 0;
221 sdramcfg.iBank = 3;
222 sdramcfg.rowSize = 4;
223 sdramcfg.CASLatency = 10;
224 sdramcfg.narrowMode = 0;
225 sdramcfg.CASWriteLat = 2;
226 sdramcfg.SDRAMDrive = 1;
227 sdramcfg.disableDLL = 0;
228 sdramcfg.dynODT = 0;
229 sdramcfg.ddrDDQS = 0;
230 sdramcfg.ddrTerm = 3;
231 sdramcfg.iBankPos = 0;
232 sdramcfg.type = 3;
233 CSL_EMIF4F_SetSDRAMConfig(&sdramcfg);
235 BOARD_delay(600); /*Wait 600us for HW init to complete*/
237 /* Refresh rate = (7.8*666MHz] */
238 /* hEmif->SDRAM_REF_CTRL = 0x00001450; */
239 CSL_EMIF4F_SetRefreshRate(0x00001450);
241 /***************** 4.2.1 Partial automatic leveling ************/
242 /* hEmif->RDWR_LVL_RMP_CTRL = 0x80000000; */
243 CSL_EMIF4F_SetLevelingRampControlInfo(1, 0, 0, 0, 0);
245 /* Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value */
246 /* hEmif->RDWR_LVL_CTRL = 0x80000000; */
247 CSL_EMIF4F_SetLevelingControlInfo(1, 0, 0, 0, 0);
249 /************************************************************
250 Wait for min 1048576 DDR clock cycles for leveling to complete
251 = 1048576 * 1.5ns = 1572864ns = 1.57ms.
252 Actual time = ~10-15 ms
253 **************************************************************/
254 BOARD_delay(3000); //Wait 3ms for leveling to complete
256 return status;
257 }