[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_2_eng / packages / ti / board / src / flash / platform_flash / evmc66x_gpmc.c
1 /*
2 * Copyright (c) 2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 *
36 * \file evm66x_gpmc.c
37 *
38 * \brief This contains C66x specific gpmc functions.
39 *
40 ******************************************************************************/
42 #include "platform_internal.h"
44 /**
45 * \brief This function reads the IP revision code of GPMC.\n
46 *
47 * \param hGpmc GPMC handle pointing to register base address.\n
48 *
49 * \return ipRev IP revision code of GPMC.\n
50 */
51 Uint32 GPMCRevisionGet(gpmcHandle hGpmc)
52 {
53 Uint32 ipRev;
55 ipRev = CSL_FEXT(hGpmc->REVISION, GPMC_REVISION_REV);
57 return (ipRev);
58 }
60 /**
61 * \brief This function sets the idle mode for gpmc.\n
62 *
63 * \param hGpmc GPMC handle pointing to register base address.\n
64 *
65 * \param mode Idle mode.\n
66 * This can take one of the following values :\n
67 * GPMC_IDLEMODE_FORCEIDLE -- for force-idle. \n
68 * GPMC_IDLEMODE_NOIDLE -- for no-idle. \n
69 * GPMC_IDLEMODE_SMARTIDLE -- for smart-idle.\n
70 */
71 void GPMCIdleModeSelect(gpmcHandle hGpmc, Uint32 mode)
72 {
73 CSL_FINS(hGpmc->SYSCONFIG, GPMC_SYSCONFIG_SIDLEMODE, mode);
74 }
76 /**
77 * \brief This function configs the internal OCP clock gating strategy.\n
78 *
79 * \param hGpmc GPMC handle pointing to register base address.\n
80 *
81 * \param configVal Config value.\n
82 * This can take one of the following values :\n
83 * GPMC_AUTOIDLE_FREERUN -- When Interface clock is
84 * free-running. \n
85 * GPMC_AUTOIDLE_AUTORUN -- When Automatic Interface clk
86 * gating strategy is applied.\n
87 *
88 * \return none.\n
89 */
90 void GPMCAutoIdleConfig(gpmcHandle hGpmc, Uint32 configVal)
91 {
92 CSL_FINS(hGpmc->SYSCONFIG, GPMC_SYSCONFIG_SIDLEMODE,
93 configVal);
94 }
96 /**
97 * \brief This function resets the GPMC.\n
98 *
99 * \param hGpmc GPMC handle pointing to register base address.\n
100 *
101 * \return None.\n
102 */
103 void GPMCModuleSoftReset(gpmcHandle hGpmc)
104 {
105 CSL_FINS(hGpmc->SYSCONFIG, GPMC_SYSCONFIG_SOFTRESET,
106 GPMC_BIT_SET_HIGH);
107 }
109 /**
110 * \brief This function gets the software resets status of GPMC.\n
111 *
112 * \param hGpmc GPMC handle pointing to register base address.\n
113 *
114 * \return status Reset status : \n
115 * 0 : Module reset is on-going.\n
116 * 1 : Module reset is completed.\n
117 */
118 Uint32 GPMCModuleResetStatusGet(gpmcHandle hGpmc)
119 {
120 Uint32 resetStat;
122 resetStat = CSL_FEXT(hGpmc->SYSSTS, GPMC_SYSSTS_RESETDONE);
124 return (resetStat);
125 }
127 /**
128 * \brief This function gets Interrupt status of interrupt passed.\n
129 *
130 * \param hGpmc GPMC handle pointing to register base address.\n
131 *
132 * \param flag Flag for which interrupt status has to get.\n
133 * This can take one of the following values :\n
134 * GPMC_FIFOEVENT_STATUS : For FIFOEvent
135 * interrupt status.\n
136 * GPMC_TERMINALCOUNT_STATUS : For TerminalCountEvent
137 * interrupt status.\n
138 * GPMC_WAIT0EDGEDETECTION_STATUS: For Wait0 Edge
139 * Detection interrupt
140 * status.\n
141 * GPMC_WAIT1EDGEDETECTION_STATUS: For Wait1 Edge
142 * Detection interrupt
143 * status.\n
144 *
145 *
146 * \return intSts Interrupt Status. Return value meaning depends on the
147 * interrupt flag passed. \n
148 * if flag is GPMC_FIFOEVENT_STATUS, then \n
149 * 0 : Less than FIFOTHRESHOLD bytes are available in
150 * prefetch/read mode.\n
151 * Less than FIFOTHRESHOLD byte free spaces are
152 * available in write-posting/write mode. \n
153 * 1 : Atleast FIFOTHRESHOLD bytes are available in
154 * prefetch/read mode.\n
155 * Atlease FIFOTHRESHOLD byte free places are
156 * available in write-posting/write mode.\n
157 * if flag is GPMC_TERMINALCOUNT_STATUS, then \n
158 * 0 : CountValue is greater than 0.\n
159 * 1 : CountValue is equal to 0.\n
160 * if flag is GPMC_WAIT0EDGEDETECTION_STATUS, then \n
161 * 0 : A transition on WAIT0 input pin has not been
162 * detected.\n
163 * 1 : A transition on WAIT0 input pin has been
164 * detected.\n
165 * if flag is GPMC_WAIT1EDGEDETECTION_STATUS, then \n
166 * 0 : A transition on WAIT1 input pin has not been
167 * detected.\n
168 * 1 : A transition on WAIT1 input pin has been
169 * detected.\n
170 *
171 */
172 Uint32 GPMCIntStatusGet(gpmcHandle hGpmc, Uint32 flag)
173 {
174 Uint32 retVal;
176 retVal = 0;
178 switch(flag)
179 {
180 case GPMC_FIFOEVENT_STATUS:
181 retVal = CSL_FEXT(hGpmc->IRQSTS,
182 GPMC_IRQSTS_FIFOEVTSTS);
183 break;
184 case GPMC_TERMINALCOUNT_STATUS:
185 retVal = CSL_FEXT(hGpmc->IRQSTS,
186 GPMC_IRQSTS_TERMINALCOUNTSTS);
187 break;
188 case GPMC_WAIT0EDGEDETECTION_STATUS:
189 retVal = CSL_FEXT(hGpmc->IRQSTS,
190 GPMC_IRQSTS_WAIT0EDGEDETECTIONSTS);
191 break;
192 case GPMC_WAIT1EDGEDETECTION_STATUS:
193 retVal = CSL_FEXT(hGpmc->IRQSTS,
194 GPMC_IRQSTS_WAIT1EDGEDETECTIONSTS);
195 break;
196 }
198 return (retVal);
199 }
201 /**
202 * \brief This function clears/resets the interrupt status.\n
203 *
204 * \param hGpmc GPMC handle pointing to register base address.\n
205 *
206 * \param flag Flag for which interrupt status has to reset.\n
207 * This can take one of the following values :\n
208 * GPMC_FIFOEVENT_STATUS : For FIFOEvent
209 * interrupt status.\n
210 * GPMC_TERMINALCOUNT_STATUS : For TerminalCountEvent
211 * interrupt status.\n
212 * GPMC_WAIT0EDGEDETECTION_STATUS: For Wait1 Edge
213 * Detection interrupt
214 * status.\n
215 * GPMC_WAIT1EDGEDETECTION_STATUS: For Wait1 Edge
216 * Detection interrupt
217 * status.\n
218 *
219 * \return None.
220 *
221 */
222 void GPMCIntStatusClear(gpmcHandle hGpmc, Uint32 flag)
223 {
224 switch(flag)
225 {
226 case GPMC_FIFOEVENT_STATUS:
227 CSL_FINS(hGpmc->IRQSTS,
228 GPMC_IRQSTS_FIFOEVTSTS, GPMC_BIT_SET_HIGH);
229 break;
230 case GPMC_TERMINALCOUNT_STATUS:
231 CSL_FINS(hGpmc->IRQSTS,
232 GPMC_IRQSTS_TERMINALCOUNTSTS, GPMC_BIT_SET_HIGH);
233 break;
234 case GPMC_WAIT0EDGEDETECTION_STATUS:
235 CSL_FINS(hGpmc->IRQSTS,
236 GPMC_IRQSTS_WAIT0EDGEDETECTIONSTS,
237 GPMC_BIT_SET_HIGH);
238 break;
239 case GPMC_WAIT1EDGEDETECTION_STATUS:
240 CSL_FINS(hGpmc->IRQSTS,
241 GPMC_IRQSTS_WAIT1EDGEDETECTIONSTS,
242 GPMC_BIT_SET_HIGH);
243 break;
244 }
245 }
247 /**
248 * \brief This function enables the interrupts.\n
249 *
250 * \param hGpmc GPMC handle pointing to register base address.\n
251 *
252 * \param flag Flag for which interrupt has to enable.
253 * This can take one of the following values :\n
254 * GPMC_FIFOEVENT_INT : For FIFOEvent interrupt.\n
255 * GPMC_TERMINALCOUNT_INT : For TerminalCountEvent
256 * interrupt.\n
257 * GPMC_WAIT0EDGEDETECTION_INT : For Wait0 Edge
258 * Detection interrupt.\n
259 * GPMC_WAIT1EDGEDETECTION_INT : For Wait1 Edge
260 * Detection interrupt.\n
261 *
262 *
263 * \return None. \n
264 *
265 */
266 void GPMCIntEnable(gpmcHandle hGpmc, Uint32 flag)
267 {
268 switch(flag)
269 {
270 case GPMC_FIFOEVENT_INT:
271 CSL_FINS(hGpmc->IRQEN,
272 GPMC_IRQEN_FIFOEVTEN, GPMC_BIT_ENABLE);
273 break;
274 case GPMC_TERMINALCOUNT_INT:
275 CSL_FINS(hGpmc->IRQEN,
276 GPMC_IRQEN_TERMINALCOUNTEVTEN,
277 GPMC_BIT_ENABLE);
278 break;
279 case GPMC_WAIT0EDGEDETECTION_INT:
280 CSL_FINS(hGpmc->IRQEN,
281 GPMC_IRQEN_WAIT0EDGEDETECTIONEN,
282 GPMC_BIT_ENABLE);
283 break;
284 case GPMC_WAIT1EDGEDETECTION_INT:
285 CSL_FINS(hGpmc->IRQEN,
286 GPMC_IRQEN_WAIT1EDGEDETECTIONEN,
287 GPMC_BIT_ENABLE);
288 break;
289 }
290 }
292 /**
293 * \brief This function disable/masks the interrupts.\n
294 *
295 * \param hGpmc GPMC handle pointing to register base address.\n
296 *
297 * \param flag Flag for which interrupt has to mask.\n
298 * This can take one of the following values :\n
299 * GPMC_FIFOEVENT_INT : For FIFOEvent interrupt.\n
300 * GPMC_TERMINALCOUNT_INT : For TerminalCountEvent
301 * interrupt.\n
302 * GPMC_WAIT0EDGEDETECTION_INT : For Wait1 Edge
303 * Detection interrupt.\n
304 * GPMC_WAIT1EDGEDETECTION_INT : For Wait1 Edge
305 * Detection interrupt. \n
306 *
307 * \return None.\n
308 *
309 */
310 void GPMCIntDisable(gpmcHandle hGpmc, Uint32 flag)
311 {
312 switch(flag)
313 {
314 case GPMC_FIFOEVENT_INT:
315 CSL_FINS(hGpmc->IRQEN,
316 GPMC_IRQEN_FIFOEVTEN, GPMC_BIT_DISABLE);
317 break;
318 case GPMC_TERMINALCOUNT_INT:
319 CSL_FINS(hGpmc->IRQEN,
320 GPMC_IRQEN_TERMINALCOUNTEVTEN,
321 GPMC_BIT_DISABLE);
322 break;
323 case GPMC_WAIT0EDGEDETECTION_INT:
324 CSL_FINS(hGpmc->IRQEN,
325 GPMC_IRQEN_WAIT0EDGEDETECTIONEN,
326 GPMC_BIT_DISABLE);
327 break;
328 case GPMC_WAIT1EDGEDETECTION_INT:
329 CSL_FINS(hGpmc->IRQEN,
330 GPMC_IRQEN_WAIT1EDGEDETECTIONEN,
331 GPMC_BIT_DISABLE);
332 break;
333 }
334 }
336 /**
337 * \brief This function sets the start timeout value(TIMEOUTSTARTVALUE)
338 * of the timeout counter.\n
339 *
340 * \param hGpmc GPMC handle pointing to register base address.\n
341 *
342 * \param timoutVal Timeout start Value in GPMC_FCLK cycles.\n
343 *
344 * \return None. \n
345 *
346 */
347 void GPMCTimeOutStartValSet(gpmcHandle hGpmc, Uint32 timeoutVal)
348 {
349 CSL_FINS(hGpmc->TIMEOUT_CTRL,
350 GPMC_TIMEOUT_CTRL_TIMEOUTSTARTVALUE, timeoutVal);
351 }
353 /**
354 * \brief This function configures the timeout feature.\n
355 *
356 * \param hGpmc GPMC handle pointing to register base address.\n
357 *
358 * \param flag Flag to indicate whether to enable or disable the
359 * feature.\n
360 * This can take one of the following values :\n
361 * GPMC_TIMEOUTFEATURE_ENABLE - To enable the timout
362 * feature.\n
363 * GPMC_TIMEOUTFEATURE_DISABLE - To disable the timout
364 * feature.\n
365 * \return None. \n
366 *
367 */
368 void GPMCTimeOutFeatureConfig(gpmcHandle hGpmc, Uint32 flag)
369 {
370 if(flag == GPMC_TIMEOUTFEATURE_ENABLE)
371 {
372 CSL_FINS(hGpmc->TIMEOUT_CTRL,
373 GPMC_TIMEOUT_CTRL_TIMEOUTEN, GPMC_BIT_ENABLE);
374 }
375 else if (flag == GPMC_TIMEOUTFEATURE_DISABLE)
376 {
377 CSL_FINS(hGpmc->TIMEOUT_CTRL,
378 GPMC_TIMEOUT_CTRL_TIMEOUTEN, GPMC_BIT_DISABLE);
379 }
380 }
382 /**
383 * \brief This function returns the address of illegal access when an error
384 * occures.\n
385 *
386 * \param hGpmc GPMC handle pointing to register base address.\n
387 *
388 * \return illegalAddrVal Address of illegal access. \n
389 *
390 */
391 Uint32 GPMCErrAddrGet(gpmcHandle hGpmc)
392 {
393 Uint32 retVal;
395 retVal = CSL_FEXT(hGpmc->ERR_ADDR, GPMC_ERR_ADDR_ILLEGALADD);
397 return (retVal);
398 }
400 /**
401 * \brief This function returns the status of error validity.\n
402 *
403 * \param hGpmc GPMC handle pointing to register base address.\n
404 *
405 * \return ErrValstatus Error validity status. \n
406 * 0 : Error fields are no longer valid.\n
407 * 1 : Error detected and logged in the
408 * other error fields.\n
409 *
410 */
411 Uint32 GPMCErrValStatusGet(gpmcHandle hGpmc)
412 {
413 Uint32 status;
415 status = CSL_FEXT(hGpmc->ERR_TYPE, GPMC_ERR_TYPE_ERRORVALID);
417 return (status);
418 }
420 /**
421 * \brief This function returns the System Command of the transaction
422 * that caused the error.\n
423 *
424 * \param hGpmc GPMC handle pointing to register base address.\n
425 *
426 * \return errCmd System Command that caused the error. \n
427 *
428 */
429 Uint32 GPMCErrSysCmdGet(gpmcHandle hGpmc)
430 {
431 Uint32 cmd;
433 cmd = CSL_FEXT(hGpmc->ERR_TYPE, GPMC_ERR_TYPE_ILLEGALMCMD);
435 return (cmd);
436 }
438 /**
439 * \brief This function returns whether passed error is occured or not.\n
440 *
441 * \param hGpmc GPMC handle pointing to register base address.\n
442 *
443 * \param errFlag Type of the error.\n
444 * This can take one of the following values :\n
445 * GPMC_TIMEOUT_ERROR -- For timeout error.\n
446 * GPMC_NOTSUPPMCMD_ERROR -- For non-supported cmd error.\n
447 * GPMC_NOTSUPPADD_ERROR -- For non-supported add error.\n
448 *
449 * \return ErrStatus \n
450 *
451 * 1 : If passed argument type of error occured.\n
452 * 0 : If passed argument type of error doesn't occured.\n
453 *
454 */
455 Uint32 GPMCErrStatusGet(gpmcHandle hGpmc, Uint32 err)
456 {
457 Uint32 retVal;
459 retVal = 0;
461 switch(err)
462 {
463 case GPMC_TIMEOUT_ERROR:
464 retVal = CSL_FEXT(hGpmc->ERR_TYPE,
465 GPMC_ERR_TYPE_ERRORTIMEOUT);
466 break;
467 case GPMC_NOTSUPPMCMD_ERROR:
468 retVal = CSL_FEXT(hGpmc->ERR_TYPE,
469 GPMC_ERR_TYPE_ERRORNOTSUPPMCMD);
470 break;
471 case GPMC_NOTSUPPADD_ERROR:
472 retVal = CSL_FEXT(hGpmc->ERR_TYPE,
473 GPMC_ERR_TYPE_ERRORNOTSUPPADD);
474 break;
475 }
476 return (retVal);
477 }
479 /**
480 * \brief This function sets/selects the waitpin polarity.\n
481 *
482 * \param hGpmc GPMC handle pointing to register base address.\n
483 *
484 * \param pin Wait pin.\n
485 * This can take one of the following values :\n
486 * GPMC_WAIT_PIN0 -- For WAITPIN0.\n
487 * GPMC_WAIT_PIN1 -- For WAITPIN1.\n
488 *
489 * \param polarity Wait pin polarity.\n
490 * This can take one of the following values :\n
491 * GPMC_WAIT_PIN_POLARITY_LOW -- for active low.\n
492 * GPMC_WAIT_PIN_POLARITY_HIGH -- for active high.\n
493 *
494 * \return None.\n
495 *
496 */
497 void GPMCWaitPinPolaritySelect(gpmcHandle hGpmc, Uint32 pin,
498 Uint32 polarity)
499 {
500 if(pin == GPMC_WAIT_PIN0)
501 {
502 if(polarity == GPMC_WAIT_PIN_POLARITY_HIGH)
503 {
504 CSL_FINS(hGpmc->CONFIG, GPMC_CONFIG_WAIT0PINPOLARITY,
505 GPMC_BIT_SET_HIGH);
506 }
507 else if(polarity == GPMC_WAIT_PIN_POLARITY_LOW)
508 {
509 CSL_FINS(hGpmc->CONFIG, GPMC_CONFIG_WAIT0PINPOLARITY,
510 GPMC_BIT_SET_LOW);
511 }
512 }
513 else if(pin == GPMC_WAIT_PIN1)
514 {
515 if(polarity == GPMC_WAIT_PIN_POLARITY_HIGH)
516 {
517 CSL_FINS(hGpmc->CONFIG, GPMC_CONFIG_WAIT1PINPOLARITY,
518 GPMC_BIT_SET_HIGH);
519 }
520 else if(polarity == GPMC_WAIT_PIN_POLARITY_LOW)
521 {
522 CSL_FINS(hGpmc->CONFIG, GPMC_CONFIG_WAIT1PINPOLARITY,
523 GPMC_BIT_SET_LOW);
524 }
525 }
526 }
528 /**
529 * \brief This function controls the write protect output pin level.\n
530 *
531 * \param hGpmc GPMC handle pointing to register base address.\n
532 *
533 * \param pinLevel Write Protect pin level.\n
534 * This can take one of the following values :\n
535 * GPMC_WP_PIN_LEVEL_LOW -- for level low.\n
536 * GPMC_WP_PIN_LEVEL_HIGH -- for level high.\n
537 *
538 * \return None.\n
539 *
540 */
541 void GPMCWriteProtectPinLevelCtrl(gpmcHandle hGpmc, Uint32 pinLevel)
542 {
543 if(pinLevel == GPMC_WP_PIN_LEVEL_HIGH)
544 {
545 CSL_FINS(hGpmc->CONFIG, GPMC_CONFIG_WRITEPROTECT,
546 GPMC_BIT_SET_HIGH);
547 }
548 else if(pinLevel == GPMC_WP_PIN_LEVEL_LOW)
549 {
550 CSL_FINS(hGpmc->CONFIG, GPMC_CONFIG_WRITEPROTECT,
551 GPMC_BIT_SET_LOW);
552 }
553 }
555 /**
556 * \brief This function configs the limited address device support.\n
557 *
558 * \param hGpmc GPMC handle pointing to register base address.\n
559 *
560 * \param flag Flag to indicate whether to enable/disable the
561 * Limited Address device support.\n
562 * This can take one of the following values :\n
563 * GPMC_LIMITEDADDRESS_SUPPORT_ENABLE -- To enable
564 * the support.\n
565 * GPMC_LIMITEDADDRESS_SUPPORT_DISABLE -- To disable
566 * the support.\n
567 *
568 * \return None.\n
569 *
570 */
571 void GPMCLimitedAddrDevSupportConfig(gpmcHandle hGpmc, Uint32 flag)
572 {
573 if(flag == GPMC_LIMITEDADDRESS_SUPPORT_ENABLE)
574 {
575 CSL_FINS(hGpmc->CONFIG, GPMC_CONFIG_LIMITEDADDR,
576 GPMC_BIT_ENABLE);
577 }
578 else if(flag == GPMC_LIMITEDADDRESS_SUPPORT_DISABLE)
579 {
580 CSL_FINS(hGpmc->CONFIG, GPMC_CONFIG_LIMITEDADDR,
581 GPMC_BIT_DISABLE);
582 }
583 }
585 /**
586 * \brief This function configs the Force Posted Write feature to NAND
587 * Cmd/Add/Data location.\n
588 *
589 * \param hGpmc GPMC handle pointing to register base address.\n
590 *
591 * \param flag Flag to indicate whether to enable/disable the
592 * Force Posted Write feature.\n
593 * This can take one of the following values :\n
594 * GPMC_FORCEPOSTEDWRITE_ENABLE -- To enable the
595 * feature.\n
596 * GPMC_FORCEPOSTEDWRITE_DISABLE -- To disable
597 * the feature.\n
598 *
599 * \return None.\n
600 *
601 */
602 void GPMCNANDForcePostedWriteFeatureConfig(gpmcHandle hGpmc,
603 Uint32 flag)
604 {
605 if(flag == GPMC_FORCEPOSTEDWRITE_ENABLE)
606 {
607 CSL_FINS(hGpmc->CONFIG, GPMC_CONFIG_NANDFORCEPOSTEDWRITE,
608 GPMC_BIT_ENABLE);
609 }
610 else if(flag == GPMC_FORCEPOSTEDWRITE_DISABLE)
611 {
612 CSL_FINS(hGpmc->CONFIG, GPMC_CONFIG_NANDFORCEPOSTEDWRITE,
613 GPMC_BIT_DISABLE);
614 }
615 }
617 /**
618 * \brief This function gets the waitpin status.\n
619 *
620 * \param hGpmc GPMC handle pointing to register base address.\n
621 *
622 * \param pin Wait pin.\n
623 * This can take one of the following values :\n
624 * GPMC_WAIT_PIN0 -- For WAITPIN0.\n
625 * GPMC_WAIT_PIN1 -- For WAITPIN1.\n
626 *
627 * \return pinStatus Pin Status.\n
628 * 0 : If the status is active low.\n
629 * 1 : If the status is active high.\n
630 *
631 */
632 Uint32 GPMCWaitPinStatusGet(gpmcHandle hGpmc, Uint32 pin)
633 {
634 Uint32 pinStatus;
636 pinStatus = 0;
638 if(pin == GPMC_WAIT_PIN0)
639 {
640 pinStatus = CSL_FEXT(hGpmc->STS, GPMC_STS_WAIT0STS);
641 }
642 else if(pin == GPMC_WAIT_PIN1)
643 {
644 pinStatus = CSL_FEXT(hGpmc->STS, GPMC_STS_WAIT1STS);
645 }
647 return (pinStatus);
648 }
650 /**
651 * \brief This function gets the empty write buffer status.\n
652 *
653 * \param hGpmc GPMC handle pointing to register base address.\n
654 *
655 * \return Status Empty buffer status.\n
656 * 0 : If the Write Buffer is not empty.\n
657 * 1 : If the Write Buffer is empty.\n
658 *
659 */
660 Uint32 GPMCEmptyWriteBuffStatusGet(gpmcHandle hGpmc)
661 {
662 Uint32 status;
664 status = CSL_FEXT(hGpmc->STS,
665 GPMC_STS_EMPTYWRITEBUFFERSTS);
666 return (status);
667 }
669 /**
670 * \brief This function selects the FCLK DIVIDER for the chip select passed.\n
671 *
672 * \param hGpmc GPMC handle pointing to register base address.\n
673 *
674 * \param csNum Chip Select Number.\n
675 * This can take one of the following values :\n
676 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
677 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
678 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
679 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
680 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
681 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
682 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
683 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
684 *
685 * \param divideVal FCLK Divice value.\n
686 * This can take one of the following values :\n
687 * GPMC_FCLK_DIV_BY_1 -- For GPMC_CLK = (GPMC_FCLK / 1)\n
688 * GPMC_FCLK_DIV_BY_2 -- For GPMC_CLK = (GPMC_FCLK / 2)\n
689 * GPMC_FCLK_DIV_BY_3 -- For GPMC_CLK = (GPMC_FCLK / 3)\n
690 * GPMC_FCLK_DIV_BY_4 -- For GPMC_CLK = (GPMC_FCLK / 4)\n
691 * \return None.\n
692 *
693 */
694 void GPMCFclkDividerSelect(gpmcHandle hGpmc, Uint32 csNum,
695 Uint32 divideVal)
696 {
697 volatile Uint32 *gpmcCfg1;
699 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
701 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_GPMCFCLKDIVIDER, divideVal);
702 }
704 /**
705 * \brief This function selects the signals timing latencies scalar factor
706 * for the chip select.\n
707 *
708 * \param hGpmc GPMC handle pointing to register base address.\n
709 *
710 * \param csNum Chip Select Number.\n
711 * This can take one of the following values :\n
712 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
713 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
714 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
715 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
716 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
717 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
718 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
719 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
720 *
721 * \param scaleftr Scalar factor.\n
722 * This can take one of the following values :\n
723 * GPMC_TIMEPARAGRANULARITY_X1 -- For x1 latencies\n
724 * GPMC_TIMEPARAGRANULARITY_X2 -- For x2 latencies\n
725 * \return None.\n
726 *
727 */
728 void GPMCTimeParaGranularitySelect(gpmcHandle hGpmc, Uint32 csNum,
729 Uint32 scaleftr)
730 {
731 volatile Uint32 *gpmcCfg1;
733 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
735 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_TIMEPARAGRANULARITY, scaleftr);
736 }
738 /**
739 * \brief This function selects the Address and data multiplexed protocol
740 * for the device connected to csNum.\n
741 *
742 * \param hGpmc GPMC handle pointing to register base address.\n
743 *
744 * \param csNum Chip Select Number.\n
745 * This can take one of the following values :\n
746 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
747 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
748 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
749 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
750 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
751 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
752 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
753 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
754 *
755 * \param protocol Protocol type.\n
756 * This can take one of the following values :\n
757 * GPMC_MUXADDDATA_AADMUX -- For Address, address and
758 * data(AAD) muxed protocol.\n
759 * GPMC_MUXADDDATA_NOMUX -- For Non-muxed prorocol.\n
760 * GPMC_MUXADDDATA_ADMUX -- For Address & Data muxed
761 * protocol.\n
762 * \return None.\n
763 *
764 */
765 void GPMCAddrDataMuxProtocolSelect(gpmcHandle hGpmc, Uint32 csNum,
766 Uint32 protocol)
767 {
768 volatile Uint32 *gpmcCfg1;
770 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
772 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_MUXADDDATA, protocol);
773 }
775 /**
776 * \brief This function selects the device type for the device connected to
777 * csNum.\n
778 *
779 * \param hGpmc GPMC handle pointing to register base address.\n
780 *
781 * \param csNum Chip Select Number.\n
782 * This can take one of the following values :\n
783 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
784 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
785 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
786 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
787 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
788 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
789 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
790 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
791 *
792 * \param devType Device Type.\n
793 * This can take one of the following values :\n
794 * GPMC_DEVICETYPE_NANDLIKE -- For NAND flash like
795 * devices.\n
796 * GPMC_DEVICETYPE_NORLIKE -- For NOR flash like
797 * devices.\n
798 * \return None.\n
799 *
800 */
801 void GPMCDevTypeSelect(gpmcHandle hGpmc, Uint32 csNum,
802 Uint32 devType)
803 {
804 volatile Uint32 *gpmcCfg1;
806 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
808 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_DEVICETYPE, devType);
809 }
811 /**
812 * \brief This function selects the device size for the device connected to
813 * csNum.\n
814 *
815 * \param hGpmc GPMC handle pointing to register base address.\n
816 *
817 * \param csNum Chip Select Number.\n
818 * This can take one of the following values :\n
819 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
820 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
821 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
822 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
823 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
824 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
825 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
826 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
827 *
828 * \param devSize Device Size.\n
829 * This can take one of the following values :\n
830 * GPMC_DEVICESIZE_8BITS -- For 8-bit device.\n
831 * GPMC_DEVICESIZE_16BITS -- For 16-bit device.\n
832 * \return None.\n
833 *
834 */
835 void GPMCDevSizeSelect(gpmcHandle hGpmc, Uint32 csNum,
836 Uint32 devSize)
837 {
838 volatile Uint32 *gpmcCfg1;
840 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
842 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_DEVICESIZE, devSize);
843 }
845 /**
846 * \brief This function selects the WAIT PIN for the device connected to
847 * csNum.\n
848 *
849 * \param hGpmc GPMC handle pointing to register base address.\n
850 *
851 * \param csNum Chip Select Number.\n
852 * This can take one of the following values :\n
853 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
854 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
855 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
856 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
857 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
858 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
859 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
860 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
861 *
862 * \param waitPin Wait Pin.\n
863 * This can take one of the following values :\n
864 * GPMC_WAIT_PIN0 -- To Select WAITPIN0.\n
865 * GPMC_WAIT_PIN1 -- To Select WAITPIN1.\n
866 * \return None.\n
867 *
868 */
869 void GPMCWaitPinSelect(gpmcHandle hGpmc, Uint32 csNum,
870 Uint32 waitPin)
871 {
872 volatile Uint32 *gpmcCfg1;
874 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
876 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_WAITPINSELECT, waitPin);
877 }
879 /**
880 * \brief This function configs/selects the wait monitoring time for the device
881 * connected to csNum.\n
882 *
883 * \param hGpmc GPMC handle pointing to register base address.\n
884 *
885 * \param csNum Chip Select Number.\n
886 * This can take one of the following values :\n
887 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
888 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
889 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
890 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
891 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
892 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
893 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
894 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
895 *
896 * \param flag Flag to indicate the wait monitoring time.\n
897 * This can take one of the following values :\n
898 * GPMC_WAITMONITORINGTIME_WITH_VALIDDATA -- For wait
899 * pin monitoring with valid data.\n
900 * GPMC_WAITMONITORINGTIME_ONECLKB4_VALIDDATA -- For
901 * wait pin monitoring one GPMC_CLK
902 * before valid data. \n
903 * GPMC_WAITMONITORINGTIME_TWOCLKB4_VALIDDATA -- For
904 * wait pin monitoring two GPMC_CLK
905 * before valid data. \n
906 * \return None.\n
907 *
908 */
909 void GPMCWaitMonitoringTimeSelect(gpmcHandle hGpmc, Uint32 csNum,
910 Uint32 flag)
911 {
912 volatile Uint32 *gpmcCfg1;
914 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
916 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_WAITMONITORINGTIME, flag);
917 }
919 /**
920 * \brief This function configs the wait pin monitoring for read and write
921 * access.
922 *
923 * \param hGpmc GPMC handle pointing to register base address.\n
924 *
925 * \param csNum Chip Select Number.\n
926 * This can take one of the following values :\n
927 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
928 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
929 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
930 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
931 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
932 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
933 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
934 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
935 *
936 * \param mode Mode for which wait monitoring has to config.\n
937 * This can take one of the following values :\n
938 * GPMC_MODE_READ -- To config the wait
939 * monitoring for READ.\n
940 * GPMC_MODE_WRITE -- To config the wait
941 * monitoring for WRITE.\n
942 *
943 * \param flag Flag to indicate whether to enable/disable the wait
944 * monitoring.\n
945 * This can take one of the following values :\n
946 * GPMC_WAITMONITORING_ENABLE -- To enable the wait
947 * monitoring.\n
948 * GPMC_WAITMONITORING_DISABLE -- To disable the wait
949 * monitoring.\n
950 * \return None.\n
951 *
952 */
953 void GPMCWaitPinMonitoringConfig(gpmcHandle hGpmc, Uint32 csNum,
954 Uint32 mode, Uint32 flag)
955 {
956 volatile Uint32 *gpmcCfg1;
958 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
960 if(mode == GPMC_MODE_WRITE)
961 {
962 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_WAITWRITEMONITORING, flag);
963 }
964 else if(mode == GPMC_MODE_READ)
965 {
966 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_WAITREADMONITORING, flag);
967 }
968 }
970 /**
971 * \brief This function configs the output GPMC_CLK activation time.\n
972 *
973 * \param hGpmc GPMC handle pointing to register base address.\n
974 *
975 * \param csNum Chip Select Number.
976 * This can take one of the following values :\n
977 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
978 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
979 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
980 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
981 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
982 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
983 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
984 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
985 *
986 * \param flag Flag to indicate the activation time of GPMC_CLK.\n
987 * This can take one of the following values :\n
988 * GPMC_CLKACTIVATIONTIME_ATSTART -- For First rising
989 * edge of GPMC_CLK at
990 * start access time.\n
991 * GPMC_CLKACTIVATIONTIME_ONECLK_AFTR -- For First rising
992 * edge of GPMC_CLK one
993 * GPMC_FCLK cycle aftr
994 * start access time.\n
995 * GPMC_CLKACTIVATIONTIME_TWOCLK_AFTR -- For First rising
996 * edge of GPMC_CLK two
997 * GPMC_FCLK cycle aftr
998 * start access time.\n
999 * \return None.\n
1000 *
1001 */
1002 void GPMCClkActivationTimeConfig(gpmcHandle hGpmc, Uint32 csNum,
1003 Uint32 flag)
1004 {
1005 volatile Uint32 *gpmcCfg1;
1007 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
1009 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_CLKACTIVATIONTIME, flag);
1010 }
1012 /**
1013 * \brief This function sets the device page length.\n
1014 *
1015 * \param hGpmc GPMC handle pointing to register base address.\n
1016 *
1017 * \param csNum Chip Select Number.\n
1018 * This can take one of the following values :\n
1019 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1020 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1021 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1022 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1023 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1024 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1025 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1026 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1027 *
1028 * \param pageLen Device Page Length.\n
1029 * This can take one of the following values :\n
1030 * GPMC_DEV_PAGELENGTH_FOUR -- For 4 words page
1031 * length.\n
1032 * GPMC_DEV_PAGELENGTH_EIGHT -- For 8 words page
1033 * length.\n
1034 * GPMC_DEV_PAGELENGTH_SIXTEEN -- For 16 words page
1035 * length. \n
1036 * \return None.\n
1037 *
1038 */
1039 void GPMCDevPageLenSet(gpmcHandle hGpmc, Uint32 csNum, Uint32 pageLen)
1040 {
1041 volatile Uint32 *gpmcCfg1;
1043 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
1045 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH, pageLen);
1046 }
1048 /**
1049 * \brief This function selects the write type.\n
1050 *
1051 * \param hGpmc GPMC handle pointing to register base address.\n
1052 *
1053 * \param csNum Chip Select Number.\n
1054 * This can take one of the following values :\n
1055 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1056 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1057 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1058 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1059 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1060 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1061 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1062 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1063 *
1064 * \param writeType writeType for the write mode operation.\n
1065 * This can take one of the following values :\n
1066 * GPMC_WRITETYPE_ASYNC -- For write asynchronous.\n
1067 * GPMC_WRITETYPE_SYNC -- For write synchronous.\n
1068 *
1069 * \return None.\n
1070 *
1071 */
1072 void GPMCWriteTypeSelect(gpmcHandle hGpmc, Uint32 csNum, Uint32 writeType)
1073 {
1074 volatile Uint32 *gpmcCfg1;
1076 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
1078 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_WRITETYPE, writeType);
1079 }
1081 /**
1082 * \brief This function selects the read type.\n
1083 *
1084 * \param hGpmc GPMC handle pointing to register base address.\n
1085 *
1086 * \param csNum Chip Select Number.\n
1087 * This can take one of the following values :\n
1088 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1089 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1090 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1091 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1092 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1093 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1094 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1095 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1096 *
1097 * \param readType readType for the read mode operation.\n
1098 * This can take one of the following values :\n
1099 * GPMC_READTYPE_ASYNC -- For read asynchronous.\n
1100 * GPMC_READTYPE_SYNC -- For read synchronous.\n
1101 *
1102 * \return None.\n
1103 *
1104 */
1105 void GPMCReadTypeSelect(gpmcHandle hGpmc, Uint32 csNum, Uint32 readType)
1106 {
1107 volatile Uint32 *gpmcCfg1;
1109 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
1111 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_READTYPE, readType);
1112 }
1114 /**
1115 * \brief This function configs the access type for read and write.\n
1116 *
1117 * \param hGpmc GPMC handle pointing to register base address.\n
1118 *
1119 * \param csNum Chip Select Number.\n
1120 * This can take one of the following values :\n
1121 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1122 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1123 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1124 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1125 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1126 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1127 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1128 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1129 *
1130 * \param mode Mode for which access type has to config.\n
1131 * This can take one of the following values :\n
1132 * GPMC_MODE_READ -- To config access
1133 * type for READ.\n
1134 * GPMC_MODE_WRITE -- To config access
1135 * type for WRITE.\n
1136 * \param AccessType Access Type.\n
1137 * This can take one of the following values :\n
1138 * GPMC_ACCESSTYPE_SINGLE -- For single access.\n
1139 * GPMC_ACCESSTYPE_MULTIPLE -- For multiple access.\n
1140 *
1141 * \return None.\n
1142 *
1143 */
1144 void GPMCAccessTypeSelect(gpmcHandle hGpmc, Uint32 csNum,
1145 Uint32 mode, Uint32 accessType)
1146 {
1147 volatile Uint32 *gpmcCfg1;
1149 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
1151 if(mode == GPMC_MODE_WRITE)
1152 {
1153 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_WRITEMULTIPLE, accessType);
1154 }
1155 else if(mode == GPMC_MODE_READ)
1156 {
1157 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_READMULTIPLE, accessType);
1158 }
1159 }
1161 /**
1162 * \brief This function configs the wrapping burst capability.\n
1163 *
1164 * \param hGpmc GPMC handle pointing to register base address.\n
1165 *
1166 * \param csNum Chip Select Number.\n
1167 * This can take one of the following values :\n
1168 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1169 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1170 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1171 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1172 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1173 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1174 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1175 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1176 *
1177 * \param flag Flag to indicate whether to enable/disable
1178 * Synchronous wrapping burst capability.\n
1179 * This can take one of the following values :\n
1180 * GPMC_WRAPBURST_ENABLE -- To enable the wrap burst
1181 * capability.\n
1182 * GPMC_WRAPBURST_DISABLE -- To disable the wrap burst
1183 * capability.\n
1184 *
1185 * \return None.\n
1186 *
1187 */
1188 void GPMCSyncWrapBurstConfig(gpmcHandle hGpmc, Uint32 csNum, Uint32 flag)
1189 {
1190 volatile Uint32 *gpmcCfg1;
1192 gpmcCfg1 = (Uint32 *)(&hGpmc->CONFIG1_0 + (csNum * 0x30));
1194 CSL_FINS(*gpmcCfg1, GPMC_CONFIG1_0_WRAPBURST, flag);
1195 }
1197 /**
1198 * \brief This function configs the timing parameters for Chip Select signal.\n
1199 *
1200 * \param hGpmc GPMC handle pointing to register base address.\n
1201 *
1202 * \param csNum Chip Select Number.\n
1203 * This can take one of the following values :\n
1204 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1205 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1206 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1207 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1208 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1209 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1210 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1211 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1212 *
1213 * \param conf Configuration value for chip select timing parameters
1214 * Use the GPMC_CS_TIMING_CONFIG macro to get the value
1215 * of conf. \n
1216 *
1217 * \return None.\n
1218 *
1219 */
1220 void GPMCCSTimingConfig(gpmcHandle hGpmc, Uint32 csNum, Uint32 conf)
1221 {
1222 volatile Uint32 *gpmcCfg2;
1224 gpmcCfg2 = (Uint32 *)(&hGpmc->CONFIG2_0 + (csNum * 0x30));
1226 *gpmcCfg2 = conf;
1227 }
1229 /**
1230 * \brief This function configs the timing parameters for ADV# signal.\n
1231 *
1232 * \param hGpmc GPMC handle pointing to register base address.\n
1233 *
1234 * \param csNum Chip Select Number.\n
1235 * This can take one of the following values :\n
1236 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1237 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1238 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1239 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1240 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1241 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1242 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1243 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1244 *
1245 * \param conf Configuration value for ADV# signal timing parameters
1246 * Use the GPMC_ADV_TIMING_CONFIG macro to get the value
1247 * of conf. \n
1248 *
1249 * \return None.\n
1250 *
1251 */
1252 void GPMCADVTimingConfig(gpmcHandle hGpmc, Uint32 csNum, Uint32 conf)
1253 {
1254 volatile Uint32 *gpmcCfg3;
1256 gpmcCfg3 = (Uint32 *)(&hGpmc->CONFIG3_0 + (csNum * 0x30));
1258 *gpmcCfg3 = conf;
1259 }
1261 /**
1262 * \brief This function configs the timing parameters for WE# and OE# signal.\n
1263 *
1264 * \param hGpmc GPMC handle pointing to register base address.\n
1265 *
1266 * \param csNum Chip Select Number.\n
1267 * This can take one of the following values :\n
1268 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1269 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1270 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1271 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1272 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1273 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1274 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1275 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1276 *
1277 * \param conf Configuration value for WE# and OE# signal timing
1278 * Parameters. Use the GPMC_WE_OE_TIMING_CONFIG macro to
1279 * get the value of conf. \n
1280 *
1281 * \return None.\n
1282 *
1283 */
1284 void GPMCWEAndOETimingConfig(gpmcHandle hGpmc, Uint32 csNum, Uint32 conf)
1285 {
1286 volatile Uint32 *gpmcCfg4;
1288 gpmcCfg4 = (Uint32 *)(&hGpmc->CONFIG4_0 + (csNum * 0x30));
1290 *gpmcCfg4 = conf;
1291 }
1293 /**
1294 * \brief This function configs the RdAccessTime and CycleTime timing
1295 * parameters.\n
1296 *
1297 * \param hGpmc GPMC handle pointing to register base address.\n
1298 *
1299 * \param csNum Chip Select Number.\n
1300 * This can take one of the following values :\n
1301 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1302 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1303 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1304 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1305 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1306 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1307 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1308 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1309 *
1310 * \param conf Configuration value for RdAccessTime and CycleTime
1311 * timing parameters. Use the
1312 * GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG macro to
1313 * get the value of conf. \n
1314 *
1315 * \return None.\n
1316 *
1317 */
1318 void GPMCRdAccessAndCycleTimeTimingConfig(gpmcHandle hGpmc,
1319 Uint32 csNum,
1320 Uint32 conf)
1321 {
1322 volatile Uint32 *gpmcCfg5;
1324 gpmcCfg5 = (Uint32 *)(&hGpmc->CONFIG5_0 + (csNum * 0x30));
1326 *gpmcCfg5 = conf;
1327 }
1329 /**
1330 * \brief This function configs the WrAccessTime, Cycle2Cycle and BusTurnAround
1331 * timing parameters.\n
1332 *
1333 * \param hGpmc GPMC handle pointing to register base address.\n
1334 *
1335 * \param csNum Chip Select Number.\n
1336 * This can take one of the following values :\n
1337 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1338 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1339 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1340 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1341 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1342 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1343 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1344 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1345 *
1346 * \param wrAccessTime Write Access Time(Delay from StartAccessTime to the
1347 * GPMC_FCLK rising edge corresponding the GPMC_CLK
1348 * rising edge used by the attached memory for the
1349 * first data capture) in GPMC_FCLK cycles.\n
1350 *
1351 * wrDataOnADmuxBus Specifies on which GPMC_FCLK rising edge the first
1352 * data of the synchronous burst write is driven in the
1353 * add/data multiplexed bus.\n
1354 *
1355 * \return None.\n
1356 *
1357 */
1358 void GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(gpmcHandle hGpmc,
1359 Uint32 csNum,
1360 Uint32 wrAccessTime,
1361 Uint32 wrDataOnADmuxBus)
1362 {
1363 Uint32 conf;
1364 volatile Uint32 *gpmcCfg6;
1366 gpmcCfg6 = (Uint32 *)(&hGpmc->CONFIG6_0 + (csNum * 0x30));
1368 conf = ( ((wrAccessTime << CSL_GPMC_CONFIG6_0_WRACCESSTIME_SHIFT) &
1369 CSL_GPMC_CONFIG6_0_WRACCESSTIME_MASK) |
1370 ((wrDataOnADmuxBus << CSL_GPMC_CONFIG6_0_WRDATAONADMUXBUS_SHIFT) &
1371 CSL_GPMC_CONFIG6_0_WRDATAONADMUXBUS_MASK));
1373 *gpmcCfg6 |= conf;
1374 }
1376 /**
1377 * \brief This function configs the Cycle2Cycle and BusTurnAround timing
1378 * parameters.\n
1379 *
1380 * \param hGpmc GPMC handle pointing to register base address.\n
1381 *
1382 * \param csNum Chip Select Number.\n
1383 * This can take one of the following values :\n
1384 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1385 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1386 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1387 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1388 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1389 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1390 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1391 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1392 *
1393 * \param conf Configuration value for Cycle2Cycle and BusTurnAround
1394 * timing parameters. Use the
1395 * GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG macro to
1396 * get the value of conf. \n
1397 *
1398 * \return None.\n
1399 *
1400 */
1401 void GPMCycle2CycleAndTurnArndTimeTimingConfig(gpmcHandle hGpmc,
1402 Uint32 csNum,
1403 Uint32 conf)
1404 {
1405 volatile Uint32 *gpmcCfg6;
1407 gpmcCfg6 = (Uint32 *)(&hGpmc->CONFIG6_0 + (csNum * 0x30));
1409 *gpmcCfg6 |= conf;
1410 }
1412 /**
1413 * \brief This function enables/disables the chip select. This function
1414 * is called during the chip select configuration.\n
1415 *
1416 * \param hGpmc GPMC handle pointing to register base address.\n
1417 *
1418 * \param csNum Chip Select Number.\n
1419 * This can take one of the following values :\n
1420 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1421 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1422 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1423 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1424 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1425 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1426 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1427 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1428 *
1429 * \param conf Flag to indicate whether to enable or disable
1430 * the Chip select.\n
1431 * This can take one of the following values :\n
1432 * GPMC_CS_ENABLE -- To enable the chip select.\n
1433 * GPMC_CS_DISABLE -- To disable the chip select.\n
1434 *
1435 * \return None.\n
1436 *
1437 */
1438 void GPMCCSConfig(gpmcHandle hGpmc, Uint32 csNum, Uint32 conf)
1439 {
1440 volatile Uint32 *gpmcCfg7;
1442 gpmcCfg7 = (Uint32 *)(&hGpmc->CONFIG7_0 + (csNum * 0x30));
1444 CSL_FINS(*gpmcCfg7, GPMC_CONFIG7_0_CSVALID, conf);
1445 }
1447 /**
1448 * \brief This function sets the base address for the chip select spcified.\n
1449 *
1450 * \param hGpmc GPMC handle pointing to register base address.\n
1451 *
1452 * \param csNum Chip Select Number.\n
1453 * This can take one of the following values :\n
1454 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1455 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1456 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1457 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1458 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1459 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1460 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1461 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1462 *
1463 * \param addr Chip Select Base address.Value can range from
1464 * 0 to 0x3F\n
1465 *
1466 * \return None.\n
1467 *
1468 */
1469 void GPMCBaseAddrSet(gpmcHandle hGpmc, Uint32 csNum, Uint32 addr)
1470 {
1471 volatile Uint32 *gpmcCfg7;
1473 gpmcCfg7 = (Uint32 *)(&hGpmc->CONFIG7_0 + (csNum * 0x30));
1475 CSL_FINS(*gpmcCfg7, GPMC_CONFIG7_0_BASEADDR, addr);
1476 }
1478 /**
1479 * \brief This function sets the chip select mask address or size.\n
1480 *
1481 * \param hGpmc GPMC handle pointing to register base address.\n
1482 *
1483 * \param csNum Chip Select Number.\n
1484 * This can take one of the following values :\n
1485 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1486 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1487 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1488 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1489 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1490 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1491 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1492 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1493 *
1494 * \param addrMask Address Mask to set. \n
1495 * This can take one of the following values :\n
1496 * GPMC_CS_SIZE_256MB -- For Chip-select size of 256 MB.\n
1497 * GPMC_CS_SIZE_128MB -- For Chip-select size of 128 MB.\n
1498 * GPMC_CS_SIZE_64MB -- For Chip-select size of 64 MB.\n
1499 * GPMC_CS_SIZE_32MB -- For Chip-select size of 32 MB.\n
1500 * GPMC_CS_SIZE_16MB -- For Chip-select size of 16 MB.\n
1501 *
1502 * \return None.\n
1503 *
1504 */
1505 void GPMCMaskAddrSet(gpmcHandle hGpmc, Uint32 csNum, Uint32 addrMask)
1506 {
1507 volatile Uint32 *gpmcCfg7;
1509 gpmcCfg7 = (Uint32 *)(&hGpmc->CONFIG7_0 + (csNum * 0x30));
1511 CSL_FINS(*gpmcCfg7, GPMC_CONFIG7_0_MASKADDR, addrMask);
1512 }
1514 /**
1515 * \brief This function writes the NAND command to COMMAND register.\n
1516 *
1517 * \param hGpmc GPMC handle pointing to register base address.\n
1518 *
1519 * \param csNum Chip Select Number for which NAND is interfaced.
1520 * This can take one of the following values :
1521 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.
1522 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.
1523 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.
1524 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.
1525 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.
1526 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.
1527 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.
1528 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1529 *
1530 * \param cmd COMMAND to write.
1531 *
1532 * \return None.\n
1533 *
1534 */
1535 void GPMCSNANDCmdWrite(gpmcHandle hGpmc, Uint32 csNum, Uint32 cmd)
1536 {
1537 volatile Uint32 *nandCmd;
1539 nandCmd = (Uint32 *)(&hGpmc->NAND_COMMAND_0 + (csNum * (0x30)));
1541 *nandCmd = cmd;
1542 }
1544 /**
1545 * \brief This function writes the NAND address to ADDRESS register.\n
1546 *
1547 * \param hGpmc GPMC handle pointing to register base address.\n
1548 *
1549 * \param csNum Chip Select Number for which NAND is interfaced.\n
1550 * This can take one of the following values :\n
1551 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1552 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1553 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1554 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1555 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1556 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1557 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1558 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1559 *
1560 * \param addr ADDRESS to write. \n
1561 *
1562 * \return None.\n
1563 *
1564 */
1565 void GPMCNANDAddrWrite(gpmcHandle hGpmc, Uint32 csNum, Uint32 addr)
1566 {
1567 volatile Uint32 *nandAddr;
1569 nandAddr = (Uint32 *)(&hGpmc->NAND_ADDR_0 + (csNum * (0x30)));
1571 *nandAddr = addr;
1572 }
1574 /**
1575 * \brief This function writes the NAND data to DATA register.\n
1576 *
1577 * \param hGpmc GPMC handle pointing to register base address.\n
1578 *
1579 * \param csNum Chip Select Number for which NAND is interfaced.\n
1580 * This can take one of the following values :\n
1581 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1582 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1583 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1584 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1585 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1586 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1587 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1588 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1589 *
1590 * \param data data to write. \n
1591 *
1592 * \return None.\n
1593 *
1594 */
1595 void GPMCNANDDataWrite(gpmcHandle hGpmc, Uint32 csNum, Uint32 data)
1596 {
1597 volatile Uint32 *nandData;
1599 nandData = (Uint32 *)(&hGpmc->NAND_DATA_0 + (csNum * (0x30)));
1601 *nandData = data;
1602 }
1604 /**
1605 * \brief This function reads the data from NAND DATA register.\n
1606 *
1607 * \param hGpmc GPMC handle pointing to register base address.\n
1608 *
1609 * \param csNum Chip Select Number for which NAND is interfaced.\n
1610 * This can take one of the following values :\n
1611 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1612 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1613 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1614 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1615 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1616 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1617 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1618 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1619 *
1620 * \return Read NAND data.\n
1621 *
1622 */
1623 Uint32 GPMCNANDDataRead(gpmcHandle hGpmc, Uint32 csNum)
1624 {
1625 volatile Uint32 *nandData;
1626 Uint32 data;
1628 nandData = (Uint32 *)(&hGpmc->NAND_DATA_0 + (csNum * (0x30)));
1630 data = *nandData;
1632 return (data);
1633 }
1635 /**
1636 * \brief This function selects the access mode of the prefetch engine.\n
1637 *
1638 * \param hGpmc GPMC handle pointing to register base address.\n
1639 *
1640 * \param accessMode Access mode of prefetch engine.\n
1641 * This can take one of the following values :\n
1642 * GPMC_PREFETCH_ACCESSMODE_READ -- For READ Access
1643 * mode.\n
1644 * GPMC_PREFETCH_ACCESSMODE_WRITE -- For WRITE Access
1645 * mode.\n
1646 *
1647 * \return None.\n
1648 *
1649 */
1650 void GPMCPrefetchAccessModeSelect(gpmcHandle hGpmc, Uint32 accessMode)
1651 {
1652 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1653 GPMC_PREFETCH_CONFIG1_ACCESSMODE, accessMode);
1654 }
1656 /**
1657 * \brief This function select the synchronization type to use on FIFO
1658 * threshold crossing.\n
1659 *
1660 * \param hGpmc GPMC handle pointing to register base address.\n
1661 *
1662 * \param syncType Synchronization type.\n
1663 * This can take one of the following values :\n
1664 * GPMC_PREFETCH_SYNCTYPE_DMA -- For DMA sync mode \n
1665 * GPMC_PREFETCH_SYNCTYPE_INT -- For INTERRUPT sync
1666 * mode.\n
1667 *
1668 * \return None.\n
1669 *
1670 */
1671 void GPMCPrefetchSyncTypeSelect(gpmcHandle hGpmc, Uint32 syncType)
1672 {
1673 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1674 GPMC_PREFETCH_CONFIG1_DMAMODE, syncType);
1675 }
1677 /**
1678 * \brief This function congigs when the PREFETCH engine has to start the
1679 * access to CS.\n
1680 *
1681 * \param hGpmc GPMC handle pointing to register base address.\n
1682 *
1683 * \param flag Flag to specify when PREFETCH engine has to start
1684 * the access to CS.\n
1685 * This can take one of the following values :\n
1686 * GPMC_PREFETCH_ACCESSCS_AT_START -- To start the
1687 * access as
1688 * soon as
1689 * STARTENGINE
1690 * is set.\n
1691 * GPMC_PREFETCH_ACCESSCS_AT_STARTANDWAIT -- To start the
1692 * access as
1693 * soon as
1694 * STARTENGINE
1695 * is set and
1696 * non wait
1697 * edge
1698 * detection
1699 * on the
1700 * selected
1701 * wait pin.\n
1702 *
1703 * \return None.\n
1704 *
1705 */
1706 void GPMCPrefetchSyncModeConfig(gpmcHandle hGpmc, Uint32 flag)
1707 {
1708 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1709 GPMC_PREFETCH_CONFIG1_SYNCHROMODE, flag);
1710 }
1712 /**
1713 * \brief This function selects the wait pin edge detector to start the
1714 * PREFETCH engine in synchronized mode.\n
1715 *
1716 * \param hGpmc GPMC handle pointing to register base address.\n
1717 *
1718 * \param waitPin Wait pin to use for edge detector. \n
1719 * This can take one of the following values :\n
1720 * GPMC_PREFETCH_WAITPINSELECTOR_W0 -- To Selects
1721 * Wait0EdgeDetection\n
1722 * GPMC_PREFETCH_WAITPINSELECTOR_W1 -- To Selects
1723 * Wait1EdgeDetection\n
1724 *
1725 * \return None.\n
1726 *
1727 */
1728 void GPMCPrefetchWaitPinSelect(gpmcHandle hGpmc, Uint32 waitPin)
1729 {
1730 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1731 GPMC_PREFETCH_CONFIG1_WAITPINSELECTOR, waitPin);
1732 }
1734 /**
1735 * \brief This function enables the PREFETCH POSTWRITE engine. \n
1736 *
1737 * \param hGpmc GPMC handle pointing to register base address.\n
1738 *
1739 * \return None.\n
1740 *
1741 */
1742 void GPMCPrefetchEngineEnable(gpmcHandle hGpmc)
1743 {
1744 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1745 GPMC_PREFETCH_CONFIG1_ENENGINE, GPMC_BIT_ENABLE);
1746 }
1748 /**
1749 * \brief This function disable the PREFETCH POSTWRITE engine. \n
1750 *
1751 * \param hGpmc GPMC handle pointing to register base address.\n
1752 *
1753 * \return None.\n
1754 *
1755 */
1756 void GPMCPrefetchEngineDisable(gpmcHandle hGpmc)
1757 {
1758 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1759 GPMC_PREFETCH_CONFIG1_ENENGINE, GPMC_BIT_DISABLE);
1760 }
1762 /**
1763 * \brief This function sets the FIFOTHRESHOLD (maximum number of bytes read
1764 * from the FIFO or written to the FIFO by the host on a DMA or
1765 * interrupt request) value for the PREFETCH and POSTWRITE engine.\n
1766 *
1767 * \param hGpmc GPMC handle pointing to register base address.\n
1768 *
1769 * \param fifoThrsld FIFO threshold value. \n
1770 *
1771 * \return None.\n
1772 *
1773 */
1774 void GPMCPrefetchFifoThrldValSet(gpmcHandle hGpmc, Uint32 fifoThrsld)
1775 {
1776 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1777 GPMC_PREFETCH_CONFIG1_FIFOTHR, fifoThrsld);
1778 }
1780 /**
1781 * \brief This function selects the chip select(CS) where Prefetch Postwrite
1782 * engine is active.\n
1783 *
1784 * \param hGpmc GPMC handle pointing to register base address.\n
1785 *
1786 * \param csNum Chip Select. \n
1787 * This can take one of the following values :\n
1788 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
1789 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
1790 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
1791 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
1792 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
1793 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
1794 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
1795 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
1796 *
1797 * \return None.\n
1798 *
1799 */
1800 void GPMCPrefetchCSSelect(gpmcHandle hGpmc, Uint32 csNum)
1801 {
1802 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1803 GPMC_PREFETCH_CONFIG1_ENGINECSSELECTOR, csNum);
1804 }
1806 /**
1807 * \brief This function configs the access cycle optimization for PREFETCH
1808 * engine. \n
1809 *
1810 * \param hGpmc GPMC handle pointing to register base address.\n
1811 *
1812 * \param configVal access cycle optimization config value.\n
1813 * This can take one of the following values :\n
1814 * GPMC_PREFETCH_OPTIMIZED_ACCESS_ENABLE -- To enable
1815 * the access
1816 * optimization\n
1817 * GPMC_PREFETCH_OPTIMIZED_ACCESS_DISABLE -- To disable
1818 * the access
1819 * optimization\n
1820 *
1821 * \return None.\n
1822 *
1823 */
1824 void GPMCPrefetchAccessCycleOptConfig(gpmcHandle hGpmc,
1825 Uint32 configVal)
1826 {
1827 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1828 GPMC_PREFETCH_CONFIG1_ENOPTIMIZEDACCESS, configVal);
1829 }
1831 /**
1832 * \brief This function sets the number of GPMC_FCLK cycles to be substracted
1833 * from RdCycleTime,WrCycleTime, AccessTime, CSRdOffTime, CSWrOffTime,
1834 * ADVRdOffTime,ADVWrOffTime, OEOffTime, WEOffTime for PREFETCH
1835 * engine cycle optimization. \n
1836 *
1837 * \param hGpmc GPMC handle pointing to register base address.\n
1838 *
1839 * \param cleOptVal Cycle optimization value. This can take value from
1840 * 0 to 7.\n
1841 *
1842 * \return None.\n
1843 *
1844 */
1845 void GPMCPrefetchCycleOptValSet(gpmcHandle hGpmc, Uint32 cleOptVal)
1846 {
1847 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1848 GPMC_PREFETCH_CONFIG1_CYCLEOPTIMIZATION, cleOptVal);
1849 }
1851 /**
1852 * \brief This function configs the PREFETCH and POSTWRITE ROUND
1853 * ROBIN arbitration. \n
1854 *
1855 * \param hGpmc GPMC handle pointing to register base address.\n
1856 *
1857 * \param configVal Round Robin arbitration config value.\n
1858 * This can take one of the following values :\n
1859 * GPMC_PREFETCH_RR_ARBITRATION_ENABLE -- To enable
1860 * the Round
1861 * robin
1862 * arbitration\n
1863 * GPMC_PREFETCH_RR_ARBITRATION_DISABLE -- To disable
1864 * the Round
1865 * robin
1866 * arbitration\n
1867 *
1868 * \return None.\n
1869 *
1870 */
1871 void GPMCPrefetchRRArbitrationConfig(gpmcHandle hGpmc,
1872 Uint32 configVal)
1873 {
1874 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1875 GPMC_PREFETCH_CONFIG1_PFPWENROUNDROBIN, configVal);
1876 }
1878 /**
1879 * \brief This function sets the number of access to be granted to PREFETCH
1880 * engine when ROUND ROBIN arbitration. i.e When an arbitration occurs
1881 * between a direct memory access and a PFPW engine access, the direct
1882 * memory access is always serviced. If the PFPWEnRoundRobin is enabled
1883 * value set by this function plus one number of access is granted to
1884 * the PREFETCH and WRITE POST engine.\n
1885 *
1886 * \param hGpmc GPMC handle pointing to register base address.\n
1887 *
1888 * \param accessVal Access value to set. \n
1889 *
1890 * \return None.\n
1891 *
1892 */
1893 void GPMCPrefetchWeightedPrioSet(gpmcHandle hGpmc, Uint32 accessVal)
1894 {
1895 CSL_FINS(hGpmc->PREFETCH_CONFIG1,
1896 GPMC_PREFETCH_CONFIG1_PFPWWEIGHTEDPRIO, accessVal);
1897 }
1899 /**
1900 * \brief This function sets the transfer count (number of bytes to be read or
1901 * written by the engine to the selected CS) for the PREFETCH engine.\n
1902 *
1903 * \param hGpmc GPMC handle pointing to register base address.\n
1904 *
1905 * \param trnsCntVal Tranfer count value. Value can range from 0 to 2000h
1906 * i.e 8 KB.\n
1907 *
1908 * \return None.\n
1909 *
1910 */
1911 void GPMCPrefetchTrnsCntValSet(gpmcHandle hGpmc, Uint32 trnsCntVal)
1912 {
1913 CSL_FINS(hGpmc->PREFETCH_CONFIG2,
1914 GPMC_PREFETCH_CONFIG2_TRANSFERCOUNT, trnsCntVal);
1915 }
1917 /**
1918 * \brief This function resets the FIFO pointer to 0 in prefetch mode
1919 * and 40h in postwrite mode starts the PREFETCH and POST WRITE engine.\n
1920 *
1921 * \param hGpmc GPMC handle pointing to register base address.\n
1922 *
1923 * \return None.\n
1924 *
1925 */
1926 void GPMCPrefetchEngineStart(gpmcHandle hGpmc)
1927 {
1928 CSL_FINS(hGpmc->PREFETCH_CTRL,
1929 GPMC_PREFETCH_CTRL_STARTENGINE, GPMC_BIT_SET_HIGH);
1930 }
1932 /**
1933 * \brief This function stops the PREFETCH and POST WRITE engine.\n
1934 *
1935 * \param hGpmc GPMC handle pointing to register base address.\n
1936 *
1937 * \return None.\n
1938 *
1939 */
1940 void GPMCPrefetchEngineStop(gpmcHandle hGpmc)
1941 {
1942 CSL_FINS(hGpmc->PREFETCH_CTRL,
1943 GPMC_PREFETCH_CTRL_STARTENGINE, GPMC_BIT_SET_LOW);
1944 }
1946 /**
1947 * \brief This function gets the status of PREFETCH and POST WRITE engine.\n
1948 *
1949 * \param hGpmc GPMC handle pointing to register base address.\n
1950 *
1951 * \return status Prefetch engine status\n
1952 * 0 : If engine is stopped.\n
1953 * 1 : If engine is running.\n
1954 *
1955 */
1956 Uint32 GPMCPrefetchEngineStatusGet(gpmcHandle hGpmc)
1957 {
1958 Uint32 status;
1960 status = CSL_FEXT(hGpmc->PREFETCH_CTRL,
1961 GPMC_PREFETCH_CTRL_STARTENGINE);
1963 return (status);
1964 }
1966 /**
1967 * \brief This function gets the number of remaining bytes to be read or to be
1968 * written by the engine according to the TransferCount value.\n
1969 *
1970 * \param hGpmc GPMC handle pointing to register base address.\n
1971 *
1972 * \return count value.\n
1973 *
1974 */
1975 Uint32 GPMCPrefetchCountValGet(gpmcHandle hGpmc)
1976 {
1977 Uint32 cntVal;
1979 cntVal = CSL_FEXT(hGpmc->PREFETCH_STS,
1980 GPMC_PREFETCH_STS_COUNTVALUE);
1982 return (cntVal);
1983 }
1985 /**
1986 * \brief This function gets the PREFETCH engine FIFO threshold status. \n
1987 *
1988 * \param hGpmc GPMC handle pointing to register base address.\n
1989 *
1990 * \return stauts Threshold status.\n
1991 * 1 : FIFO Pointer is greater than FIFO Threshold.\n
1992 * 0 : FIFO Pointer is smaller or equal to FIFO
1993 * Threshold.\n
1994 *
1995 */
1996 Uint32 GPMCPrefetchFifoThrldStatusGet(gpmcHandle hGpmc)
1997 {
1998 Uint32 status;
2000 status = CSL_FEXT(hGpmc->PREFETCH_STS,
2001 GPMC_PREFETCH_STS_FIFOTHRSTS);
2003 return (status);
2004 }
2006 /**
2007 * \brief This function gets the FIFO pointer value of PREFETCH engine.
2008 * FIFO pointer value indicates number of bytes available to be read
2009 * or number of free empty place to write.\n
2010 *
2011 * \param hGpmc GPMC handle pointing to register base address.\n
2012 *
2013 * \return FIFO pointer value.\n
2014 *
2015 */
2016 Uint32 GPMCPrefetchFifoPtrValGet(gpmcHandle hGpmc)
2017 {
2018 Uint32 fifoPtrVal;
2020 fifoPtrVal = CSL_FEXT(hGpmc->PREFETCH_STS,
2021 GPMC_PREFETCH_STS_FIFOPOINTER);
2023 return (fifoPtrVal);
2024 }
2026 /**
2027 * \brief This function selects the ECC algorithm to use for ECC error
2028 * detection and correction.\n
2029 *
2030 * \param hGpmc GPMC handle pointing to register base address.\n
2031 *
2032 * \param eccAlgo ECC algorithm to use.\n
2033 * This can take one of the following values :\n
2034 * GPMC_ECC_ALGORITHM_HAMMINGCODE -- For Hamming code.\n
2035 * GPMC_ECC_ALGORITHM_BCH -- For BCH.\n
2036 * \return None.\n
2037 *
2038 */
2039 void GPMCECCAlgoSelect(gpmcHandle hGpmc, Uint32 algo)
2040 {
2041 CSL_FINS(hGpmc->ECC_CONFIG, GPMC_ECC_CONFIG_ECCALGORITHM, algo);
2042 }
2044 /**
2045 * \brief This function selects the Error correction capability used for BCH
2046 * ECC algorithm.\n
2047 *
2048 * \param hGpmc GPMC handle pointing to register base address.\n
2049 *
2050 * \param errCorrCapVal Error correction capability value.\n
2051 * This can take one of the following values :\n
2052 * GPMC_ECC_BCH_ERRCORRCAP_UPTO_4BITS -- For Up to 4
2053 * bits error
2054 * correction.\n
2055 * GPMC_ECC_BCH_ERRCORRCAP_UPTO_8BITS -- For Up to 8
2056 * bits error
2057 * correction.\n
2058 * GPMC_ECC_BCH_ERRCORRCAP_UPTO_16BITS -- For Up to 16
2059 * bits error
2060 * correction.\n
2061 *
2062 * \return None.\n
2063 *
2064 */
2065 void GPMCECCBCHErrCorrectionCapSelect(gpmcHandle hGpmc,
2066 Uint32 errCorrCapVal)
2067 {
2068 CSL_FINS(hGpmc->ECC_CONFIG, GPMC_ECC_CONFIG_ECCBCHTSEL,
2069 errCorrCapVal);
2070 }
2072 /**
2073 * \brief This function sets the wrap mode(Spare area organization definition)
2074 * for the ECC BCH algorithm.\n
2075 *
2076 * \param hGpmc GPMC handle pointing to register base address.\n
2077 *
2078 * \param wrapModeVal Wrap mode value. Value can range from 0x00 to 0x0F.\n
2079 *
2080 * \return None.\n
2081 *
2082 */
2083 void GPMCECCBCHWrapModeValSet(gpmcHandle hGpmc, Uint32 wrapModeVal)
2084 {
2085 CSL_FINS(hGpmc->ECC_CONFIG, GPMC_ECC_CONFIG_ECCWRAPMODE,
2086 wrapModeVal);
2087 }
2089 /**
2090 * \brief This function selects number of columns to use for ECC calculation.\n
2091 *
2092 * \param hGpmc GPMC handle pointing to register base address.\n
2093 *
2094 * \param eccColVal ECC column value.\n
2095 * This can take one of the following values :\n
2096 * GPMC_ECC_COLUMNS_8 -- ECC calculated on 8 columns.\n
2097 * GPMC_ECC_COLUMNS_16 -- ECC calculated on 16 columns.\n
2098 *
2099 * \return None.\n
2100 *
2101 */
2102 void GPMCECCColumnSelect(gpmcHandle hGpmc, Uint32 eccColVal)
2103 {
2104 CSL_FINS(hGpmc->ECC_CONFIG, GPMC_ECC_CONFIG_ECC16B, eccColVal);
2105 }
2107 /**
2108 * \brief This function selects the number of sectors to process with the BCH
2109 * algorithm.\n
2110 *
2111 * \param hGpmc GPMC handle pointing to register base address.\n
2112 *
2113 * \param numOfSects Number of sectors.\n
2114 * This can take one of the following values :\n
2115 * GPMC_ECC_BCH_NUMOFSECTS_1 -- For 1 sector (512 bytes
2116 * page).\n
2117 * GPMC_ECC_BCH_NUMOFSECTS_2 -- For 2 sectors. \n
2118 * GPMC_ECC_BCH_NUMOFSECTS_3 -- For 3 sectors. \n
2119 * GPMC_ECC_BCH_NUMOFSECTS_4 -- For 4 sectors. \n
2120 * GPMC_ECC_BCH_NUMOFSECTS_5 -- For 5 sectors. \n
2121 * GPMC_ECC_BCH_NUMOFSECTS_6 -- For 6 sectors. \n
2122 * GPMC_ECC_BCH_NUMOFSECTS_7 -- For 7 sectors. \n
2123 * GPMC_ECC_BCH_NUMOFSECTS_8 -- For 8 sectors
2124 * (4KB page).\n
2125 *
2126 * \return None.\n
2127 *
2128 */
2129 void GPMCECCBCHNumOfSectorsSelect(gpmcHandle hGpmc,
2130 Uint32 numOfSects)
2131 {
2132 CSL_FINS(hGpmc->ECC_CONFIG, GPMC_ECC_CONFIG_ECCTOPSECTOR,
2133 numOfSects);
2134 }
2136 /**
2137 * \brief This function selects the Chip-select where ECC is computed.\n
2138 *
2139 * \param hGpmc GPMC handle pointing to register base address.\n
2140 *
2141 * \param csNum Chip Select. \n
2142 * This can take one of the following values :\n
2143 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
2144 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
2145 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
2146 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
2147 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
2148 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
2149 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
2150 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
2151 *
2152 * \return None.\n
2153 *
2154 */
2155 void GPMCECCCSSelect(gpmcHandle hGpmc, Uint32 csNum)
2156 {
2157 CSL_FINS(hGpmc->ECC_CONFIG, GPMC_ECC_CONFIG_ECCCS, csNum);
2158 }
2160 /**
2161 * \brief This function Enables the ECC feature.\n
2162 *
2163 * \param hGpmc GPMC handle pointing to register base address.\n
2164 *
2165 * \return None.\n
2166 *
2167 */
2168 void GPMCECCEnable(gpmcHandle hGpmc)
2169 {
2170 CSL_FINS(hGpmc->ECC_CONFIG, GPMC_ECC_CONFIG_ECCEN,
2171 GPMC_BIT_ENABLE);
2172 }
2174 /**
2175 * \brief This function disables the ECC feature.\n
2176 *
2177 * \param hGpmc GPMC handle pointing to register base address.\n
2178 *
2179 * \return None.\n
2180 *
2181 */
2182 void GPMCECCDisable(gpmcHandle hGpmc)
2183 {
2184 CSL_FINS(hGpmc->ECC_CONFIG, GPMC_ECC_CONFIG_ECCEN,
2185 GPMC_BIT_DISABLE);
2186 }
2188 /**
2189 * \brief This function clears all ECC result registers.\n
2190 *
2191 * \param hGpmc GPMC handle pointing to register base address.\n
2192 *
2193 * \return None.\n
2194 *
2195 */
2196 void GPMCECCResultRegClear(gpmcHandle hGpmc)
2197 {
2198 CSL_FINS(hGpmc->ECC_CTRL, GPMC_ECC_CTRL_ECCCLR,
2199 GPMC_BIT_SET_HIGH);
2200 }
2202 /**
2203 * \brief This function selects the ECC result register where the first
2204 * ECC computation will be stored.\n
2205 *
2206 * \param hGpmc GPMC handle pointing to register base address.\n
2207 *
2208 * \param eccResReg ECC result register.\n
2209 * This can take one of the following values :\n
2210 * GPMC_ECCPOINTER_RESULT_1 -- ECC pointer for result 1
2211 * register.\n
2212 * GPMC_ECCPOINTER_RESULT_2 -- ECC pointer for result 2
2213 * register.\n
2214 * GPMC_ECCPOINTER_RESULT_3 -- ECC pointer for result 3
2215 * register.\n
2216 * GPMC_ECCPOINTER_RESULT_4 -- ECC pointer for result 4
2217 * register.\n
2218 * GPMC_ECCPOINTER_RESULT_5 -- ECC pointer for result 5
2219 * register.\n
2220 * GPMC_ECCPOINTER_RESULT_6 -- ECC pointer for result 6
2221 * register.\n
2222 * GPMC_ECCPOINTER_RESULT_7 -- ECC pointer for result 7
2223 * register.\n
2224 * GPMC_ECCPOINTER_RESULT_8 -- ECC pointer for result 8
2225 * register.\n
2226 * GPMC_ECCPOINTER_RESULT_9 -- ECC pointer for result 9
2227 * register.\n
2228 *
2229 * \return None.\n
2230 *
2231 */
2232 void GPMCECCResultRegSelect(gpmcHandle hGpmc, Uint32 eccResReg)
2233 {
2234 CSL_FINS(hGpmc->ECC_CTRL, GPMC_ECC_CTRL_ECCPOINTER,
2235 eccResReg);
2236 }
2238 /**
2239 * \brief This function sets the ECCSIZE1 value. \n
2240 *
2241 * \param hGpmc GPMC handle pointing to register base address.\n
2242 *
2243 * \param eccSize ECC size for which size has to set.\n
2244 * This can take one of the following values :\n
2245 * GPMC_ECC_SIZE_0 -- For ECC size 0.\n
2246 * GPMC_ECC_SIZE_1 -- For ECC size 1.\n
2247 *
2248 * \param eccSizeVal ECC size value.\n
2249 *
2250 * \return None.\n
2251 *
2252 */
2253 void GPMCECCSizeValSet(gpmcHandle hGpmc,Uint32 eccSize,
2254 Uint32 eccSizeVal)
2255 {
2256 if(eccSize == GPMC_ECC_SIZE_0)
2257 {
2258 CSL_FINS(hGpmc->ECC_SIZE_CONFIG, GPMC_ECC_SIZE_CONFIG_ECCSIZE0,
2259 eccSizeVal);
2260 }
2261 else if(eccSize == GPMC_ECC_SIZE_1)
2262 {
2263 CSL_FINS(hGpmc->ECC_SIZE_CONFIG, GPMC_ECC_SIZE_CONFIG_ECCSIZE1,
2264 eccSizeVal);
2265 }
2266 }
2268 /**
2269 * \brief This function selects the ECC size for the ECC result register. \n
2270 *
2271 * \param hGpmc GPMC handle pointing to register base address.\n
2272 *
2273 * \param eccResReg ECC result register for which ECC size has to select.\n
2274 * This can take one of the following values :\n
2275 * GPMC_ECC_RESULT_1 -- For ECC result 1 register.\n
2276 * GPMC_ECC_RESULT_2 -- For ECC result 2 register.\n
2277 * GPMC_ECC_RESULT_3 -- For ECC result 3 register.\n
2278 * GPMC_ECC_RESULT_4 -- For ECC result 4 register.\n
2279 * GPMC_ECC_RESULT_5 -- For ECC result 5 register.\n
2280 * GPMC_ECC_RESULT_6 -- For ECC result 6 register.\n
2281 * GPMC_ECC_RESULT_7 -- For ECC result 7 register.\n
2282 * GPMC_ECC_RESULT_8 -- For ECC result 8 register.\n
2283 * GPMC_ECC_RESULT_9 -- For ECC result 9 register.\n
2284 *
2285 * \param eccSize ECC size.\n
2286 * This can take one of the following values :\n
2287 * GPMC_ECC_SIZE_0 -- For ECC size 0.\n
2288 * GPMC_ECC_SIZE_1 -- For ECC size 1.\n
2289 *
2290 \return None.\n
2291 *
2292 */
2293 void GPMCECCResultSizeSelect(gpmcHandle hGpmc, Uint32 eccResReg,
2294 Uint32 eccSize)
2295 {
2296 switch(eccResReg)
2297 {
2298 case GPMC_ECC_RESULT_1:
2299 CSL_FINS(hGpmc->ECC_SIZE_CONFIG,
2300 GPMC_ECC_SIZE_CONFIG_ECC1RESULTSIZE, eccSize);
2301 break;
2302 case GPMC_ECC_RESULT_2:
2303 CSL_FINS(hGpmc->ECC_SIZE_CONFIG,
2304 GPMC_ECC_SIZE_CONFIG_ECC2RESULTSIZE, eccSize);
2305 break;
2306 case GPMC_ECC_RESULT_3:
2307 CSL_FINS(hGpmc->ECC_SIZE_CONFIG,
2308 GPMC_ECC_SIZE_CONFIG_ECC3RESULTSIZE, eccSize);
2309 break;
2310 case GPMC_ECC_RESULT_4:
2311 CSL_FINS(hGpmc->ECC_SIZE_CONFIG,
2312 GPMC_ECC_SIZE_CONFIG_ECC4RESULTSIZE, eccSize);
2313 break;
2314 case GPMC_ECC_RESULT_5:
2315 CSL_FINS(hGpmc->ECC_SIZE_CONFIG,
2316 GPMC_ECC_SIZE_CONFIG_ECC5RESULTSIZE, eccSize);
2317 break;
2318 case GPMC_ECC_RESULT_6:
2319 CSL_FINS(hGpmc->ECC_SIZE_CONFIG,
2320 GPMC_ECC_SIZE_CONFIG_ECC6RESULTSIZE, eccSize);
2321 break;
2322 case GPMC_ECC_RESULT_7:
2323 CSL_FINS(hGpmc->ECC_SIZE_CONFIG,
2324 GPMC_ECC_SIZE_CONFIG_ECC7RESULTSIZE, eccSize);
2325 break;
2326 case GPMC_ECC_RESULT_8:
2327 CSL_FINS(hGpmc->ECC_SIZE_CONFIG,
2328 GPMC_ECC_SIZE_CONFIG_ECC8RESULTSIZE, eccSize);
2329 break;
2330 case GPMC_ECC_RESULT_9:
2331 CSL_FINS(hGpmc->ECC_SIZE_CONFIG,
2332 GPMC_ECC_SIZE_CONFIG_ECC9RESULTSIZE, eccSize);
2333 break;
2334 }
2335 }
2337 /**
2338 * \brief This function gets the ECC result from the ECC register.\n
2339 *
2340 * \param hGpmc GPMC handle pointing to register base address.\n
2341 *
2342 * \param eccResReg ECC result register for from which ECC value has to
2343 * retrive.\n
2344 * This can take one of the following values :\n
2345 * GPMC_ECC_RESULT_1 -- For ECC result 1 register.\n
2346 * GPMC_ECC_RESULT_2 -- For ECC result 2 register.\n
2347 * GPMC_ECC_RESULT_3 -- For ECC result 3 register.\n
2348 * GPMC_ECC_RESULT_4 -- For ECC result 4 register.\n
2349 * GPMC_ECC_RESULT_5 -- For ECC result 5 register.\n
2350 * GPMC_ECC_RESULT_6 -- For ECC result 6 register.\n
2351 * GPMC_ECC_RESULT_7 -- For ECC result 7 register.\n
2352 * GPMC_ECC_RESULT_8 -- For ECC result 8 register.\n
2353 * GPMC_ECC_RESULT_9 -- For ECC result 9 register.\n
2354 *
2355 * \return ECC result.\n
2356 *
2357 */
2358 Uint32 GPMCECCResultGet(gpmcHandle hGpmc, Uint32 eccResReg)
2359 {
2360 Uint32 res;
2361 volatile Uint32 *eccRes;
2363 eccRes = (Uint32 *)(&hGpmc->ECC1_RESULT + ((eccResReg - 1) * 0x4));
2365 res = *eccRes;
2367 return (res);
2368 }
2370 /**
2371 * \brief This function gets the BCH result.\n
2372 *
2373 * \param hGpmc GPMC handle pointing to register base address.\n
2374 *
2375 * \param resIndex BCH ECC result index.\n
2376 * This can take one of the following values :\n
2377 * GPMC_BCH_RESULT_0 -- For BCH result 0.\n
2378 * GPMC_BCH_RESULT_1 -- For BCH result 1.\n
2379 * GPMC_BCH_RESULT_2 -- For BCH result 2.\n
2380 * GPMC_BCH_RESULT_3 -- For BCH result 3.\n
2381 * GPMC_BCH_RESULT_4 -- For BCH result 4.\n
2382 * GPMC_BCH_RESULT_5 -- For BCH result 5.\n
2383 * GPMC_BCH_RESULT_6 -- For BCH result 6.\n
2384 *
2385 * \param csNum Chip Select. \n
2386 * This can take one of the following values :\n
2387 * GPMC_CHIP_SELECT_0 -- For Chip Select 0.\n
2388 * GPMC_CHIP_SELECT_1 -- For Chip Select 1.\n
2389 * GPMC_CHIP_SELECT_2 -- For Chip Select 2.\n
2390 * GPMC_CHIP_SELECT_3 -- For Chip Select 3.\n
2391 * GPMC_CHIP_SELECT_4 -- For Chip Select 4.\n
2392 * GPMC_CHIP_SELECT_5 -- For Chip Select 5.\n
2393 * GPMC_CHIP_SELECT_6 -- For Chip Select 6.\n
2394 * GPMC_CHIP_SELECT_7 -- For Chip Select 7.\n
2396 * \return ECC result.\n
2397 *
2398 */
2399 Uint32 GPMCECCBCHResultGet(gpmcHandle hGpmc, Uint32 resIndex, Uint32 csNum)
2400 {
2401 Uint32 res;
2402 volatile Uint32 *bchResReg;
2404 res = 0;
2406 switch(resIndex)
2407 {
2408 case GPMC_BCH_RESULT_0:
2409 bchResReg = (Uint32 *)(&hGpmc->BCH_RESULT0_0 + (csNum * 0x10));
2410 res = *bchResReg;
2411 break;
2412 case GPMC_BCH_RESULT_1:
2413 bchResReg = (Uint32 *)(&hGpmc->BCH_RESULT1_0 + (csNum * 0x10));
2414 res = *bchResReg;
2415 break;
2416 case GPMC_BCH_RESULT_2:
2417 bchResReg = (Uint32 *)(&hGpmc->BCH_RESULT2_0 + (csNum * 0x10));
2418 res = *bchResReg;
2419 break;
2420 case GPMC_BCH_RESULT_3:
2421 bchResReg = (Uint32 *)(&hGpmc->BCH_RESULT3_0 + (csNum * 0x10));
2422 res = *bchResReg;
2423 break;
2424 case GPMC_BCH_RESULT_4:
2425 bchResReg = (Uint32 *)(&hGpmc->BCH_RESULT4_0 + (csNum * 0x10));
2426 res = *bchResReg;
2427 break;
2428 case GPMC_BCH_RESULT_5:
2429 bchResReg = (Uint32 *)(&hGpmc->BCH_RESULT5_0 + (csNum * 0x10));
2430 res = *bchResReg;
2431 break;
2432 case GPMC_BCH_RESULT_6:
2433 bchResReg = (Uint32 *)(&hGpmc->BCH_RESULT6_0 + (csNum * 0x10));
2434 res = *bchResReg;
2435 break;
2436 }
2438 return (res);
2439 }
2441 /**
2442 * \brief This function write the data to BCH_SWDATA register. This is used
2443 * to directly padd data to the BCH ECC calculator without accessing
2444 * the actual NAND flash interface.\n
2445 *
2446 * \param hGpmc GPMC handle pointing to register base address.\n
2447 *
2448 * \param bchData BCH data to be included in the BCH calculation.
2449 * Only bits 0 to 7 are taken into account, if
2450 * the calculator is configured to use 8 bits data
2451 * using GPMCECCColumnSelect function.\n
2452 *
2453 * \return None.\n
2454 *
2455 */
2456 void GPMCECCBCHSWDataWrite(gpmcHandle hGpmc, Uint32 bchData)
2457 {
2458 CSL_FINS(hGpmc->BCH_SWDATA, GPMC_BCH_SWDATA_BCH_DATA, bchData);
2459 }
2461 /**
2462 * \brief This function read the data from BCH_SWDATA register.
2463 *
2464 * \param hGpmc GPMC handle pointing to register base address.\n
2465 *
2466 * \return None.\n
2467 *
2468 */
2469 Uint32 GPMCECCBCHSWDataRead(gpmcHandle hGpmc)
2470 {
2471 Uint32 bchData;
2473 bchData = CSL_FEXT(hGpmc->BCH_SWDATA, GPMC_BCH_SWDATA_BCH_DATA);
2475 return (bchData);
2476 }
2478 /***************************** End Of File ***********************************/