psdk_cust/pdk_k2g_1_0_1_2_eng/packages/ti/board/src/flash/platform_flash/evmc66x_nand.h

   1 /*
   2  * Copyright (c) 2011-2015, Texas Instruments Incorporated
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * *  Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  * *  Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * *  Neither the name of Texas Instruments Incorporated nor the names of
  17  *    its contributors may be used to endorse or promote products derived
  18  *    from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  24  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  27  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  28  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  29  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  */
  33
  34 /**
  35  *
  36  * \file  evmc66x_nand.h
  37  *
  38  * \brief This is the header file for Nand flash API's.
  39  ******************************************************************************/
  40
  41 #ifndef _EVMC66X_NAND_H_
  42 #define _EVMC66X_NAND_H_
  43
  44 /*********************************
  45  * Defines and Macros and globals
  46  *********************************/
  47
  48 /* NAND chip select ID */
  49 #define NAND_CS            (0)
  50
  51 /* NAND FLASH ADDRESS */
  52 #define NAND_CMD_ADDR      (GPMC_CMD_REG(NAND_CS))
  53 #define NAND_ALE_ADDR      (GPMC_ADDR_REG(NAND_CS))
  54 #define NAND_DATA_ADDR     (GPMC_DATA_REG(NAND_CS))
  55
  56 #define NAND_TYPE_MASK_0X00000020               (0x00000020)
  57
  58 /* NAND FLASH COMMANDS */
  59
  60 #define NAND_ADD_00H                    (0x00)
  61 #define NAND_ADD_08H                    (0x08)
  62 #define NAND_CMD_05H                    (0x05)  /* Random Data Read Command */
  63 #define NAND_CMD_10H                    (0x10)  /* Program Confirm Command */
  64 #define NAND_CMD_30H                    (0x30)
  65 #define NAND_CMD_E0H                    (0xE0)
  66 #define NAND_BLOCK_ERASE                (0x60)  /* Block Erase Command */
  67 #define NAND_ERASE_CONFIRM              (0xD0)  /* Erase Confirm Command */
  68 #define NAND_GET_FEATURES               (0xEE)
  69 #define NAND_OTP_DATA_PROG              (0xA0)
  70 #define NAND_OTP_DATA_PROT              (0xA5)
  71 #define NAND_OTP_DATA_READ              (0xAF)
  72 #define NAND_PAGE_READ                  (0x00)  /* Page Read Command */
  73 #define NAND_PAGE_READ_LAST             (0x3F)  /* Page Read Cache Mode Start Last*/
  74 #define NAND_PAGE_READ_RANDOM           (0x00)
  75 #define NAND_PAGE_READ_SEQUENTIAL       (0x31)  /* page Read Cache mode start */
  76 #define NAND_INT_DATA_MOVE_PROG         (0x85)  /* Program for Internal Data Move */
  77 #define NAND_PROG_PAGE                  (0x80)  /* Program Page Command */
  78 #define NAND_PROG_PAGE_CACHE            (0x80)  /* Program Page command */
  79 #define NAND_RANDOM_DATA_IN             (0x85)  /* Program for internal Data Move */
  80 #define NAND_RANDOM_DATA_READ           (0x05)
  81 #define NAND_INT_DATA_MOVE_READ         (0xA5)
  82 #define NAND_RDID                       (0x90)  /* Read NAND ID Command */
  83 #define NAND_READ_PARAM_PAGE            (0xEC)
  84 #define NAND_STATUS                     (0x70)  /* Read Status command */
  85 #define NAND_READ_UNIQUE_ID             (0xED)
  86 #define NAND_RST                        (0xFF)  /* Reset Command */
  87 #define NAND_RDY                        (0x40)
  88 #define NAND_RDIDADD                    (0x20)
  89
  90 /* Maximum number of ECC bytes per page */
  91 #define NAND_MAX_NUM_ECC_BYTES          (NAND_ECC_BCH_8BIT_BYTECNT)
  92
  93  /**
  94  @}
  95  */
  96 /****************
  97  * Defines
  98  ****************/
  99 #define PACK_ADDR(col, page, block) \
 100                 ((col & 0x00000fff) | ((page & 0x0000003f)<<16) | ((block & 0x000003ff) << 22 ))
 101
 102 // Macros for delay in micro Sec
 103 #define STD_DELAY                                        (25)
 104 #define NAND_PROG_TIMEOUT            (100000)
 105 #define NAND_RESET_TIMEOUT           (100000)
 106 #define NAND_BLOCK_ERASE_TIMEOUT     (2000000)
 107 #define NAND_WAIT_PIN_POLL_ST_DLY    (10)
 108
 109
 110 // Macros for errors
 111 #define INVALID_NAND_ADDR                       (8)
 112 #define NAND_PAGE_WRITE_FAIL            (9)
 113 #define NAND_SPARE_AREA_WRITE_FAIL      (10)
 114 #define NAND_PAGE_READ_FAIL                     (11)
 115 #define NAND_SPARE_AREA_READ_FAIL       (12)
 116 #define NAND_BLOCK_ERASE_FAIL           (13)
 117 #define NAND_ID_READ_ERROR                      (14)
 118 #define NAND_TWO_BIT_ERROR                      (15)
 119 #define INVALID_NAND_DEVICE                     (16)
 120
 121 #define NAND_MAN_ID_MICRON                      (0x2C)
 122 #define NAND_DEVICE_ID                          (0xCA)
 123
 124 #define BYTES_PER_PAGE                          (2048)
 125 #define SPARE_BYTES_PER_PAGE            (64)
 126 #define PAGES_PER_BLOCK                         (64)
 127 #define TOTAL_BYTES_PER_PAGE            (BYTES_PER_PAGE + SPARE_BYTES_PER_PAGE)
 128 #define BLOCKS_PER_DEVICE                       (2048)
 129
 130 // ECC related macros
 131 #define ECC_BLOCK_SIZE                          (512)   // in Bytes
 132 #define ECC_SPARE_OFFSET                        (SPARE_BYTES_PER_PAGE/(BYTES_PER_PAGE/ECC_BLOCK_SIZE))
 133
 134 // NAND flags
 135 #define NAND_FLAG_LINUX             (0x0)
 136 #define NAND_FLAG_RBL               (0x1)
 137
 138 /*
 139 ** Macros which defines the chip select base address and cs region size.
 140 **
 141 */
 142 #define NAND_CS0_BASEADDR                       (0x4000000)//(0x10000000)
 143 #define NAND_CS0_REGIONSIZE                     (GPMC_CS_SIZE_64MB)//(GPMC_CS_SIZE_256MB)
 144
 145 /*
 146 ** Macros which defines the NAND timing info.
 147 **
 148 */
 149 #define NAND_CSWROFFTIME                        (20)
 150 #define NAND_CSRDOFFTIME                        (20)
 151 #define NAND_CSONTIME                           (0)
 152
 153 #define NAND_ADVONTIME                          (0)
 154 #define NAND_ADVAADMUXONTIME                    (0)
 155 #define NAND_ADVRDOFFTIME                       (20)
 156 #define NAND_ADVWROFFTIME                       (20)
 157 #define NAND_ADVAADMUXRDOFFTIME                 (0)
 158 #define NAND_ADVAADMUXWROFFTIME                 (0)
 159
 160 #define NAND_WEOFFTIME                          (15)
 161 #define NAND_WEONTIME                           (1)
 162 #define NAND_OEAADMUXOFFTIME                    (0)
 163 #define NAND_OEOFFTIME                          (15)
 164 #define NAND_OEAADMUXONTIME                     (0)
 165 #define NAND_OEONTIME                           (1)
 166
 167 #define NAND_RDCYCLETIME                        (20)
 168 #define NAND_WRCYCLETIME                        (20)
 169 #define NAND_RDACCESSTIME                       (12)
 170 #define NAND_PAGEBURSTACCESSTIME                (1)
 171
 172 #define NAND_BUSTURNAROUND                      (0)
 173 #define NAND_CYCLE2CYCLEDIFFCSEN                (0)
 174 #define NAND_CYCLE2CYCLESAMECSEN                (1)
 175 #define NAND_CYCLE2CYCLEDELAY                   (10)
 176 #define NAND_WRDATAONADMUXBUS                   (15)
 177 #define NAND_WRACCESSTIME                       (31)
 178
 179 typedef struct _NAND_ADDR
 180 {
 181     uint32_t uiColumnAddr;
 182     uint32_t uiPageAddr;
 183     uint32_t uiBlockAddr;
 184 } NAND_ADDR;
 185
 186 typedef struct  {
 187     uint32_t uiDeviceID;                // DeviceID
 188     uint32_t uiPageCount;               // Page count per block
 189     uint32_t uiPageSize;                // Byte count per page(include redundant parts)
 190     uint32_t blk_shift;         // Number of bits by which block address is to be shifted
 191     uint32_t addr_cycles;               // Number of address cycles
 192 } StdNANDDeviceInfoObj;
 193
 194 //  NAND_info structure
 195 typedef struct  {
 196     uint32_t uiNandWidth;               // NAND width 1-&gt;16 bits 0-&gt;8 bits
 197     uint32_t dev_code;          // NAND_DevTable index
 198     uint32_t uiPageCount;               // page count per block
 199     uint32_t addr_cycles;               // Number of address cycles
 200     uint32_t big_block;         // 1 - Big block device, 0 - small block device
 201     uint32_t uiPageSize;                // Number of bytes in a page including extra data 264/528
 202     uint32_t blk_shift;         // Number of bits by which block address is to be shifted
 203     uint32_t page_shift;                // Number of bits by which      page address is to be shifted
 204     uint32_t numPage;                   // Number of pages where boot loader is stored
 205     uint32_t block;                     // starting block number where User boot loader is stored
 206     uint32_t page;                      // starting page number where boot-loader is stored
 207 } StdNANDBootInfoObj;
 208
 209 /************************
 210  * Function declarations
 211  ************************/
 212 uint32_t nandInit(void);
 213 uint32_t readNandPage(PLATFORM_DEVICE_info* pNandInfo, NAND_ADDR address, uint8_t* puchBuffer);
 214 uint32_t writeNandPage(PLATFORM_DEVICE_info* pNandInfo, NAND_ADDR address,      uint8_t* puchBuffer);
 215 uint32_t nandFlashBlockErase(PLATFORM_DEVICE_info* pNandInfo, uint32_t uiBlockNumber);
 216 uint32_t NandGetDetails(PLATFORM_DEVICE_info* pNandInfo);
 217 uint32_t NandReadSpareArea(PLATFORM_DEVICE_info* pNandInfo, uint32_t uiBlkAddr, uint32_t uiPage, uint8_t *pBuffer);
 218 uint32_t NandWriteSpareArea (PLATFORM_DEVICE_info* pNandInfo, uint32_t uiBlkAddr, uint32_t uiPage, uint8_t *pBuffer);
 219
 220 #endif /* _EVMC66X_NAND_H_ */