[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_2_eng / packages / ti / board / src / idkAM571x / idkAM571x_ddr.c
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2 * Copyright (c) 2010-2015 Texas Instruments Incorporated - http://www.ti.com
3 *
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32 *****************************************************************************/
34 #include "board_cfg.h"
35 #include "board_internal.h"
37 #include <ti/csl/csl_emif4fAux.h>
38 #include <ti/csl/cslr_dmm.h>
39 #include <ti/csl/cslr_ma_mpu_lsm.h>
40 #include <ti/csl/src/ip/emif4/V2/csl_emif4d5.h>
42 /** \brief Compute EMIF phy control. */
43 #define EXT_PHY_CTRL_VALUE(ctrlSlaveRatio) \
44 ((ctrlSlaveRatio << 20U) | (ctrlSlaveRatio << 10U) | (ctrlSlaveRatio << 0U))
46 /** \brief Compute EMIF phy FIFO WE. */
47 #define EXT_PHY_FIFO_WE_VALUE(fifoWeSlaveRatio) \
48 ((fifoWeSlaveRatio << 16U) | (fifoWeSlaveRatio << 0U))
50 /** \brief Compute EMIF phy read DQS. */
51 #define EXT_PHY_RD_DQS_VALUE(rdDqsSlaveRatio) \
52 ((rdDqsSlaveRatio << 16U) | (rdDqsSlaveRatio << 0U))
54 /** \brief Compute EMIF phy write data. */
55 #define EXT_PHY_WR_DATA_VALUE(wrDataslaveRatio) \
56 ((wrDataslaveRatio << 16U) | (wrDataslaveRatio << 0U))
58 /** \brief Compute EMIF phy write DQS. */
59 #define EXT_PHY_WR_DQS_VALUE(wrDqsSlaveRatio) \
60 ((wrDqsSlaveRatio << 16U) | (wrDqsSlaveRatio << 0U))
62 /** \brief Compute EMIF phy DQ. */
63 #define EXT_PHY_DQ_VALUE(dqOffset) \
64 ((dqOffset << 21U) | (dqOffset << 14U) | (dqOffset << 7U) | (dqOffset << 0U))
66 /** \brief Compute EMIF phy gate level init. */
67 #define EXT_PHY_GATE_LVL_INIT_VALUE(gateLvlInitRatio) \
68 ((gateLvlInitRatio << 16U) | (gateLvlInitRatio << 0U))
70 /** \brief Compute EMIF phy gate level init. */
71 #define EXT_PHY_WR_LVL_INIT_VALUE(wrLvlInitRatio) \
72 ((wrLvlInitRatio << 16U) | (wrLvlInitRatio << 0U))
74 /** \brief Compute EMIF phy . */
75 #define EXT_PHY_RANK0_DELAY_VALUE(dqOffset, gateLvlInitRatio, rank0Delay, \
76 wrDataslaveRatio) \
77 ((dqOffset << 24U) | (gateLvlInitRatio << 16U) | (rank0Delay << 12U) | \
78 (wrDataslaveRatio << 0U))
80 /** \brief Compute EMIF phy slave and Rank0 delays. */
81 #define EXT_PHY_RANK0_DELAY_MODE(dqOffset, gateLvlInitMode, rank0Delay, \
82 wrDataslaveDelay) \
83 ((dqOffset << 24U) | (gateLvlInitMode << 16U) | (rank0Delay << 12U) | \
84 (wrDataslaveDelay << 0U))
86 /** \brief Compute FIFO_WE_IN and Phy control slave delay .*/
87 #define EXT_PHY_FIFO_WE_SLAVE_CTRL_DELAY(fifoWeInDelay, ctrlSlaveDelay) \
88 ((fifoWeInDelay << 16U) | (ctrlSlaveDelay << 0U))
90 /** \brief Compute WR_LVL_NUM_DQ0 and GATE_LVL_NUM_DQ0.*/
91 #define EXT_PHY_WR_LVL_GATE_LVL_NUM_DQ0(wrLvlNumDq0, gateLvlNumDq0) \
92 ((wrLvlNumDq0 << 4U) | (gateLvlNumDq0 << 0U))
94 /** \brief Compute Read and WriteDQS slave delay. */
95 #define EXT_PHY_WR_RD_DQS_SLAVE_DELAY(wrDqsSlaveDelay, rdDqsSlaveDelay) \
96 ((wrDqsSlaveDelay << 16U) | (rdDqsSlaveDelay << 0U))
98 #define DDR_PHY_CTRL1_VALUE(emif_phy_read_latency, emif_phy_fast_dll_lock, \
99 emif_phy_dll_lock_diff, emif_phy_invert_clkout, emif_phy_dis_calib_rst, \
100 emif_phy_half_delay_mode, emif_phy_levelling_disabled) \
101 ((emif_phy_read_latency << 0U) | (emif_phy_fast_dll_lock << 9U) | \
102 (emif_phy_dll_lock_diff << 10U) | (emif_phy_invert_clkout << 18U) | \
103 (emif_phy_dis_calib_rst << 19U) | (emif_phy_half_delay_mode << 21U) | \
104 (emif_phy_levelling_disabled))
107 #define MPU_DEVICE_PRM_REGS (0x4ae07d00U)
108 #define PRM_RSTST_REG (0x4U)
109 #define PRM_RSTST_EXTERNAL_WARM_RST_MASK (0x00000020U)
110 #define PRM_RSTST_GLOBAL_WARM_SW_RST_MASK (0x00000002U)
112 #define HW_WR_REG32(addr, data) *(unsigned int*)(addr) =(unsigned int)(data)
113 #define HW_RD_REG32(x) (*((volatile uint32_t *)(x)))
115 /**< IODFT TLGC */
116 uint32_t ioDftLogicCtrl;
118 /**< Read Write level ramp window*/
119 uint32_t readWriteLvlRampWin;
121 static void ddr_delay(uint32_t ix);
123 static void emif_ddr3_updateHwLevelOutput(CSL_emifHandle hEmif);
125 static void ddr_delay(uint32_t ix)
126 {
127 while (ix--) {
128 asm(" NOP");
129 }
130 }
132 int emifConfigureDdr3
133 (
134 CSL_emifHandle hEmif,
135 CSL_emifDdrConfig *ddr3Config,
136 Uint32 enableHwLeveling
137 );
139 /* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
140 Board_STATUS Board_DDR3Init()
141 {
142 int retVal = BOARD_SOK;
143 CSL_emifObj emifObj1;
144 CSL_emifHandle hEmif1 = &emifObj1;
145 CSL_emifDdrConfig ddr3Config1;
146 CSL_ckgen_cm_core_aonRegs *hCkgenCmCoreAon =
147 (CSL_ckgen_cm_core_aonRegs *) CSL_MPU_CKGEN_CM_CORE_AON_REGS;
148 CSL_control_core_padRegs *hCtrlCorePad =
149 (CSL_control_core_padRegs *) CSL_MPU_CTRL_MODULE_CORE_CORE_PAD_REGISTERS_REGS;
150 CSL_control_core_wkupRegs *hCtrlCoreWkup =
151 (CSL_control_core_wkupRegs *) CSL_MPU_CTRL_MODULE_WKUP_CORE_REGISTERS_REGS;
152 CSL_DmmRegs *hDmmCfg =(CSL_DmmRegs *) CSL_MPU_DMM_CONF_REGS_REGS;
153 CSL_MampuLsmRegs *hMampuLsm = (CSL_MampuLsmRegs *) CSL_MPU_MA_MPU_LSM_REGS;
155 hEmif1->regs = (CSL_emifRegsOvly)CSL_MPU_EMIF1_CONF_REGS_REGS;
157 /* DLL override disable =0 ; enable = 1 */
158 hCkgenCmCoreAon->CM_DLL_CTRL_REG = 0x00000000;
160 /*
161 * CONTROL_DDR3CH1_0 -- channel_1 CMDs
162 * -- 40Ohm Ron (011)
163 * -- SR=slowest-3 (111) on CMDs
164 * -- CLK SR=slow (011)
165 * -- No pulls (00)
166 */
167 hCtrlCorePad->CONTROL_DDRCACH1_0 = 0x60606080U;
169 /*
170 * CTRL_CORE_CONTROL_DDRCH1_0
171 * - Impedance = 40ohm / SlewRate = fastest / No pulls
172 */
173 hCtrlCorePad->CONTROL_DDRCH1_0 = 0x40404040U;
175 /*
176 * CTRL_CORE_CONTROL_DDRCH1_1
177 * - Impedance = 40ohm / SlewRate = fastest / No pulls
178 */
179 hCtrlCorePad->CONTROL_DDRCH1_1 = 0x40404040U;
181 /*
182 * CTRL_CORE_CONTROL_DDRCH1_2
183 * - Impedance = 40ohm / SlewRate = fastest / No pulls
184 */
185 hCtrlCorePad->CONTROL_DDRCH1_2 = 0x00404000U;
187 /*
188 * CTRL_CORE_CONTROL_DDRIO_0
189 * - DDRCH1_VREF_DQ0/1_INT_EN = 0, reset values for other fields
190 */
191 hCtrlCorePad->CONTROL_DDRIO_0 = 0x00094A40U;
193 /*
194 * EMIF1_SDRAM_CONFIG_EXT
195 * -- cslice_en[2:0]=111 / Local_odt=01 / dyn_pwrdn=1 / dis_reset=0 / rd_lvl_samples=11 (128)
196 */
197 hCtrlCoreWkup->EMIF1_SDRAM_CONFIG_EXT = 0x0001C1A7U;
199 ddr3Config1.emifDdrParam.ddrPhyCtrl = hEmif1->regs->DDR_PHY_CONTROL_2;
201 ddr3Config1.emifDdrParam.sdramTim1 = 0xD113781C;
202 ddr3Config1.emifDdrParam.sdramTim2 = 0x30B37FE3;
203 ddr3Config1.emifDdrParam.sdramTim3 = 0x409F8AD8;
205 ddr3Config1.emifDdrParam.sdramCfg = 0x61862B32U;
206 ddr3Config1.emifDdrParam.sdramCfg2 = 0x08000000U;
207 ddr3Config1.emifDdrParam.sdramRefCtrl = 0x0000144AU;
208 ddr3Config1.emifDdrParam.zqConfig = 0x5007190BU;
209 ddr3Config1.emifDdrParam.sdramPwrMngtCtrl = 0x00000000U;
211 ioDftLogicCtrl = hEmif1->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL;
212 readWriteLvlRampWin = hEmif1->regs->READ_WRITE_LEVELING_RAMP_WINDOW;
214 ddr3Config1.emifDdrPhyParam.ctrlSlaveRatio = 0x80U;
215 ddr3Config1.emifDdrPhyParam.dqOffset = 0x40U;
216 ddr3Config1.emifDdrPhyParam.gateLevelInitMode = 0x01U;
217 ddr3Config1.emifDdrPhyParam.fifoWeInDelay = 0x0U;
218 ddr3Config1.emifDdrPhyParam.ctrlSlaveDelay = 0x0U;
219 ddr3Config1.emifDdrPhyParam.readDqsSlaveDelay = 0x20U;
220 ddr3Config1.emifDdrPhyParam.writeDqsSlaveDelay = 0x60U;
221 ddr3Config1.emifDdrPhyParam.writeDataSlaveDelay = 0x80U;
223 ddr3Config1.emifDdrPhyParam.gateLevelRatio = 0x00U;
224 ddr3Config1.emifDdrPhyParam.writeLevelInitRatio = 0x00;
225 ddr3Config1.emifDdrPhyParam.writeDqsSlaveRatio = 0x60U;
226 ddr3Config1.emifDdrPhyParam.fifoWeSlaveRatio = 0xBBU;
227 ddr3Config1.emifDdrPhyParam.useRank0Delays = 0U;
229 ddr3Config1.emifDdrPhyParam.gateLevelNumDq0 = 0xFU;
230 ddr3Config1.emifDdrPhyParam.writeLevelNumDq0 =
231 hEmif1->regs->EXT_PHY_CONTROL_36;
233 retVal = emifConfigureDdr3(hEmif1, &ddr3Config1, 1U);
235 if(BOARD_SOK == retVal)
236 {
237 /* MA_LISA_MAP_i */
238 hMampuLsm->MAP_0 = 0x80600100U;
239 hMampuLsm->MAP_1 = 0x00000000U;
240 hMampuLsm->MAP_2 = 0x00000000U;
241 hMampuLsm->MAP_3 = 0x00000000U;
243 /* DMM_LISA_MAP_i */
244 hDmmCfg->LISA_MAP[0U] = 0x80600100U;
245 hDmmCfg->LISA_MAP[1U] = 0x00000000U;
246 hDmmCfg->LISA_MAP[2U] = 0x00000000U;
247 hDmmCfg->LISA_MAP[3U] = 0x00000000U;
248 }
249 else
250 {
251 retVal = BOARD_INIT_DDR_FAIL;
252 }
254 return retVal;
255 }
257 int emifConfigureDdr3
258 (
259 CSL_emifHandle hEmif,
260 CSL_emifDdrConfig *ddr3Config,
261 Uint32 enableHwLeveling
262 )
263 {
264 int retVal = 0;
265 Uint32 regVal = 0U;
266 Uint32 emifPhyLevelDisable = 0U;
267 Uint32 sdRamRefCtrlInit = 0x0000514CU;
269 /* Fields in DDR_PHY_CTRL_1 */
270 /* Bit[21] - calculated using DataMacro/MDLL clock ratio
271 * Set to 1 for 532M, so that PHY DLL runs at 266.
272 * Set to 0 for 400M, so that PHY DLL runs at 400M.
273 * Ensure PHY DLL lower limit of 266M is not violated.
274 */
275 uint32_t emifPhyHalfDelayMode = 1U;
276 uint32_t emifPhyDisCalibRst = 0U; /* Bit[19] */
277 uint32_t emifPhyInvertClkout = 1U; /* Bit[18] */
278 uint32_t emifPhyDllLockDiff = 0x10U; /* Bit[17:10] */
279 uint32_t emifPhyFastDllLock = 0U; /* Bit[9] */
280 uint32_t emifPhyReadLatency = 0xDU; /* Bit[4:0], Typically >= (CL + 4) */
282 if (0U != (HW_RD_REG32(MPU_DEVICE_PRM_REGS + PRM_RSTST_REG) &
283 (PRM_RSTST_GLOBAL_WARM_SW_RST_MASK | PRM_RSTST_EXTERNAL_WARM_RST_MASK)))
284 {
285 /* Phy reset is required if you are coming back from a warm reset */
286 regVal = hEmif->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL;
287 regVal |= 0x400U;
288 hEmif->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL = regVal;
289 }
291 if(1U == emifPhyInvertClkout)
292 {
293 regVal = EXT_PHY_CTRL_VALUE((ddr3Config->emifDdrPhyParam.ctrlSlaveRatio + 0x80U));
294 hEmif->regs->EXT_PHY_CONTROL_1 = regVal;
295 hEmif->regs->EXT_PHY_CONTROL_1_SHADOW = regVal;
296 }
298 /* PHY settings for DQ offset, DLL override delay, levelling etc. */
299 regVal = EXT_PHY_FIFO_WE_SLAVE_CTRL_DELAY(ddr3Config->emifDdrPhyParam.fifoWeInDelay,
300 ddr3Config->emifDdrPhyParam.ctrlSlaveDelay);
301 hEmif->regs->EXT_PHY_CONTROL_22 = regVal;
302 hEmif->regs->EXT_PHY_CONTROL_22_SHADOW = regVal;
303 regVal = EXT_PHY_WR_RD_DQS_SLAVE_DELAY(ddr3Config->emifDdrPhyParam.writeDqsSlaveDelay,
304 ddr3Config->emifDdrPhyParam.readDqsSlaveDelay);
305 hEmif->regs->EXT_PHY_CONTROL_23 = regVal;
306 hEmif->regs->EXT_PHY_CONTROL_23_SHADOW = regVal;
307 regVal = EXT_PHY_RANK0_DELAY_VALUE(ddr3Config->emifDdrPhyParam.dqOffset,
308 ddr3Config->emifDdrPhyParam.gateLevelInitMode,
309 ddr3Config->emifDdrPhyParam.useRank0Delays,
310 ddr3Config->emifDdrPhyParam.writeDataSlaveDelay);
311 hEmif->regs->EXT_PHY_CONTROL_24 = regVal;
312 hEmif->regs->EXT_PHY_CONTROL_24_SHADOW = regVal;
313 regVal = EXT_PHY_DQ_VALUE(ddr3Config->emifDdrPhyParam.dqOffset);
314 hEmif->regs->EXT_PHY_CONTROL_25 = regVal;
315 hEmif->regs->EXT_PHY_CONTROL_25_SHADOW = regVal;
317 /* Use Init values if HW leveling is enabled */
318 /* Gate level Init ratios */
319 regVal = EXT_PHY_GATE_LVL_INIT_VALUE(ddr3Config->emifDdrPhyParam.gateLevelRatio);
320 hEmif->regs->EXT_PHY_CONTROL_26 = regVal;
321 hEmif->regs->EXT_PHY_CONTROL_26_SHADOW = regVal;
322 hEmif->regs->EXT_PHY_CONTROL_27 = regVal;
323 hEmif->regs->EXT_PHY_CONTROL_27_SHADOW = regVal;
324 hEmif->regs->EXT_PHY_CONTROL_28 = regVal;
325 hEmif->regs->EXT_PHY_CONTROL_28_SHADOW = regVal;
326 hEmif->regs->EXT_PHY_CONTROL_29 = regVal;
327 hEmif->regs->EXT_PHY_CONTROL_29_SHADOW = regVal;
328 hEmif->regs->EXT_PHY_CONTROL_30 = regVal;
329 hEmif->regs->EXT_PHY_CONTROL_30_SHADOW = regVal;
331 /* WR DQS Init ratios */
332 regVal = EXT_PHY_WR_LVL_INIT_VALUE(ddr3Config->emifDdrPhyParam.writeLevelInitRatio);
333 hEmif->regs->EXT_PHY_CONTROL_31 = regVal;
334 hEmif->regs->EXT_PHY_CONTROL_31_SHADOW = regVal;
335 hEmif->regs->EXT_PHY_CONTROL_32 = regVal;
336 hEmif->regs->EXT_PHY_CONTROL_32_SHADOW = regVal;
337 hEmif->regs->EXT_PHY_CONTROL_33 = regVal;
338 hEmif->regs->EXT_PHY_CONTROL_33_SHADOW = regVal;
339 hEmif->regs->EXT_PHY_CONTROL_34 = regVal;
340 hEmif->regs->EXT_PHY_CONTROL_34_SHADOW = regVal;
341 hEmif->regs->EXT_PHY_CONTROL_35 = regVal;
342 hEmif->regs->EXT_PHY_CONTROL_35_SHADOW = regVal;
344 regVal = ddr3Config->emifDdrPhyParam.writeLevelNumDq0;
345 hEmif->regs->EXT_PHY_CONTROL_36 = regVal;
346 hEmif->regs->EXT_PHY_CONTROL_36_SHADOW = regVal;
348 regVal = hEmif->regs->SDRAM_REFRESH_CONTROL_SHADOW;
349 regVal = (CSL_EMIF4D5_SDRAM_REFRESH_CONTROL_INITREF_DIS_MASK |
350 sdRamRefCtrlInit);
351 regVal = hEmif->regs->SDRAM_REFRESH_CONTROL;
352 regVal = (CSL_EMIF4D5_SDRAM_REFRESH_CONTROL_INITREF_DIS_MASK |
353 sdRamRefCtrlInit);
354 hEmif->regs->SDRAM_REFRESH_CONTROL = regVal;
356 /* Set up the EMIF registers */
357 hEmif->regs->SDRAM_TIMING_1 = ddr3Config->emifDdrParam.sdramTim1;
358 hEmif->regs->SDRAM_TIMING_1_SHADOW = ddr3Config->emifDdrParam.sdramTim1;
359 hEmif->regs->SDRAM_TIMING_2 = ddr3Config->emifDdrParam.sdramTim2;
360 hEmif->regs->SDRAM_TIMING_2_SHADOW = ddr3Config->emifDdrParam.sdramTim2;
361 hEmif->regs->SDRAM_TIMING_3 = ddr3Config->emifDdrParam.sdramTim3;
362 hEmif->regs->SDRAM_TIMING_3_SHADOW = ddr3Config->emifDdrParam.sdramTim3;
364 hEmif->regs->POWER_MANAGEMENT_CONTROL = ddr3Config->emifDdrParam.sdramPwrMngtCtrl;
365 hEmif->regs->POWER_MANAGEMENT_CONTROL_SHADOW = ddr3Config->emifDdrParam.sdramPwrMngtCtrl;
367 hEmif->regs->OCP_CONFIG = 0x0A500000U;
369 hEmif->regs->IODFT_TEST_LOGIC_GLOBAL_CONTROL = ioDftLogicCtrl;
370 hEmif->regs->SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG = ddr3Config->emifDdrParam.zqConfig;
371 hEmif->regs->DLL_CALIB_CTRL = 0x00050000U;
372 hEmif->regs->DLL_CALIB_CTRL_SHADOW = 0x00050000U;
374 hEmif->regs->READ_WRITE_LEVELING_RAMP_WINDOW = readWriteLvlRampWin;
375 hEmif->regs->READ_WRITE_LEVELING_RAMP_CONTROL = 0x80000000;
377 hEmif->regs->READ_WRITE_LEVELING_CONTROL = 0U;
379 regVal = DDR_PHY_CTRL1_VALUE(emifPhyReadLatency, emifPhyFastDllLock,
380 emifPhyDllLockDiff, emifPhyInvertClkout, emifPhyDisCalibRst,
381 emifPhyHalfDelayMode, emifPhyLevelDisable);
383 hEmif->regs->DDR_PHY_CONTROL_1 = regVal;
384 hEmif->regs->DDR_PHY_CONTROL_1_SHADOW = regVal;
386 /* Backup of the previous value. */
387 hEmif->regs->DDR_PHY_CONTROL_2 = ddr3Config->emifDdrParam.ddrPhyCtrl;
389 hEmif->regs->PRIORITY_TO_CLASS_OF_SERVICE_MAPPING = 0U;
390 hEmif->regs->CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING = 0U;
391 hEmif->regs->CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING = 0U;
392 hEmif->regs->READ_WRITE_EXECUTION_THRESHOLD = 0x00000305U;
393 hEmif->regs->COS_CONFIG = 0x00FFFFFFU;
395 /* SDRAM_REF_CTRL_INIT:
396 * For DDR3: value used initially to get 500us delay between
397 * RESET de-assertion to CKE assertion after power-up
398 */
399 hEmif->regs->SDRAM_REFRESH_CONTROL_SHADOW = 0x0000514CU;
400 hEmif->regs->SDRAM_REFRESH_CONTROL = 0x0000514CU;
401 hEmif->regs->SDRAM_CONFIG_2 = ddr3Config->emifDdrParam.sdramCfg2;
402 hEmif->regs->SDRAM_CONFIG = ddr3Config->emifDdrParam.sdramCfg;
404 ddr_delay(100000);
406 /* Now update with the correct refresh time */
407 hEmif->regs->SDRAM_REFRESH_CONTROL_SHADOW = ddr3Config->emifDdrParam.sdramRefCtrl;
408 hEmif->regs->SDRAM_REFRESH_CONTROL = ddr3Config->emifDdrParam.sdramRefCtrl;
410 /* If ECC is enabled. */
411 hEmif->regs->ECC_ADDRESS_RANGE_1 = 0U;
412 hEmif->regs->ECC_ADDRESS_RANGE_2 = 0U;
413 hEmif->regs->ECC_CTRL_REG = (CSL_EMIF4D5_ECC_CTRL_REG_REG_ECC_EN_MASK |
414 CSL_EMIF4D5_ECC_CTRL_REG_REG_ECC_ADDR_RGN_PROT_MASK);
416 /* Launch Full HW levelling. */
417 regVal = hEmif->regs->EXT_PHY_CONTROL_36;
418 regVal = (regVal | 0x00000100U);
419 hEmif->regs->EXT_PHY_CONTROL_36 = regVal;
420 regVal = hEmif->regs->EXT_PHY_CONTROL_36_SHADOW;
421 regVal = (regVal | 0x00000100U);
422 hEmif->regs->EXT_PHY_CONTROL_36_SHADOW = regVal;
424 /* Disable SDRAM refreshes before levelling */
425 regVal = hEmif->regs->SDRAM_REFRESH_CONTROL;
426 regVal = regVal | CSL_EMIF4D5_SDRAM_REFRESH_CONTROL_INITREF_DIS_MASK;
427 hEmif->regs->SDRAM_REFRESH_CONTROL = regVal;
429 /* RDWR_LVL_CTRL */
430 hEmif->regs->READ_WRITE_LEVELING_CONTROL =
431 CSL_EMIF4D5_READ_WRITE_LEVELING_CONTROL_RDWRLVLFULL_START_MASK;
433 /* Some clock cycle delay for refresh to complete. */
434 ddr_delay(30000U);
436 /* Wait for the levelling procedure to complete */
437 while((hEmif->regs->READ_WRITE_LEVELING_CONTROL & 0x80000000) != 0x0U);
439 /* Enable SDRAM refreshes after levelling */
440 regVal = hEmif->regs->SDRAM_REFRESH_CONTROL;
441 regVal = (regVal & ~CSL_EMIF4D5_SDRAM_REFRESH_CONTROL_INITREF_DIS_MASK);
442 hEmif->regs->SDRAM_REFRESH_CONTROL = regVal;
444 if((hEmif->regs->STATUS & 0x70) != 0U)
445 {
446 /* Indicates Hardware levelling timeout. */
447 retVal = -1;
448 }
449 else
450 {
451 emif_ddr3_updateHwLevelOutput(hEmif);
453 hEmif->regs->ECC_CTRL_REG = 0U;
454 }
456 return retVal;
457 }
459 static void emif_ddr3_updateHwLevelOutput(CSL_emifHandle hEmif)
460 {
461 /* Following function is needed for whenever CORE can go in and out of
462 * INACTIVE/CSWR.
463 */
464 Uint32 regVal = 0U;
466 /*
467 ** Updating slave ratios in PHY_STATUSx registers as per HW levelling output
468 */
469 /* if DISABLE_READ_GATE_LEVELING is set to 0 */
470 hEmif->regs->EXT_PHY_CONTROL_2 = hEmif->regs->PHY_STATUS_12;
471 hEmif->regs->EXT_PHY_CONTROL_2_SHADOW = hEmif->regs->PHY_STATUS_12;
472 hEmif->regs->EXT_PHY_CONTROL_3 = hEmif->regs->PHY_STATUS_13;
473 hEmif->regs->EXT_PHY_CONTROL_3_SHADOW = hEmif->regs->PHY_STATUS_13;
474 hEmif->regs->EXT_PHY_CONTROL_4 = hEmif->regs->PHY_STATUS_14;
475 hEmif->regs->EXT_PHY_CONTROL_4_SHADOW = hEmif->regs->PHY_STATUS_14;
476 hEmif->regs->EXT_PHY_CONTROL_5 = hEmif->regs->PHY_STATUS_15;
477 hEmif->regs->EXT_PHY_CONTROL_5_SHADOW = hEmif->regs->PHY_STATUS_15;
478 hEmif->regs->EXT_PHY_CONTROL_6 = hEmif->regs->PHY_STATUS_16;
479 hEmif->regs->EXT_PHY_CONTROL_6_SHADOW = hEmif->regs->PHY_STATUS_16;
481 /* if DISABLE_READ_LEVELING is set to 0 */
482 hEmif->regs->EXT_PHY_CONTROL_7 = hEmif->regs->PHY_STATUS_7;
483 hEmif->regs->EXT_PHY_CONTROL_7_SHADOW = hEmif->regs->PHY_STATUS_7;
484 hEmif->regs->EXT_PHY_CONTROL_8 = hEmif->regs->PHY_STATUS_8;
485 hEmif->regs->EXT_PHY_CONTROL_8_SHADOW = hEmif->regs->PHY_STATUS_8;
486 hEmif->regs->EXT_PHY_CONTROL_9 = hEmif->regs->PHY_STATUS_9;
487 hEmif->regs->EXT_PHY_CONTROL_9_SHADOW = hEmif->regs->PHY_STATUS_9;
488 hEmif->regs->EXT_PHY_CONTROL_10 = hEmif->regs->PHY_STATUS_10;
489 hEmif->regs->EXT_PHY_CONTROL_10_SHADOW = hEmif->regs->PHY_STATUS_10;
490 hEmif->regs->EXT_PHY_CONTROL_11 = hEmif->regs->PHY_STATUS_11;
491 hEmif->regs->EXT_PHY_CONTROL_11_SHADOW = hEmif->regs->PHY_STATUS_11;
493 /* if DISABLE_WRITE_LEVELING is set to 0 */
494 hEmif->regs->EXT_PHY_CONTROL_12 = hEmif->regs->PHY_STATUS_17;
495 hEmif->regs->EXT_PHY_CONTROL_12_SHADOW = hEmif->regs->PHY_STATUS_17;
496 hEmif->regs->EXT_PHY_CONTROL_13 = hEmif->regs->PHY_STATUS_18;
497 hEmif->regs->EXT_PHY_CONTROL_13_SHADOW = hEmif->regs->PHY_STATUS_18;
498 hEmif->regs->EXT_PHY_CONTROL_14 = hEmif->regs->PHY_STATUS_19;
499 hEmif->regs->EXT_PHY_CONTROL_14_SHADOW = hEmif->regs->PHY_STATUS_19;
500 hEmif->regs->EXT_PHY_CONTROL_15 = hEmif->regs->PHY_STATUS_20;
501 hEmif->regs->EXT_PHY_CONTROL_15_SHADOW = hEmif->regs->PHY_STATUS_20;
502 hEmif->regs->EXT_PHY_CONTROL_16 = hEmif->regs->PHY_STATUS_21;
503 hEmif->regs->EXT_PHY_CONTROL_16_SHADOW = hEmif->regs->PHY_STATUS_21;
505 /* EMIF_PHY_WR_DQS_SLAVE_RATIO */
506 hEmif->regs->EXT_PHY_CONTROL_17 = hEmif->regs->PHY_STATUS_22;
507 hEmif->regs->EXT_PHY_CONTROL_17_SHADOW = hEmif->regs->PHY_STATUS_22;
508 hEmif->regs->EXT_PHY_CONTROL_18 = hEmif->regs->PHY_STATUS_23;
509 hEmif->regs->EXT_PHY_CONTROL_18_SHADOW = hEmif->regs->PHY_STATUS_23;
510 hEmif->regs->EXT_PHY_CONTROL_19 = hEmif->regs->PHY_STATUS_24;
511 hEmif->regs->EXT_PHY_CONTROL_19_SHADOW = hEmif->regs->PHY_STATUS_24;
512 hEmif->regs->EXT_PHY_CONTROL_20 = hEmif->regs->PHY_STATUS_25;
513 hEmif->regs->EXT_PHY_CONTROL_20_SHADOW = hEmif->regs->PHY_STATUS_25;
514 hEmif->regs->EXT_PHY_CONTROL_21 = hEmif->regs->PHY_STATUS_26;
515 hEmif->regs->EXT_PHY_CONTROL_21_SHADOW = hEmif->regs->PHY_STATUS_26;
517 regVal = hEmif->regs->DDR_PHY_CONTROL_1;
518 regVal = (regVal | 0x0E000000U);
519 hEmif->regs->DDR_PHY_CONTROL_1 = regVal;
521 regVal = hEmif->regs->DDR_PHY_CONTROL_1_SHADOW;
522 regVal = (regVal | 0x0E000000U);
523 hEmif->regs->DDR_PHY_CONTROL_1_SHADOW = regVal;
525 hEmif->regs->READ_WRITE_LEVELING_RAMP_CONTROL = 0U;
526 }