[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_2_eng / packages / ti / board / src / idkAM572x / boardPadDelayTune.h
1 /**
2 * Note: This file was auto-generated by TI PinMux on 3/1/2016 at 8:15:27 PM.
3 *
4 * \file boardPadDelayTune.h
5 *
6 * \brief This file contain manual/vritual iodelay mode definitions
7 *
8 * \copyright Copyright (CU) 2015 Texas Instruments Incorporated -
9 * http://www.ti.com/
10 */
12 /**
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 *
20 * Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the
23 * distribution.
24 *
25 * Neither the name of Texas Instruments Incorporated nor the names of
26 * its contributors may be used to endorse or promote products derived
27 * from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 */
46 /*#define VIP2_REC1 */ /* VIN3A/3B IOSET1 Rise-Edge Capture Mode */
47 /*#define VIP2_FEC2 */ /* VIN3A/3B IOSET1, VIN4A IOSET1/2 Fall-Edge Capture Mode */
48 /*#define VIP2_REC4 */ /* VIN4B Rise-Edge Capture Mode */
49 #define VIP2_FEC5 /* VIN4B Fall-Edge Capture Mode */
50 #define GMAC_RGMII0_MANUAL1 /* GMAC RGMII0 with Transmit Clock Internal Delay Enabled Timings */
51 #define QSPI_MODE0_DEFAULT /* QSPI Mode 0 Default Timing Mode */
52 /*#define QSPI_MODE3_ALT1 */ /* QSPI Mode 3 Alternate Timing Mode 1 */
53 /*#define QSPI_MODE3_ALT2 */ /* QSPI Mode 3 Alternate Timing Mode 2 */
54 /*#define DSS_ALT4 */ /* DPI1 Video Output Alternate */
55 /*#define DSS_FEC */ /* DPI1/2/3 Video Output Default - Falling-edge Clock Reference */
56 #define GPMC_ASYNC /* GPMC Asynchronous Mode (1/5 Load) Timings and Synchronous Mode (1 Load) */
57 /*#define GPMC_SYNC_5 */ /* GPMC Synchronous Mode (5 Load) */
58 #define MMC1_DS_PLB_SDR12_PLB_DEFAULT /* MMC1 DS (Pad Loopback) and SDR12 (Pad Loopback) Default Timings */
59 /*#define MMC1_DDR50_PLB */ /* MMC1 DDR50 (Pad Loopback) Timings */
60 /*#define MMC1_SDR_104 */ /* MMC1 SDR104 Timings */
61 /*#define MMC1_HS_SDR12_ILB_SDR25 */ /* MMC1 HS (Internal Loopback and Pad Loopback), SDR12 (Internal Loopback), SDR25 Timings (Internal Loopback and Pad Loopback) */
62 /*#define MMC1_SDR50_PLB */ /* MMC1 SDR50 (Pad Loopback) Timings */
63 /*#define MMC1_DS_ILB */ /* MMC1 DS (Internal Loopback) Timings */
64 /*#define MMC1_SDR50_ILB */ /* MMC1 SDR50 (Internal Loopback) Timings */
65 /*#define MMC1_DDR50_ILB */ /* MMC1 DDR50 (Internal Loopback) Timings */
66 #define PR2_PRU1_DIR_OUT2 /* PRU-ICSS2 PRU1 IOSET2 Direct Output Mode Timings */
67 /*#define PRU_ICSS2_OUT */ /* PRU-ICSS2 Direct Output Mode Timings */
68 #define PR2_PRU1_DIR_IN2 /* PRU-ICSS2 PRU1 IOSET2 Direct Input Mode Timings */
69 /*#define PR2_PRU1_PAR_CAP2 */ /* PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode Timings */
70 /*#define PRU_ICSS2_IN */ /* PRU-ICSS2 Direct Input Mode Timings */
71 #define GMAC_RGMII1_MANUAL1 /* GMAC RGMII1 with Transmit Clock Internal Delay Enabled Timings */
72 /*#define PR1_PRU1_DIR_OUT */ /* PRU-ICSS1 PRU1 Direct Output Mode Timings */
73 /*#define PRU_ICSS1_OUT */ /* PRU-ICSS1 Direct Output Mode Timings */
74 /*#define GMAC_RMII0 */ /* GMAC RMII0 Timings */
75 /*#define GMAC_RMII1 */ /* GMAC RMII1 Timings */
76 #define MMC2_STD_PLB_HS_PLB /* MMC2 Standard (Pad Loopback) and High Speed (Pad Loopback) Timings */
77 /*#define MMC2_DDR_PLB */ /* MMC2 DDR (Pad Loopback) 1.8V and 3.3V Mode Timings */
78 /*#define MMC2_DDR_ILB */ /* MMC2 DDR (Internal Loopback) Timings */
79 /*#define MMC2_STD_ILB_HS_ILB */ /* MMC2 Standard (Internal Loopback), High Speed (Internal Loopback) Timings */
80 /*#define MMC2_HS200 */ /* MMC2 HS200 Timings */
82 /* MODE RE-DEFINITIONS */
84 #ifdef VIP2_REC1
85 #define VIP2_MANUAL1
86 #endif
87 #ifdef VIP2_FEC2
88 #define VIP2_MANUAL2
89 #endif
90 #ifdef VIP2_REC4
91 #define VIP2_4B_MANUAL1
92 #endif
93 #ifdef VIP2_FEC5
94 #define VIP2_4B_MANUAL2
95 #endif
96 #ifdef GMAC_RGMII0_MANUAL1
97 #define GMAC_RGMII0_MANUAL1
98 #endif
99 #ifdef QSPI_MODE0_DEFAULT
100 #define QSPI_MODE0_MANUAL1
101 #endif
102 #ifdef QSPI_MODE3_ALT1
103 #define QSPI1_VIRTUAL1
104 #endif
105 #ifdef QSPI_MODE3_ALT2
106 #define QSPI1_VIRTUAL2
107 #endif
108 #ifdef DSS_ALT4
109 #define VOUT1_MANUAL1
110 #endif
111 #ifdef DSS_FEC
112 #define DSS_VIRTUAL1
113 #endif
114 #ifdef GPMC_ASYNC
115 #define GPMC_DEFAULT
116 #endif
117 #ifdef GPMC_SYNC_5
118 #define GPMC_VIRTUAL1
119 #endif
120 #ifdef MMC1_DS_PLB_SDR12_PLB_DEFAULT
121 #define MMC1_DEFAULT
122 #endif
123 #ifdef MMC1_DDR50_PLB
124 #define MMC1_DDR_MANUAL1
125 #endif
126 #ifdef MMC1_SDR_104
127 #define MMC1_SDR104_MANUAL1
128 #endif
129 #ifdef MMC1_HS_SDR12_ILB_SDR25
130 #define MMC1_VIRTUAL1
131 #endif
132 #ifdef MMC1_SDR50_PLB
133 #define MMC1_VIRTUAL2
134 #endif
135 #ifdef MMC1_DS_ILB
136 #define MMC1_VIRTUAL5
137 #endif
138 #ifdef MMC1_SDR50_ILB
139 #define MMC1_VIRTUAL6
140 #endif
141 #ifdef MMC1_DDR50_ILB
142 #define MMC1_VIRTUAL7
143 #endif
144 #ifdef PR2_PRU1_DIR_OUT2
145 #define PR2_PRU1_DIR_OUT_MANUAL2
146 #endif
147 #ifdef PRU_ICSS2_OUT
148 #define PRU_ICSS2_OUT_VIRTUAL1
149 #endif
150 #ifdef PR2_PRU1_DIR_IN2
151 #define PR2_PRU1_DIR_IN_MANUAL2
152 #endif
153 #ifdef PR2_PRU1_PAR_CAP2
154 #define PR2_PRU1_PAR_CAP_MANUAL2
155 #endif
156 #ifdef PRU_ICSS2_IN
157 #define PRU_ICSS2_IN_VIRTUAL1
158 #endif
159 #ifdef GMAC_RGMII1_MANUAL1
160 #define GMAC_RGMII1_MANUAL1
161 #endif
162 #ifdef PR1_PRU1_DIR_OUT
163 #define PR1_PRU1_DIR_OUT_MANUAL
164 #endif
165 #ifdef PRU_ICSS1_OUT
166 #define PRU_ICSS1_OUT_VIRTUAL1
167 #endif
168 #ifdef GMAC_RMII0
169 #define GMAC_RMII0_MANUAL1
170 #endif
171 #ifdef GMAC_RMII1
172 #define GMAC_RMII1_MANUAL1
173 #endif
174 #ifdef MMC2_STD_PLB_HS_PLB
175 #define MMC2_DEFAULT
176 #endif
177 #ifdef MMC2_DDR_PLB
178 #define MMC2_DDR_MANUAL1
179 #endif
180 #ifdef MMC2_DDR_ILB
181 #define MMC2_DDR_LB_MANUAL1
182 #endif
183 #ifdef MMC2_STD_ILB_HS_ILB
184 #define MMC2_STD_HS_LB_MANUAL1
185 #endif
186 #ifdef MMC2_HS200
187 #define MMC2_HS200_MANUAL1
188 #endif