[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_2_eng / packages / ti / board / src / idkAM572x / idkAM572x.c
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2 * Copyright (c) 2010-2015 Texas Instruments Incorporated - http://www.ti.com
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32 *****************************************************************************/
34 #include "board_internal.h"
36 Board_gblObj Board_obj;
38 Board_STATUS Board_unlockMMR(void)
39 {
40 CSL_control_coreRegs *ctrlCoreReg =
41 (CSL_control_coreRegs *) CSL_MPU_CTRL_MODULE_CORE_CORE_REGISTERS_REGS;
43 /* unlock MMR1 space for region 0x0100 to 0x079F */
44 ctrlCoreReg->MMR_LOCK_1 = 804367403U;
45 /* unlock MMR2 space for region 0x07A0 to 0x0D9F */
46 ctrlCoreReg->MMR_LOCK_2 = 4149738944U;
47 /* unlock MMR3 space for region 0x0DA0 to 0x0FFF */
48 ctrlCoreReg->MMR_LOCK_3 = 3803986541U;
49 /* unlock MMR4 space for region 0x1000 to 0x13FF */
50 ctrlCoreReg->MMR_LOCK_4 = 515838749U;
51 /* unlock MMR5 space for region 0x1400 to 0x1FFF */
52 ctrlCoreReg->MMR_LOCK_5 = 1865817605U;
54 return BOARD_SOK;
55 }
57 Board_STATUS Board_watchdogDisable()
58 {
59 CSL_watchdogocp2Regs *watchdogRegs = (CSL_watchdogocp2Regs *) CSL_MPU_WD_TIMER2_REGS;
61 /* Wait until reset complete */
62 while(CSL_WATCHDOGOCP2_WDST_RESETVAL !=
63 CSL_FEXT(watchdogRegs->WDST, WATCHDOGOCP2_WDST_RESETDONE));
65 /* Disable watchdog timer */
66 CSL_FINS(watchdogRegs->WSPR, WATCHDOGOCP2_WSPR_WSPR_VALUE, 0xAAAAU);
68 while(CSL_WATCHDOGOCP2_WWPS_W_PEND_WSPR_RESETVAL !=
69 CSL_FEXT(watchdogRegs->WWPS,WATCHDOGOCP2_WWPS_W_PEND_WSPR));
71 /* Disable 32Khz watchdog timer */
72 CSL_FINS(watchdogRegs->WSPR, WATCHDOGOCP2_WSPR_WSPR_VALUE, 0x5555U);
74 while(CSL_WATCHDOGOCP2_WWPS_W_PEND_WSPR_RESETVAL !=
75 CSL_FEXT(watchdogRegs->WWPS,WATCHDOGOCP2_WWPS_W_PEND_WSPR));
77 return BOARD_SOK;
78 }
80 Board_STATUS Board_init(Board_initCfg cfg)
81 {
82 Board_STATUS ret = BOARD_SOK;
84 if (cfg & BOARD_INIT_UNLOCK_MMR)
85 ret = Board_unlockMMR();
86 if (ret != BOARD_SOK)
87 return ret;
89 if (cfg & BOARD_INIT_PLL)
90 ret = Board_PLLInit(OPP_NOM);
91 else if(cfg & BOARD_INIT_PLL_OPP_HIGH)
92 ret = Board_PLLInit(OPP_HIGH);
93 else if(cfg & BOARD_INIT_PLL_OPP_OD)
94 ret = Board_PLLInit(OPP_OD);
95 else if(cfg & BOARD_INIT_PLL_OPP_NOM)
96 ret = Board_PLLInit(OPP_NOM);
97 if (ret != BOARD_SOK)
98 return ret;
100 if (cfg & BOARD_INIT_MODULE_CLOCK)
101 ret = Board_moduleClockInit();
102 if (ret != BOARD_SOK)
103 return ret;
105 if (cfg & BOARD_INIT_PINMUX_CONFIG)
106 ret = Board_pinmuxConfig();
107 if (ret != BOARD_SOK)
108 return ret;
110 if (cfg & BOARD_INIT_DDR)
111 ret = Board_DDR3Init();
112 if (ret != BOARD_SOK)
113 return ret;
115 if (cfg & BOARD_INIT_WATCHDOG_DISABLE)
116 ret = Board_watchdogDisable();
117 if (ret != BOARD_SOK)
118 return ret;
120 if (cfg & BOARD_INIT_UART_STDIO)
121 ret = Board_uartStdioInit();
122 if (ret != BOARD_SOK)
123 return ret;
125 return ret;
126 }