[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_2_eng / packages / ti / boot / sbl / soc / am57xx / mailbox.h
1 /**
2 * \file mailbox.h
3 *
4 * \brief This file contains the function prototypes for Mail box access.
5 */
7 /*
8 * Copyright (c) 2015, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * * Neither the name of Texas Instruments Incorporated nor the names of
23 * its contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
33 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
34 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
35 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
36 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
39 #ifndef MAILBOX_H_
40 #define MAILBOX_H_
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
46 /* ======================================================================= */
47 /**
48 * @def User Id's Corresponds to the Core using the mailbox
49 * Mailbox Queue's Corresponds to the Mailbox Queue Number
50 */
51 /* ======================================================================= */
52 /********************** MACROS ***************************/
54 /* Mailbox Queue's */
55 #define MAILBOX_QUEUE_0 0U
56 #define MAILBOX_QUEUE_1 1U
57 #define MAILBOX_QUEUE_2 2U
58 #define MAILBOX_QUEUE_3 3U
59 #define MAILBOX_QUEUE_4 4U
60 #define MAILBOX_QUEUE_5 5U
61 #define MAILBOX_QUEUE_6 6U
62 #define MAILBOX_QUEUE_7 7U
63 #define MAILBOX_QUEUE_8 8U
64 #define MAILBOX_QUEUE_9 9U
65 #define MAILBOX_QUEUE_10 10U
66 #define MAILBOX_QUEUE_11 11U
67 #define MAILBOX_QUEUE_12 12U
68 #define MAILBOX_QUEUE_13 13U
70 #define MESSAGE_VALID 0U
71 #define MESSAGE_INVALID 1U
73 /****************************************************************************************************
74 * Register Definitions
75 ****************************************************************************************************/
76 #define MAILBOX_REVISION (0x0U)
77 #define MAILBOX_SYSCONFIG (0x10U)
78 #define MAILBOX_MESSAGE(n) ((uint32_t)0x40U + ((n) * 4U))
79 #define MAILBOX_FIFOSTATUS(n) ((uint32_t)0x80U + ((n) * 4U))
80 #define MAILBOX_MSGSTATUS(n) ((uint32_t)0xc0U + ((n) * 4U))
81 #define MAILBOX_IRQSTATUS_RAW(n) ((uint32_t)0x100U + ((n) * 16U))
82 #define MAILBOX_IRQSTATUS_CLR(n) ((uint32_t)0x104U + ((n) * 16U))
83 #define MAILBOX_IRQENABLE_CLR(n) ((uint32_t)0x10cU + ((n) * 16U))
84 #define MAILBOX_IRQENABLE_SET(n) ((uint32_t)0x108U + ((n) * 16U))
86 #define MAILBOX_FIFOSTATUS_FIFOFULLMBM_SHIFT (0U)
87 #define MAILBOX_FIFOSTATUS_FIFOFULLMBM_MASK (0x00000001U)
89 #define MAILBOX_FIFOSTATUS_RESERVED_0_SHIFT (1U)
90 #define MAILBOX_FIFOSTATUS_RESERVED_0_MASK (0xfffffffeU)
92 #define MAILBOX_MSGSTATUS_NBOFMSGMBM_SHIFT (0U)
93 #define MAILBOX_MSGSTATUS_NBOFMSGMBM_MASK (0x0000007fU)
95 #define MAILBOX_MSGSTATUS_RESERVED_SHIFT (7U)
96 #define MAILBOX_MSGSTATUS_RESERVED_MASK (0xffffff80U)
98 /*****************************************************************************
99 ** FUNCTION DECLARATIONS
100 *****************************************************************************/
102 /* Queue Access API's */
103 /**
104 * This function resets the mailbox
105 *
106 * @param baseAdd It is the Memory address of the Mailbox instance.
107 * MAILBOXn (n = 1 to 10) Ex MAILBOX1, MAILBOX2, etc
108 * EVEn_MLBm (n = 1 to 3, m = 1 to 4)
109 * @return None
110 */
111 void MailboxReset(uint32_t baseAdd);
113 /* ========================================================================= */
114 /**
115 * This function configures the idle mode of the mailbox
116 *
117 * @param baseAdd It is the Memory address of the Mailbox instance.
118 * @param idleMode Idle mode to be configured. Possible values are
119 * 0x0: Force-idle. An idle request is acknowledged
120 * unconditionally
121 * 0x1: No-idle. An idle request is never acknowledged
122 * 0x2: Smart-idle. Acknowledgement to an idle request is
123 * given based on the internal activity of the module
124 * @return None
125 */
126 void MailboxConfigIdleMode(uint32_t baseAdd, uint32_t idleMode);
128 /**
129 * This function gets the first message in the queue
130 *
131 * @param baseAdd It is the Memory address of the Mailbox instance.
132 * @param queueId Queue to be read
133 * @param *msgPtr Message pointer in which the message will be returned
134 *
135 * @return Validity The return value indicates whether the message is valid
136 */
137 uint32_t MailboxGetMessage(uint32_t baseAdd, uint32_t queueId, uint32_t *msgPtr);
139 /**
140 * This function writes message in the queue
141 *
142 * @param baseAdd It is the Memory address of the Mailbox instance.
143 * @param queueId Queue to be written
144 * @param msg Message which has to be sent
145 *
146 * @return status The return value indicates whether the message is
147 * written to the queue. Possible values are,
148 * 0 - Written successfully
149 * 0 - Queue full
150 */
151 uint32_t MailboxSendMessage(uint32_t baseAdd, uint32_t queueId, uint32_t msg);
153 /* Mailbox user(hw using mailbox) access API's */
154 /**
155 * This function enables the new message interrupt for a user for given queue
156 *
157 * @param baseAdd It is the Memory address of the Mailbox instance.
158 * @param userId User for whom the new meaasge should be intimated
159 * @param queueId Queue to be monitored for new message
160 *
161 * @return None
162 */
163 void MailboxEnableNewMsgInt(uint32_t baseAdd, uint32_t userId, uint32_t queueId);
165 /**
166 * This function enables the queue not full interrupt for a user for given
167 * queue
168 *
169 * @param baseAdd It is the Memory address of the Mailbox instance.
170 * @param userId User for whom the event should be intimated
171 * @param queueId Queue to be monitored for non-full condition
172 *
173 * @return None
174 */
175 void MailboxEnableQueueNotFullInt(uint32_t baseAdd, uint32_t userId,
176 uint32_t queueId);
178 /**
179 * This function disables the new message interrupt for a user for given queue
180 *
181 * @param baseAdd It is the Memory address of the Mailbox instance.
182 * @param userId User for whom the new meaasge event should be disabled
183 * @param queueId Queue to be monitored for new message
184 *
185 * @return None
186 */
187 void MailboxDisableNewMsgInt(uint32_t baseAdd, uint32_t userId,
188 uint32_t queueId);
190 /**
191 * This function disables the queue not full interrupt for a user for given
192 * queue
193 *
194 * @param baseAdd It is the Memory address of the Mailbox instance.
195 * @param userId User for whom the event should be disabled
196 * @param queueId Queue for which the non-full event to be disabled
197 *
198 * @return None
199 */
200 void MailboxDisableQueueNotFullInt(uint32_t baseAdd, uint32_t userId,
201 uint32_t queueId);
203 /**
204 * This function clears the queue not-full status
205 *
206 * @param baseAdd It is the Memory address of the Mailbox instance.
207 * @param userId User for whom the event should be cleared
208 * @param queueId Queue for which the event should be cleared
209 *
210 * @return None
211 */
212 void MailboxClrNewMsgStatus(uint32_t baseAdd, uint32_t userId, uint32_t queueId);
214 /**
215 * This function clears the queue not-full status
216 *
217 * @param baseAdd It is the Memory address of the Mailbox instance.
218 * @param userId User for whom the event should be cleared
219 * @param queueId Queue for which the event should be cleared
220 *
221 * @return None
222 */
223 void MailboxClrQueueNotFullStatus(uint32_t baseAdd, uint32_t userId,
224 uint32_t queueId);
226 /**
227 * This function gets the raw new message status
228 *
229 * @param baseAdd It is the Memory address of the Mailbox instance.
230 * @param userId User for whom the event should be checked
231 * @param queueId Queue for which the event should be checked
232 *
233 * @return status status of new message
234 */
235 uint32_t MailboxGetRawNewMsgStatus(uint32_t baseAdd, uint32_t userId,
236 uint32_t queueId);
238 /**
239 * This function gets the raw queue not-full status
240 *
241 * @param baseAdd It is the Memory address of the Mailbox instance.
242 * @param userId User for whom the event should be checked
243 * @param queueId Queue for which the event should be checked
244 *
245 * @return status Queue not full status
246 */
247 uint32_t MailboxGetRawQueueNotFullStatus(uint32_t baseAdd, uint32_t userId,
248 uint32_t queueId);
250 #ifdef __cplusplus
251 }
252 #endif
254 #endif