[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_2_eng / packages / ti / csl / arch / a15 / hw_mpu_intc_phys.h
1 /* =============================================================================
2 * Copyright (c) Texas Instruments Incorporated 2008-2013
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
34 /**
35 *
36 * \file hw_mpu_intc_phys.h
37 *
38 * \brief register-level header file for MPU
39 *
40 **/
42 #ifndef HW_MPU_INTC_PHYS_H_
43 #define HW_MPU_INTC_PHYS_H_
45 #ifdef __cplusplus
46 extern "C"
47 {
48 #endif
50 /****************************************************************************************************
51 * Register Definitions
52 ****************************************************************************************************/
53 #define MPU_GICC_ICR (0x0U)
54 #define MPU_GICC_PMR (0x4U)
55 #define MPU_GICC_BPR (0x8U)
56 #define MPU_GICC_IAR (0xcU)
57 #define MPU_GICC_EOIR (0x10U)
58 #define MPU_GICC_RPR (0x14U)
59 #define MPU_GICC_HPIR (0x18U)
60 #define MPU_GICC_ABPR (0x1cU)
61 #define MPU_GICC_AIAR (0x20U)
62 #define MPU_GICC_AEOIR (0x24U)
63 #define MPU_GICC_AHPPIR (0x28U)
64 #define MPU_GICC_APR0 (0xd0U)
65 #define MPU_GICC_NSAPR0 (0xe0U)
66 #define MPU_GICC_IIDR (0xfcU)
67 #define MPU_GICC_DIR (0x1000U)
69 /****************************************************************************************************
70 * Field Definition Macros
71 ****************************************************************************************************/
73 #define MPU_GICC_ICR_RESERVED_SHIFT (11U)
74 #define MPU_GICC_ICR_RESERVED_MASK (0xfffff800U)
76 #define MPU_GICC_ICR_ENABLES_SHIFT (0U)
77 #define MPU_GICC_ICR_ENABLES_MASK (0x00000001U)
79 #define MPU_GICC_ICR_ENABLENS_SHIFT (1U)
80 #define MPU_GICC_ICR_ENABLENS_MASK (0x00000002U)
82 #define MPU_GICC_ICR_ACKCTL_SHIFT (2U)
83 #define MPU_GICC_ICR_ACKCTL_MASK (0x00000004U)
85 #define MPU_GICC_ICR_FIQEN_SHIFT (3U)
86 #define MPU_GICC_ICR_FIQEN_MASK (0x00000008U)
88 #define MPU_GICC_ICR_SBPR_SHIFT (4U)
89 #define MPU_GICC_ICR_SBPR_MASK (0x00000010U)
91 #define MPU_GICC_ICR_FIQBYPDISABLE_SHIFT (5U)
92 #define MPU_GICC_ICR_FIQBYPDISABLE_MASK (0x00000020U)
94 #define MPU_GICC_ICR_IRQBYPDISABLE_SHIFT (6U)
95 #define MPU_GICC_ICR_IRQBYPDISABLE_MASK (0x00000040U)
97 #define MPU_GICC_ICR_FIQBYPDISNS_SHIFT (7U)
98 #define MPU_GICC_ICR_FIQBYPDISNS_MASK (0x00000080U)
100 #define MPU_GICC_ICR_IRQBYPDISNS_SHIFT (8U)
101 #define MPU_GICC_ICR_IRQBYPDISNS_MASK (0x00000100U)
103 #define MPU_GICC_ICR_EOIMODE_SHIFT (9U)
104 #define MPU_GICC_ICR_EOIMODE_MASK (0x00000200U)
106 #define MPU_GICC_ICR_EOIMODENS_SHIFT (10U)
107 #define MPU_GICC_ICR_EOIMODENS_MASK (0x00000400U)
109 #define MPU_GICC_PMR_PRIORITY_SHIFT (3U)
110 #define MPU_GICC_PMR_PRIORITY_MASK (uint32_t)(0x000000f8U)
112 #define MPU_GICC_PMR_RESERVED_SHIFT (8U)
113 #define MPU_GICC_PMR_RESERVED_MASK (0xffffff00U)
115 #define MPU_GICC_PMR_RESERVED1_SHIFT (0U)
116 #define MPU_GICC_PMR_RESERVED1_MASK (0x00000007U)
118 #define MPU_GICC_BPR_BINARYPOINT_SHIFT (0U)
119 #define MPU_GICC_BPR_BINARYPOINT_MASK (0x00000007U)
121 #define MPU_GICC_BPR_RESERVED_SHIFT (3U)
122 #define MPU_GICC_BPR_RESERVED_MASK (0xfffffff8U)
124 #define MPU_GICC_IAR_ACKINTID_SHIFT (0U)
125 #define MPU_GICC_IAR_ACKINTID_MASK (0x000003ffU)
127 #define MPU_GICC_IAR_RESERVED_SHIFT (13U)
128 #define MPU_GICC_IAR_RESERVED_MASK (0xffffe000U)
130 #define MPU_GICC_IAR_CPUID_SHIFT (10U)
131 #define MPU_GICC_IAR_CPUID_MASK (0x00001c00U)
133 #define MPU_GICC_EOIR_EOIINTID_SHIFT (0U)
134 #define MPU_GICC_EOIR_EOIINTID_MASK (0x000003ffU)
136 #define MPU_GICC_EOIR_CPUID_SHIFT (10U)
137 #define MPU_GICC_EOIR_CPUID_MASK (0x00001c00U)
139 #define MPU_GICC_EOIR_RESERVED_SHIFT (13U)
140 #define MPU_GICC_EOIR_RESERVED_MASK (0xffffe000U)
142 #define MPU_GICC_RPR_RESERVED_SHIFT (8U)
143 #define MPU_GICC_RPR_RESERVED_MASK (0xffffff00U)
145 #define MPU_GICC_RPR_PRIORITY_SHIFT (0U)
146 #define MPU_GICC_RPR_PRIORITY_MASK (0x000000ffU)
148 #define MPU_GICC_HPIR_RESERVED_SHIFT (13U)
149 #define MPU_GICC_HPIR_RESERVED_MASK (0xffffe000U)
151 #define MPU_GICC_HPIR_CPUID_SHIFT (10U)
152 #define MPU_GICC_HPIR_CPUID_MASK (uint32_t)(0x00001c00U)
154 #define MPU_GICC_HPIR_PENDINTID_SHIFT (0U)
155 #define MPU_GICC_HPIR_PENDINTID_MASK (uint32_t)(0x000003ffU)
157 #define MPU_GICC_ABPR_RESERVED_SHIFT (3U)
158 #define MPU_GICC_ABPR_RESERVED_MASK (0xfffffff8U)
160 #define MPU_GICC_ABPR_BINARYPOINT_SHIFT (0U)
161 #define MPU_GICC_ABPR_BINARYPOINT_MASK (0x00000007U)
163 #define MPU_GICC_AIAR_ACKINTID_SHIFT (0U)
164 #define MPU_GICC_AIAR_ACKINTID_MASK (0x000003ffU)
166 #define MPU_GICC_AIAR_RESERVED_SHIFT (13U)
167 #define MPU_GICC_AIAR_RESERVED_MASK (0xffffe000U)
169 #define MPU_GICC_AIAR_CPUID_SHIFT (10U)
170 #define MPU_GICC_AIAR_CPUID_MASK (0x00001c00U)
172 #define MPU_GICC_AEOIR_EOIINTID_SHIFT (0U)
173 #define MPU_GICC_AEOIR_EOIINTID_MASK (0x000003ffU)
175 #define MPU_GICC_AEOIR_CPUID_SHIFT (10U)
176 #define MPU_GICC_AEOIR_CPUID_MASK (0x00001c00U)
178 #define MPU_GICC_AEOIR_RESERVED_SHIFT (13U)
179 #define MPU_GICC_AEOIR_RESERVED_MASK (0xffffe000U)
181 #define MPU_GICC_AHPPIR_RESERVED_SHIFT (13U)
182 #define MPU_GICC_AHPPIR_RESERVED_MASK (0xffffe000U)
184 #define MPU_GICC_AHPPIR_CPUID_SHIFT (10U)
185 #define MPU_GICC_AHPPIR_CPUID_MASK (0x00001c00U)
187 #define MPU_GICC_AHPPIR_PENDINTID_SHIFT (0U)
188 #define MPU_GICC_AHPPIR_PENDINTID_MASK (0x000003ffU)
190 #define MPU_GICC_APR0_AP0_SHIFT (0U)
191 #define MPU_GICC_APR0_AP0_MASK (0x00000001U)
193 #define MPU_GICC_APR0_AP1_SHIFT (1U)
194 #define MPU_GICC_APR0_AP1_MASK (0x00000002U)
196 #define MPU_GICC_APR0_AP2_SHIFT (2U)
197 #define MPU_GICC_APR0_AP2_MASK (0x00000004U)
199 #define MPU_GICC_APR0_AP3_SHIFT (3U)
200 #define MPU_GICC_APR0_AP3_MASK (0x00000008U)
202 #define MPU_GICC_APR0_AP4_SHIFT (4U)
203 #define MPU_GICC_APR0_AP4_MASK (0x00000010U)
205 #define MPU_GICC_APR0_AP5_SHIFT (5U)
206 #define MPU_GICC_APR0_AP5_MASK (0x00000020U)
208 #define MPU_GICC_APR0_AP6_SHIFT (6U)
209 #define MPU_GICC_APR0_AP6_MASK (0x00000040U)
211 #define MPU_GICC_APR0_AP7_SHIFT (7U)
212 #define MPU_GICC_APR0_AP7_MASK (0x00000080U)
214 #define MPU_GICC_APR0_AP8_SHIFT (8U)
215 #define MPU_GICC_APR0_AP8_MASK (0x00000100U)
217 #define MPU_GICC_APR0_AP9_SHIFT (9U)
218 #define MPU_GICC_APR0_AP9_MASK (0x00000200U)
220 #define MPU_GICC_APR0_AP10_SHIFT (10U)
221 #define MPU_GICC_APR0_AP10_MASK (0x00000400U)
223 #define MPU_GICC_APR0_AP11_SHIFT (11U)
224 #define MPU_GICC_APR0_AP11_MASK (0x00000800U)
226 #define MPU_GICC_APR0_AP12_SHIFT (12U)
227 #define MPU_GICC_APR0_AP12_MASK (0x00001000U)
229 #define MPU_GICC_APR0_AP13_SHIFT (13U)
230 #define MPU_GICC_APR0_AP13_MASK (0x00002000U)
232 #define MPU_GICC_APR0_AP14_SHIFT (14U)
233 #define MPU_GICC_APR0_AP14_MASK (0x00004000U)
235 #define MPU_GICC_APR0_AP15_SHIFT (15U)
236 #define MPU_GICC_APR0_AP15_MASK (0x00008000U)
238 #define MPU_GICC_APR0_AP16_SHIFT (16U)
239 #define MPU_GICC_APR0_AP16_MASK (0x00010000U)
241 #define MPU_GICC_APR0_AP17_SHIFT (17U)
242 #define MPU_GICC_APR0_AP17_MASK (0x00020000U)
244 #define MPU_GICC_APR0_AP18_SHIFT (18U)
245 #define MPU_GICC_APR0_AP18_MASK (0x00040000U)
247 #define MPU_GICC_APR0_AP19_SHIFT (19U)
248 #define MPU_GICC_APR0_AP19_MASK (0x00080000U)
250 #define MPU_GICC_APR0_AP20_SHIFT (20U)
251 #define MPU_GICC_APR0_AP20_MASK (0x00100000U)
253 #define MPU_GICC_APR0_AP21_SHIFT (21U)
254 #define MPU_GICC_APR0_AP21_MASK (0x00200000U)
256 #define MPU_GICC_APR0_AP22_SHIFT (22U)
257 #define MPU_GICC_APR0_AP22_MASK (0x00400000U)
259 #define MPU_GICC_APR0_AP23_SHIFT (23U)
260 #define MPU_GICC_APR0_AP23_MASK (0x00800000U)
262 #define MPU_GICC_APR0_AP24_SHIFT (24U)
263 #define MPU_GICC_APR0_AP24_MASK (0x01000000U)
265 #define MPU_GICC_APR0_AP25_SHIFT (25U)
266 #define MPU_GICC_APR0_AP25_MASK (0x02000000U)
268 #define MPU_GICC_APR0_AP26_SHIFT (26U)
269 #define MPU_GICC_APR0_AP26_MASK (0x04000000U)
271 #define MPU_GICC_APR0_AP27_SHIFT (27U)
272 #define MPU_GICC_APR0_AP27_MASK (0x08000000U)
274 #define MPU_GICC_APR0_AP28_SHIFT (28U)
275 #define MPU_GICC_APR0_AP28_MASK (0x10000000U)
277 #define MPU_GICC_APR0_AP29_SHIFT (29U)
278 #define MPU_GICC_APR0_AP29_MASK (0x20000000U)
280 #define MPU_GICC_APR0_AP30_SHIFT (30U)
281 #define MPU_GICC_APR0_AP30_MASK (0x40000000U)
283 #define MPU_GICC_APR0_AP31_SHIFT (31U)
284 #define MPU_GICC_APR0_AP31_MASK (0x80000000U)
286 #define MPU_GICC_NSAPR0_AP0_SHIFT (0U)
287 #define MPU_GICC_NSAPR0_AP0_MASK (0x00000001U)
289 #define MPU_GICC_NSAPR0_AP1_SHIFT (1U)
290 #define MPU_GICC_NSAPR0_AP1_MASK (0x00000002U)
292 #define MPU_GICC_NSAPR0_AP2_SHIFT (2U)
293 #define MPU_GICC_NSAPR0_AP2_MASK (0x00000004U)
295 #define MPU_GICC_NSAPR0_AP3_SHIFT (3U)
296 #define MPU_GICC_NSAPR0_AP3_MASK (0x00000008U)
298 #define MPU_GICC_NSAPR0_AP4_SHIFT (4U)
299 #define MPU_GICC_NSAPR0_AP4_MASK (0x00000010U)
301 #define MPU_GICC_NSAPR0_AP5_SHIFT (5U)
302 #define MPU_GICC_NSAPR0_AP5_MASK (0x00000020U)
304 #define MPU_GICC_NSAPR0_AP6_SHIFT (6U)
305 #define MPU_GICC_NSAPR0_AP6_MASK (0x00000040U)
307 #define MPU_GICC_NSAPR0_AP7_SHIFT (7U)
308 #define MPU_GICC_NSAPR0_AP7_MASK (0x00000080U)
310 #define MPU_GICC_NSAPR0_AP8_SHIFT (8U)
311 #define MPU_GICC_NSAPR0_AP8_MASK (0x00000100U)
313 #define MPU_GICC_NSAPR0_AP9_SHIFT (9U)
314 #define MPU_GICC_NSAPR0_AP9_MASK (0x00000200U)
316 #define MPU_GICC_NSAPR0_AP10_SHIFT (10U)
317 #define MPU_GICC_NSAPR0_AP10_MASK (0x00000400U)
319 #define MPU_GICC_NSAPR0_AP11_SHIFT (11U)
320 #define MPU_GICC_NSAPR0_AP11_MASK (0x00000800U)
322 #define MPU_GICC_NSAPR0_AP12_SHIFT (12U)
323 #define MPU_GICC_NSAPR0_AP12_MASK (0x00001000U)
325 #define MPU_GICC_NSAPR0_AP13_SHIFT (13U)
326 #define MPU_GICC_NSAPR0_AP13_MASK (0x00002000U)
328 #define MPU_GICC_NSAPR0_AP14_SHIFT (14U)
329 #define MPU_GICC_NSAPR0_AP14_MASK (0x00004000U)
331 #define MPU_GICC_NSAPR0_AP15_SHIFT (15U)
332 #define MPU_GICC_NSAPR0_AP15_MASK (0x00008000U)
334 #define MPU_GICC_NSAPR0_AP16_SHIFT (16U)
335 #define MPU_GICC_NSAPR0_AP16_MASK (0x00010000U)
337 #define MPU_GICC_NSAPR0_AP17_SHIFT (17U)
338 #define MPU_GICC_NSAPR0_AP17_MASK (0x00020000U)
340 #define MPU_GICC_NSAPR0_AP18_SHIFT (18U)
341 #define MPU_GICC_NSAPR0_AP18_MASK (0x00040000U)
343 #define MPU_GICC_NSAPR0_AP19_SHIFT (19U)
344 #define MPU_GICC_NSAPR0_AP19_MASK (0x00080000U)
346 #define MPU_GICC_NSAPR0_AP20_SHIFT (20U)
347 #define MPU_GICC_NSAPR0_AP20_MASK (0x00100000U)
349 #define MPU_GICC_NSAPR0_AP21_SHIFT (21U)
350 #define MPU_GICC_NSAPR0_AP21_MASK (0x00200000U)
352 #define MPU_GICC_NSAPR0_AP22_SHIFT (22U)
353 #define MPU_GICC_NSAPR0_AP22_MASK (0x00400000U)
355 #define MPU_GICC_NSAPR0_AP23_SHIFT (23U)
356 #define MPU_GICC_NSAPR0_AP23_MASK (0x00800000U)
358 #define MPU_GICC_NSAPR0_AP24_SHIFT (24U)
359 #define MPU_GICC_NSAPR0_AP24_MASK (0x01000000U)
361 #define MPU_GICC_NSAPR0_AP25_SHIFT (25U)
362 #define MPU_GICC_NSAPR0_AP25_MASK (0x02000000U)
364 #define MPU_GICC_NSAPR0_AP26_SHIFT (26U)
365 #define MPU_GICC_NSAPR0_AP26_MASK (0x04000000U)
367 #define MPU_GICC_NSAPR0_AP27_SHIFT (27U)
368 #define MPU_GICC_NSAPR0_AP27_MASK (0x08000000U)
370 #define MPU_GICC_NSAPR0_AP28_SHIFT (28U)
371 #define MPU_GICC_NSAPR0_AP28_MASK (0x10000000U)
373 #define MPU_GICC_NSAPR0_AP29_SHIFT (29U)
374 #define MPU_GICC_NSAPR0_AP29_MASK (0x20000000U)
376 #define MPU_GICC_NSAPR0_AP30_SHIFT (30U)
377 #define MPU_GICC_NSAPR0_AP30_MASK (0x40000000U)
379 #define MPU_GICC_NSAPR0_AP31_SHIFT (31U)
380 #define MPU_GICC_NSAPR0_AP31_MASK (0x80000000U)
382 #define MPU_GICC_IIDR_PRODUCTID_SHIFT (20U)
383 #define MPU_GICC_IIDR_PRODUCTID_MASK (0xfff00000U)
385 #define MPU_GICC_IIDR_ARCHITECTUREVERSION_SHIFT (16U)
386 #define MPU_GICC_IIDR_ARCHITECTUREVERSION_MASK (0x000f0000U)
388 #define MPU_GICC_IIDR_REVISION_SHIFT (12U)
389 #define MPU_GICC_IIDR_REVISION_MASK (0x0000f000U)
391 #define MPU_GICC_IIDR_IMPLEMENTER_SHIFT (0U)
392 #define MPU_GICC_IIDR_IMPLEMENTER_MASK (0x00000fffU)
394 #define MPU_GICC_DIR_INTERRUPTID_SHIFT (0U)
395 #define MPU_GICC_DIR_INTERRUPTID_MASK (0x000003ffU)
397 #define MPU_GICC_DIR_CPUID_SHIFT (10U)
398 #define MPU_GICC_DIR_CPUID_MASK (0x00001c00U)
400 #define MPU_GICC_DIR_RESERVED_SHIFT (13U)
401 #define MPU_GICC_DIR_RESERVED_MASK (0xffffe000U)
403 #ifdef __cplusplus
404 }
405 #endif
406 #endif /* _HW_MPU_INTC_PHYS_H_ */