[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_2_eng / packages / ti / csl / arch / a15 / src / exceptionhandler.asm
1 @******************************************************************************
2 @
3 @ Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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33 @
34 @******************************************************************************
35 @
36 @******************************************************************************
37 @
38 @ exceptionhandler.S - Definitions of exception handlers
39 @
40 @
41 @******************************************************************************
42 @
43 @ Share header file with assembly source code
44 @
45 #include <hw_intc.h>
47 @************************** Global symbols ************************************
48 .global IRQHandler
49 .global FIQHandler
50 .global AbortHandler
51 .global SVCHandler
52 .global UndefInstHandler
53 .global Intc_AbortHandler
54 .global fnRAMVectors
55 .global addrIar
56 .global addrEoi
58 @**************************** Text Section ************************************
59 .text
61 @ This source file is assembled for ARM instructions
62 .code 32
63 @******************************************************************************
64 @* Function Definition of SWI Handler
65 @******************************************************************************
66 @
67 @ The SVC Handler switches to system mode if the SVC number is 458752. If the
68 @ SVC number is different, no mode switching will be done. No other SVC are
69 @ handled here
70 @
71 SVCHandler:
72 STMFD r13!, {r0-r1, r14} @ Save context in SVC stack
73 SUB r13, r13, #0x4 @ Adjust the stack pointer
74 LDR r0, [r14, #-4] @ R0 points to SWI instruction
75 BIC r0, r0, #MASK_SVC_NUM @ Get the SWI number
76 CMP r0, #458752
77 MRSEQ r1, spsr @ Copy SPSR
78 ORREQ r1, r1, #0x1F @ Change the mode to System
79 MSREQ spsr_cf, r1 @ Restore SPSR
80 ADD r13, r13, #0x4 @ Adjust the stack pointer
81 LDMFD r13!, {r0-r1, pc}^ @ Restore registers from IRQ stack
83 @******************************************************************************
84 @* Function Definition of IRQ Handler
85 @******************************************************************************
86 @
87 @ The IRQ handler jumps to the ISR of highest priority pending IRQ.
88 @ This handler doesnot support nesting.
89 @
90 IRQHandler:
91 STMFD r13!, {r0-r3, r12, r14} @ Save context in IRQ stack
92 LDR r1, =addrIar @ Load global variable addrIar address into r1
93 LDR r0, [r1] @ Load IAR address into r0
94 LDR r1, [r0] @ Get the Active IRQ
95 MOV r2, r1 @ save active IRQ in r2
96 AND r1, r1, #IAR_INT_ID_MASK @ Mask the Active IRQ number
97 SUB r1, r1, #PPI_SGI_MASK @ Get Shared pheriperal int number
98 LDR r3, =fnRAMVectors @ Load the base of the vector table
99 LDR r0, =argArray @ Load base of argument
100 LDR r0, [r0, r1, lsl #2] @ Load argument
101 STMFD r13!, {r2} @ Save active IRO in stack
102 ADD r14, pc, #0 @ Save return address in LR
103 LDR pc, [r3, r1, lsl #2] @ Jump to the ISR
104 LDMFD r13!, {r2} @ Get active IRO from stack
105 LDR r1, =addrEoi @ Load global variable addrEoi address into r1
106 LDR r2, [r1] @ Acknowledge the current IRQ
107 STR r3, [r2]
108 DMB @ Barrier to complete the data write
109 LDMFD r13!, {r0-r3, r12, r14} @ Restore registers from IRQ stack
110 SUBS pc, r14, #0x4 @ Return to program before IRQ
112 /*IRQHandler:
113 STMFD r13!, {r0-r3, r12, r14} ; Save context in IRQ stack
114 LDR r2, =addrIar @ Load global variable for IAR address into r1
115 LDR r0, [r2] @ Load IAR address into r0
116 LDR r1, [r0] @ Get the Active IRQ
117 AND r1, r1, #IAR_INT_ID_MASK ; Mask the Active IRQ number
118 LDR r0, _fnRAMVectors ; Load the base of the vector table
119 ADD r14, pc, #0 ; Save return address in LR
120 LDR pc, [r0, r1, lsl #2] ; Jump to the ISR
121 MOV r0, #NEWIRQAGR ; Acknowledge the current IRQ
122 LDR r1, ADDR_CONTROL
123 STR r0, [r1]
124 DMB ; Barrier to complete the data write
125 LDMFD r13!, {r0-r3, r12, r14} ; Restore registers from IRQ stack
126 SUBS pc, r14, #0x4 ; Return to program before IRQ*/
128 @******************************************************************************
129 @* Function Definition of FIQ Handler
130 @******************************************************************************
131 @
132 @ The FIQ Handler jumps to the ISR of the highest priority pending FIQ. The
133 @ pending FIQ. This handler doesnot support nesting
134 @
135 FIQHandler:
136 STMFD r13!, {r0-r3, r12, r14} @ Save context in FIQ stack
137 LDR r2, =addrIar @ Load global variable for IAR address into r1
138 LDR r0, [r2] @ Load IAR address into r0
139 LDR r1, [r0] @ Get the Active FIQ
140 MOV r2, r1
141 AND r1, r1, #IAR_INT_ID_MASK @ Mask the Active IRQ number
142 SUB r1, r1, #PPI_SGI_MASK
143 LDR r0, =fnRAMVectors @ Load the base of the vector table
144 ADD r14, pc, #0 @ Save return address in LR
145 LDR pc, [r0, r1, lsl #2] @ Jump to the ISR
146 LDR r1, =addrEoi @ Load global variable addrEoi address into r1
147 LDR r2, [r1] @ Acknowledge the current IRQ
148 STR r3, [r2]
149 DMB @ Barrier to complete the data write
150 LDMFD r13!, {r0-r3, r12, r14} @ Restore registers from IRQ stack
151 SUBS pc, r14, #0x4 @ Return to program before FIQ
153 @******************************************************************************
154 @* Function Definition of Abort Handler
155 @******************************************************************************
156 @
157 @ The Abort handler goes to the C handler of abort mode.
158 @ if app registers the User defined ISR then will service the ISR else the
159 @ execution enters infinite loop.
160 @
162 AbortHandler:
163 @
164 @ Disable all the interrupts
165 @
166 STMFD r13!, {r0-r3, r12, r14} @ Save context in stack
167 MRS r0, cpsr @ Read from CPSR
168 ORR r0, r0, #0xC0 @ Clear the IRQ and FIQ bits
169 MSR cpsr, r0 @ Write to CPSR
170 ADD r14, pc, #0 @ Store the return address
171 LDR pc, =Intc_AbortHandler @ Go to C handler
172 LDMFD r13!, {r0-r3, r12, r14} @ Restore registers from IRQ stack
173 SUBS pc, r14, #0x4 @ Return to program before IRQ
175 @******************************************************************************
176 @* Function Definition of Undef Handler
177 @******************************************************************************
178 @ The Undef handler enters infinite loop
179 @
181 UndefInstHandler:
182 @
183 @ Disable all the interrupts
184 @
185 MRS r0, cpsr @ Read from CPSR
186 ORR r0, r0, #0xC0 @ Clear the IRQ and FIQ bits
187 MSR cpsr, r0 @ Write to CPSR
188 ADD r14, pc, #0 @ Store the return address
189 @
190 @ Go to infinite loop
191 @
192 loop0:
193 B loop0
194 @*****************************************************************************
195 @
196 @ End of the file
197 @
198 .end