[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_2_eng / packages / ti / csl / csl_ipcAux.h
1 /* ============================================================================
2 * Copyright (c) Texas Instruments Incorporated 2008, 2009
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
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19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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32 */
34 /**
35 * @file csl_ipcAux.h
36 *
37 * @brief
38 * API Auxilary header file for IPC CSL. It gives the definitions of the
39 * query & control functions.
40 *
41 * \par
42 * ============================================================================
43 * @n (C) Copyright 2008, 2009, Texas Instruments, Inc.
44 * @n Use of this software is controlled by the terms and conditions found
45 * @n in the license agreement under which this software has been supplied.
46 * ===========================================================================
47 * \par
48 */
50 #ifndef CSL_IPCAUX_H_
51 #define CSL_IPCAUX_H_
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
57 #include <ti/csl/csl_ipc.h>
59 /** @addtogroup CSL_IPC_FUNCTION
60 @{ */
62 /** ============================================================================
63 * @n@b CSL_IPC_genNMIEvent
64 *
65 * @b Description
66 * @n This function sets the NMIG bit of the NMI Generation Register (NMIGRx)
67 * to create an NMI pulse to the GEM corresponding to the index
68 * specified here.
69 *
70 * @b Arguments
71 @verbatim
72 index GEM number for which the NMI event is to be raised.
73 @endverbatim
74 *
75 * <b> Return Value </b>
76 * @n None
77 *
78 * <b> Pre Condition </b>
79 * @n None.
80 *
81 * <b> Post Condition </b>
82 * @n NMIG bit in the corresponding NMIGRx register configured.
83 *
84 * @b Writes
85 * @n IPC_NMIGR_NMIG=1
86 *
87 * @b Example
88 * @verbatim
89 Example 1: Raise an NMI interrupt to Gem 2
90 Uint32 index = 2;
92 CSL_IPC_genNMIEvent (index);
93 @endverbatim
94 * =============================================================================
95 */
96 static inline void CSL_IPC_genNMIEvent (
97 Uint32 index
98 )
99 {
100 CSL_FINS (hIpc->NMIGR[index], IPC_NMIGR_NMIG, 1);
102 return;
103 }
106 /** ============================================================================
107 * @n@b CSL_IPC_genGEMInterrupt
108 *
109 * @b Description
110 * @n This function sets the IPCG bit of the IPC Generation Register (IPCGRx)
111 * to create an inter-DSP pulse to the GEM corresponding to the index
112 * specified here. This API also configures the source ID for this
113 * interrupt by setting the SRCSx bit of the IPCGRx register based on
114 * the source ID specified.
115 *
116 * @b Arguments
117 @verbatim
118 index GEM number for which the interrupt is to be raised.
119 srcId Indicates which of the 0-27 SRCSx bits needs to be set
120 in the IPCGRx registers corresponding to the index specified.
121 @endverbatim
122 *
123 * <b> Return Value </b>
124 * @n None
125 *
126 * <b> Pre Condition </b>
127 * @n None
128 *
129 * <b> Post Condition </b>
130 * @n IPCG and SRCSx/SRCCx bits in the corresponding IPCGRx/IPCARx register
131 * configured.
132 *
133 * @b Writes
134 * @n IPC_IPCGR_IPCG=1,
135 * IPC_IPCGR_SRCS0=1;
136 * IPC_IPCGR_SRCS1=1;
137 * IPC_IPCGR_SRCS2=1;
138 * IPC_IPCGR_SRCS3=1;
139 * IPC_IPCGR_SRCS4=1;
140 * IPC_IPCGR_SRCS5=1;
141 * IPC_IPCGR_SRCS6=1;
142 * IPC_IPCGR_SRCS7=1;
143 * IPC_IPCGR_SRCS8=1;
144 * IPC_IPCGR_SRCS9=1;
145 * IPC_IPCGR_SRCS10=1;
146 * IPC_IPCGR_SRCS11=1;
147 * IPC_IPCGR_SRCS12=1;
148 * IPC_IPCGR_SRCS13=1;
149 * IPC_IPCGR_SRCS14=1;
150 * IPC_IPCGR_SRCS15=1;
151 * IPC_IPCGR_SRCS16=1;
152 * IPC_IPCGR_SRCS17=1;
153 * IPC_IPCGR_SRCS18=1;
154 * IPC_IPCGR_SRCS19=1;
155 * IPC_IPCGR_SRCS20=1;
156 * IPC_IPCGR_SRCS21=1;
157 * IPC_IPCGR_SRCS22=1;
158 * IPC_IPCGR_SRCS23=1;
159 * IPC_IPCGR_SRCS24=1;
160 * IPC_IPCGR_SRCS25=1;
161 * IPC_IPCGR_SRCS26=1;
162 * IPC_IPCGR_SRCS27=1;
163 *
164 * @b Affects
165 * @n IPC_IPCAR_SRCC0=1;
166 * IPC_IPCAR_SRCC1=1;
167 * IPC_IPCAR_SRCC2=1;
168 * IPC_IPCAR_SRCC3=1;
169 * IPC_IPCAR_SRCC4=1;
170 * IPC_IPCAR_SRCC5=1;
171 * IPC_IPCAR_SRCC6=1;
172 * IPC_IPCAR_SRCC7=1;
173 * IPC_IPCAR_SRCC8=1;
174 * IPC_IPCAR_SRCC9=1;
175 * IPC_IPCAR_SRCC10=1;
176 * IPC_IPCAR_SRCC11=1;
177 * IPC_IPCAR_SRCC12=1;
178 * IPC_IPCAR_SRCC13=1;
179 * IPC_IPCAR_SRCC14=1;
180 * IPC_IPCAR_SRCC15=1;
181 * IPC_IPCAR_SRCC16=1;
182 * IPC_IPCAR_SRCC17=1;
183 * IPC_IPCAR_SRCC18=1;
184 * IPC_IPCAR_SRCC19=1;
185 * IPC_IPCAR_SRCC20=1;
186 * IPC_IPCAR_SRCC21=1;
187 * IPC_IPCAR_SRCC22=1;
188 * IPC_IPCAR_SRCC23=1;
189 * IPC_IPCAR_SRCC24=1;
190 * IPC_IPCAR_SRCC25=1;
191 * IPC_IPCAR_SRCC26=1;
192 * IPC_IPCAR_SRCC27=1
193 *
194 * @b Example
195 * @verbatim
196 Example 1: An application running on GEM 2 is trying to raise
197 an interrupt to Gem 1. The source Id for Gem 2 say is 2.
198 Uint32 index = 1;
199 Uint32 srcId = 2;
201 CSL_IPC_genGEMInterrupt (index, srcId);
202 @endverbatim
203 * =============================================================================
204 */
205 static inline void CSL_IPC_genGEMInterrupt (
206 Uint32 index,
207 Uint32 srcId
208 )
209 {
210 hIpc->IPCGR[index] = CSL_FMK (IPC_IPCGR_IPCG, 1) |
211 CSL_FMKR (CSL_IPC_IPCGR_SRCS0_SHIFT + srcId, CSL_IPC_IPCGR_SRCS0_SHIFT + srcId, 1);
213 return;
214 }
217 /** ============================================================================
218 * @n@b CSL_IPC_isGEMInterruptSourceSet
219 *
220 * @b Description
221 * @n This function checks if the SRCSx bit of the IPCGRx register is set.
222 * It returns 1 if the SRCSx bit corresponding to the srcId is set in the
223 * IPCGRx register corresponding to the index specified. Otherwise it returns
224 * 0.
225 *
226 * @b Arguments
227 @verbatim
228 index GEM number for which the IPCGRx register needs to be checked.
229 srcId Indicates which of the 0-27 SRCSx bits needs to be read
230 in the IPCGRx registers corresponding to the index specified.
231 @endverbatim
232 *
233 * <b> Return Value </b>
234 * @n 1 - Indicates that the corresponding SRCSx bit is set and the
235 * srcId specified is in fact the source for the IPC Gem interrupt. \n
236 * 0 - Indicates that corresponding SRCSx bit not set and the
237 * srcId specified is not the IPC source.
238 *
239 * <b> Pre Condition </b>
240 * @n None
241 *
242 * <b> Post Condition </b>
243 * @n None
244 *
245 * @b Reads
246 * @n IPC_IPCGR_SRCS0;
247 * IPC_IPCGR_SRCS1;
248 * IPC_IPCGR_SRCS2;
249 * IPC_IPCGR_SRCS3;
250 * IPC_IPCGR_SRCS4;
251 * IPC_IPCGR_SRCS5;
252 * IPC_IPCGR_SRCS6;
253 * IPC_IPCGR_SRCS7;
254 * IPC_IPCGR_SRCS8;
255 * IPC_IPCGR_SRCS9;
256 * IPC_IPCGR_SRCS10;
257 * IPC_IPCGR_SRCS11;
258 * IPC_IPCGR_SRCS12;
259 * IPC_IPCGR_SRCS13;
260 * IPC_IPCGR_SRCS14;
261 * IPC_IPCGR_SRCS15;
262 * IPC_IPCGR_SRCS16;
263 * IPC_IPCGR_SRCS17;
264 * IPC_IPCGR_SRCS18;
265 * IPC_IPCGR_SRCS19;
266 * IPC_IPCGR_SRCS20;
267 * IPC_IPCGR_SRCS21;
268 * IPC_IPCGR_SRCS22;
269 * IPC_IPCGR_SRCS23;
270 * IPC_IPCGR_SRCS24;
271 * IPC_IPCGR_SRCS25;
272 * IPC_IPCGR_SRCS26;
273 * IPC_IPCGR_SRCS27
274 *
275 * @b Example
276 * @verbatim
277 Example 1: An application running on Gem 1 received an interrupt and
278 wants to check if the interrupt was from the core it was waiting on,
279 i.e., the Gem 2.
281 Uint32 index = 1;
282 Uint32 srcId = 2;
283 Uint32 retVal;
285 retVal = CSL_IPC_isGEMInterruptSourceSet (index, srcId);
287 if (retVal == 0)
288 {
289 ... // Maybe cotinue waiting for the IPC/message
290 }
291 else
292 {
293 ... // Do the needful processing.
294 }
295 @endverbatim
296 * =============================================================================
297 */
298 static inline Uint32 CSL_IPC_isGEMInterruptSourceSet (
299 Uint32 index,
300 Uint32 srcId
301 )
302 {
303 return CSL_FEXTR (hIpc->IPCGR[index], CSL_IPC_IPCGR_SRCS0_SHIFT + srcId, CSL_IPC_IPCGR_SRCS0_SHIFT + srcId);
305 }
307 /** ============================================================================
308 * @n@b CSL_IPC_isGEMInterruptAckSet
309 *
310 * @b Description
311 * @n This function checks if the SRCCx bit of the IPCARx register is set.
312 * It returns 1 if the SRCCx bit corresponding to the srcId is set in the
313 * IPCARx register corresponding to the index specified. Otherwise it returns
314 * 0.
315 *
316 * @b Arguments
317 @verbatim
318 index GEM number for which the IPCARx register needs to be checked.
319 srcId Indicates which of the 0-27 SRCCx bits needs to be read
320 in the IPCARx registers corresponding to the index specified.
321 @endverbatim
322 *
323 * <b> Return Value </b>
324 * @n 1 - Indicates that the corresponding SRCCx bit is set and the
325 * srcId specified is in fact the source for the IPC Gem interrupt. \n
326 * 0 - Indicates that corresponding SRCCx bit not set and the
327 * srcId specified is not the IPC source.
328 *
329 * <b> Pre Condition </b>
330 * @n None
331 *
332 * <b> Post Condition </b>
333 * @n None
334 *
335 * @b Reads
336 * @n IPC_IPCAR_SRCC0;
337 * IPC_IPCAR_SRCC1;
338 * IPC_IPCAR_SRCC2;
339 * IPC_IPCAR_SRCC3;
340 * IPC_IPCAR_SRCC4;
341 * IPC_IPCAR_SRCC5;
342 * IPC_IPCAR_SRCC6;
343 * IPC_IPCAR_SRCC7;
344 * IPC_IPCAR_SRCC8;
345 * IPC_IPCAR_SRCC9;
346 * IPC_IPCAR_SRCC10;
347 * IPC_IPCAR_SRCC11;
348 * IPC_IPCAR_SRCC12;
349 * IPC_IPCAR_SRCC13;
350 * IPC_IPCAR_SRCC14;
351 * IPC_IPCAR_SRCC15;
352 * IPC_IPCAR_SRCC16;
353 * IPC_IPCAR_SRCC17;
354 * IPC_IPCAR_SRCC18;
355 * IPC_IPCAR_SRCC19;
356 * IPC_IPCAR_SRCC20;
357 * IPC_IPCAR_SRCC21;
358 * IPC_IPCAR_SRCC22;
359 * IPC_IPCAR_SRCC23;
360 * IPC_IPCAR_SRCC24;
361 * IPC_IPCAR_SRCC25;
362 * IPC_IPCAR_SRCC26;
363 * IPC_IPCAR_SRCC27
364 *
365 * @b Example
366 * @verbatim
367 Uint32 index = 1;
368 Uint32 srcId = 2;
369 Uint32 retVal;
371 retVal = CSL_IPC_isGEMInterruptAckSet (index, srcId);
372 @endverbatim
373 * =============================================================================
374 */
375 static inline Uint32 CSL_IPC_isGEMInterruptAckSet (
376 Uint32 index,
377 Uint32 srcId
378 )
379 {
380 return CSL_FEXTR (hIpc->IPCAR[index], CSL_IPC_IPCAR_SRCC0_SHIFT + srcId, CSL_IPC_IPCAR_SRCC0_SHIFT + srcId);
382 }
384 /** ============================================================================
385 * @n@b CSL_IPC_clearGEMInterruptSource
386 *
387 * @b Description
388 * @n This function clears the interrupt source IDs by setting the SRCCx bit of
389 * the IPC Acknowledgment Register (IPCARx) and SRCSx bit of IPC Generation
390 * Register (IPCGRx) corresponding to the GEM index and Source ID specified.
391 *
392 * @b Arguments
393 @verbatim
394 index GEM number for which the interrupt surce is to be cleared.
395 srcId Indicates which of the 0-27 SRCSx/SRCCx bits needs to be cleared
396 in the IPCGRx/IPCARx registers corresponding to the index specified.
397 @endverbatim
398 *
399 * <b> Return Value </b>
400 * @n None
401 *
402 * <b> Pre Condition </b>
403 * @n None
404 *
405 * <b> Post Condition </b>
406 * @n SRCSx/SRCCx bits in the corresponding IPCGRx/IPCARx register are cleared.
407 *
408 * @b Writes
409 * @n IPC_IPCAR_SRCC0=0;
410 * IPC_IPCAR_SRCC1=0;
411 * IPC_IPCAR_SRCC2=0;
412 * IPC_IPCAR_SRCC3=0;
413 * IPC_IPCAR_SRCC4=0;
414 * IPC_IPCAR_SRCC5=0;
415 * IPC_IPCAR_SRCC6=0;
416 * IPC_IPCAR_SRCC7=0;
417 * IPC_IPCAR_SRCC8=0;
418 * IPC_IPCAR_SRCC9=0;
419 * IPC_IPCAR_SRCC10=0;
420 * IPC_IPCAR_SRCC11=0;
421 * IPC_IPCAR_SRCC12=0;
422 * IPC_IPCAR_SRCC13=0;
423 * IPC_IPCAR_SRCC14=0;
424 * IPC_IPCAR_SRCC15=0;
425 * IPC_IPCAR_SRCC16=0;
426 * IPC_IPCAR_SRCC17=0;
427 * IPC_IPCAR_SRCC18=0;
428 * IPC_IPCAR_SRCC19=0;
429 * IPC_IPCAR_SRCC20=0;
430 * IPC_IPCAR_SRCC21=0;
431 * IPC_IPCAR_SRCC22=0;
432 * IPC_IPCAR_SRCC23=0;
433 * IPC_IPCAR_SRCC24=0;
434 * IPC_IPCAR_SRCC25=0;
435 * IPC_IPCAR_SRCC26=0;
436 * IPC_IPCAR_SRCC27=0
437 *
438 * @b Affects
439 * @n IPC_IPCGR_SRCS0=0,
440 * IPC_IPCGR_SRCS1=0;
441 * IPC_IPCGR_SRCS2=0;
442 * IPC_IPCGR_SRCS3=0;
443 * IPC_IPCGR_SRCS4=0;
444 * IPC_IPCGR_SRCS5=0;
445 * IPC_IPCGR_SRCS6=0;
446 * IPC_IPCGR_SRCS7=0;
447 * IPC_IPCGR_SRCS8=0;
448 * IPC_IPCGR_SRCS9=0;
449 * IPC_IPCGR_SRCS10=0;
450 * IPC_IPCGR_SRCS11=0;
451 * IPC_IPCGR_SRCS12=0;
452 * IPC_IPCGR_SRCS13=0;
453 * IPC_IPCGR_SRCS14=0;
454 * IPC_IPCGR_SRCS15=0;
455 * IPC_IPCGR_SRCS16=0;
456 * IPC_IPCGR_SRCS17=0;
457 * IPC_IPCGR_SRCS18=0;
458 * IPC_IPCGR_SRCS19=0;
459 * IPC_IPCGR_SRCS20=0;
460 * IPC_IPCGR_SRCS21=0;
461 * IPC_IPCGR_SRCS22=0;
462 * IPC_IPCGR_SRCS23=0;
463 * IPC_IPCGR_SRCS24=0;
464 * IPC_IPCGR_SRCS25=0;
465 * IPC_IPCGR_SRCS26=0;
466 * IPC_IPCGR_SRCS27=0
467 *
468 * @b Example
469 * @verbatim
470 Example 1: Clear the interrupt for Gem 1 raised by Gem 2.
471 Uint32 index = 1;
472 Uint32 srcId = 2;
474 CSL_IPC_clearGEMInterruptSource (index, srcId);
475 @endverbatim
476 * =============================================================================
477 */
478 static inline void CSL_IPC_clearGEMInterruptSource (
479 Uint32 index,
480 Uint32 srcId
481 )
482 {
483 hIpc->IPCAR[index] = CSL_FMKR (CSL_IPC_IPCAR_SRCC0_SHIFT + srcId, CSL_IPC_IPCAR_SRCC0_SHIFT + srcId, 1);
485 return;
486 }
489 /** ============================================================================
490 * @n@b CSL_IPC_genHostInterrupt
491 *
492 * @b Description
493 * @n This function sets the IPCG bit of the Host IPC Generation Register (IPCGRH)
494 * to create an interrupt pulse on the device pin. This API also configures the
495 * source ID for this interrupt by setting the SRCSx bit of the IPCGRHx
496 * register based on the source ID specified.
497 *
498 * @b Arguments
499 @verbatim
500 srcId Indicates which of the 0-27 SRCSx bits needs to be set
501 in the IPCGRH register.
502 @endverbatim
503 *
504 * <b> Return Value </b>
505 * @n None
506 *
507 * <b> Pre Condition </b>
508 * @n None
509 *
510 * <b> Post Condition </b>
511 * @n IPCG and SRCSx/SRCCx bits in the IPCGRH/IPCARH register configured.
512 *
513 * @b Writes
514 * @n IPC_IPCGRH_IPCG=1,
515 * IPC_IPCGRH_SRCS0=1;
516 * IPC_IPCGRH_SRCS1=1;
517 * IPC_IPCGRH_SRCS2=1;
518 * IPC_IPCGRH_SRCS3=1;
519 * IPC_IPCGRH_SRCS4=1;
520 * IPC_IPCGRH_SRCS5=1;
521 * IPC_IPCGRH_SRCS6=1;
522 * IPC_IPCGRH_SRCS7=1;
523 * IPC_IPCGRH_SRCS8=1;
524 * IPC_IPCGRH_SRCS9=1;
525 * IPC_IPCGRH_SRCS10=1;
526 * IPC_IPCGRH_SRCS11=1;
527 * IPC_IPCGRH_SRCS12=1;
528 * IPC_IPCGRH_SRCS13=1;
529 * IPC_IPCGRH_SRCS14=1;
530 * IPC_IPCGRH_SRCS15=1;
531 * IPC_IPCGRH_SRCS16=1;
532 * IPC_IPCGRH_SRCS17=1;
533 * IPC_IPCGRH_SRCS18=1;
534 * IPC_IPCGRH_SRCS19=1;
535 * IPC_IPCGRH_SRCS20=1;
536 * IPC_IPCGRH_SRCS21=1;
537 * IPC_IPCGRH_SRCS22=1;
538 * IPC_IPCGRH_SRCS23=1;
539 * IPC_IPCGRH_SRCS24=1;
540 * IPC_IPCGRH_SRCS25=1;
541 * IPC_IPCGRH_SRCS26=1;
542 * IPC_IPCGRH_SRCS27=1
543 *
544 * @b Affects
545 * IPC_IPCARH_SRCC0=1;
546 * IPC_IPCARH_SRCC1=1;
547 * IPC_IPCARH_SRCC2=1;
548 * IPC_IPCARH_SRCC3=1;
549 * IPC_IPCARH_SRCC4=1;
550 * IPC_IPCARH_SRCC5=1;
551 * IPC_IPCARH_SRCC6=1;
552 * IPC_IPCARH_SRCC7=1;
553 * IPC_IPCARH_SRCC8=1;
554 * IPC_IPCARH_SRCC9=1;
555 * IPC_IPCARH_SRCC10=1;
556 * IPC_IPCARH_SRCC11=1;
557 * IPC_IPCARH_SRCC12=1;
558 * IPC_IPCARH_SRCC13=1;
559 * IPC_IPCARH_SRCC14=1;
560 * IPC_IPCARH_SRCC15=1;
561 * IPC_IPCARH_SRCC16=1;
562 * IPC_IPCARH_SRCC17=1;
563 * IPC_IPCARH_SRCC18=1;
564 * IPC_IPCARH_SRCC19=1;
565 * IPC_IPCARH_SRCC20=1;
566 * IPC_IPCARH_SRCC21=1;
567 * IPC_IPCARH_SRCC22=1;
568 * IPC_IPCARH_SRCC23=1;
569 * IPC_IPCARH_SRCC24=1;
570 * IPC_IPCARH_SRCC25=1;
571 * IPC_IPCARH_SRCC26=1;
572 * IPC_IPCARH_SRCC27=1
573 *
574 * @b Example
575 * @verbatim
576 Example 1: An application running on GEM 2 is trying to raise
577 a host interrupt.
578 Uint32 srcId = 2;
580 CSL_IPC_genHostInterrupt (srcId);
581 @endverbatim
582 * =============================================================================
583 */
584 static inline void CSL_IPC_genHostInterrupt (
585 Uint32 srcId
586 )
587 {
588 hIpc->IPCGRH = CSL_FMK (IPC_IPCGRH_IPCG, 1) |
589 CSL_FMKR (CSL_IPC_IPCGRH_SRCS0_SHIFT + srcId, CSL_IPC_IPCGRH_SRCS0_SHIFT + srcId, 1);
591 return;
592 }
595 /** ============================================================================
596 * @n@b CSL_IPC_isHostInterruptSourceSet
597 *
598 * @b Description
599 * @n This function checks if the SRCSx bit of the IPCGRH register is set.
600 * It returns 1 if the SRCSx bit corresponding to the srcId is set in the
601 * IPCGRH register. Otherwise it returns 0.
602 *
603 * @b Arguments
604 @verbatim
605 srcId Indicates which of the 0-27 SRCSx bits needs to be read
606 in the IPCGRH register.
607 @endverbatim
608 *
609 * <b> Return Value </b>
610 * @n 1 - Indicates that the corresponding SRCSx bit is set and the
611 * srcId specified is in fact the source for the IPC Host interrupt. \n
612 * 0 - Indicates that corresponding SRCSx bit not set and the
613 * srcId specified is not the IPC source.
614 *
615 * <b> Pre Condition </b>
616 * @n None
617 *
618 * <b> Post Condition </b>
619 * @n None
620 *
621 * @b Reads
622 * @n IPC_IPCGRH_SRCS0;
623 * IPC_IPCGRH_SRCS1;
624 * IPC_IPCGRH_SRCS2;
625 * IPC_IPCGRH_SRCS3;
626 * IPC_IPCGRH_SRCS4;
627 * IPC_IPCGRH_SRCS5;
628 * IPC_IPCGRH_SRCS6;
629 * IPC_IPCGRH_SRCS7;
630 * IPC_IPCGRH_SRCS8;
631 * IPC_IPCGRH_SRCS9;
632 * IPC_IPCGRH_SRCS10;
633 * IPC_IPCGRH_SRCS11;
634 * IPC_IPCGRH_SRCS12;
635 * IPC_IPCGRH_SRCS13;
636 * IPC_IPCGRH_SRCS14;
637 * IPC_IPCGRH_SRCS15;
638 * IPC_IPCGRH_SRCS16;
639 * IPC_IPCGRH_SRCS17;
640 * IPC_IPCGRH_SRCS18;
641 * IPC_IPCGRH_SRCS19;
642 * IPC_IPCGRH_SRCS20;
643 * IPC_IPCGRH_SRCS21;
644 * IPC_IPCGRH_SRCS22;
645 * IPC_IPCGRH_SRCS23;
646 * IPC_IPCGRH_SRCS24;
647 * IPC_IPCGRH_SRCS25;
648 * IPC_IPCGRH_SRCS26;
649 * IPC_IPCGRH_SRCS27
650 *
651 * @b Example
652 * @verbatim
653 Example 1: Check if the host interrupt's source was set correctly
654 to 2, i.e., the Gem 2 the source of the host interrupt.
656 Uint32 srcId = 2;
657 Uint32 retVal;
659 retVal = CSL_IPC_isHostInterruptSourceSet (srcId);
661 if (retVal == 0)
662 {
663 ... // Do something.
664 }
665 else
666 {
667 ... // Do the needful processing.
668 }
669 @endverbatim
670 * =============================================================================
671 */
672 static inline Uint32 CSL_IPC_isHostInterruptSourceSet (
673 Uint32 srcId
674 )
675 {
676 return CSL_FEXTR (hIpc->IPCGRH, CSL_IPC_IPCGRH_SRCS0_SHIFT + srcId, CSL_IPC_IPCGRH_SRCS0_SHIFT + srcId);
678 }
681 /** ============================================================================
682 * @n@b CSL_IPC_isHostInterruptAckSet
683 *
684 * @b Description
685 * @n This function checks if the SRCCx bit of the IPCARH register is set.
686 * It returns 1 if the SRCCx bit corresponding to the srcId is set in the
687 * IPCARH register. Otherwise it returns 0.
688 *
689 * @b Arguments
690 @verbatim
691 srcId Indicates which of the 0-27 SRCCx bits needs to be read
692 in the IPCARH register.
693 @endverbatim
694 *
695 * <b> Return Value </b>
696 * @n 1 - Indicates that the corresponding SRCCx bit is set and the
697 * srcId specified is in fact the source for the IPC Host interrupt. \n
698 * 0 - Indicates that corresponding SRCCx bit not set and the
699 * srcId specified is not the IPC source.
700 *
701 * <b> Pre Condition </b>
702 * @n None
703 *
704 * <b> Post Condition </b>
705 * @n None
706 *
707 * @b Reads
708 * @n IPC_IPCARH_SRCC0;
709 * IPC_IPCARH_SRCC1;
710 * IPC_IPCARH_SRCC2;
711 * IPC_IPCARH_SRCC3;
712 * IPC_IPCARH_SRCC4;
713 * IPC_IPCARH_SRCC5;
714 * IPC_IPCARH_SRCC6;
715 * IPC_IPCARH_SRCC7;
716 * IPC_IPCARH_SRCC8;
717 * IPC_IPCARH_SRCC9;
718 * IPC_IPCARH_SRCC10;
719 * IPC_IPCARH_SRCC11;
720 * IPC_IPCARH_SRCC12;
721 * IPC_IPCARH_SRCC13;
722 * IPC_IPCARH_SRCC14;
723 * IPC_IPCARH_SRCC15;
724 * IPC_IPCARH_SRCC16;
725 * IPC_IPCARH_SRCC17;
726 * IPC_IPCARH_SRCC18;
727 * IPC_IPCARH_SRCC19;
728 * IPC_IPCARH_SRCC20;
729 * IPC_IPCARH_SRCC21;
730 * IPC_IPCARH_SRCC22;
731 * IPC_IPCARH_SRCC23;
732 * IPC_IPCARH_SRCC24;
733 * IPC_IPCARH_SRCC25;
734 * IPC_IPCARH_SRCC26;
735 * IPC_IPCARH_SRCC27
736 *
737 * @b Example
738 * @verbatim
739 Uint32 srcId = 2;
740 Uint32 retVal;
742 retVal = CSL_IPC_isHostInterruptAckSet (srcId);
743 @endverbatim
744 * =============================================================================
745 */
746 static inline Uint32 CSL_IPC_isHostInterruptAckSet (
747 Uint32 srcId
748 )
749 {
750 return CSL_FEXTR (hIpc->IPCARH, CSL_IPC_IPCARH_SRCC0_SHIFT + srcId, CSL_IPC_IPCARH_SRCC0_SHIFT + srcId);
752 }
755 /** ============================================================================
756 * @n@b CSL_IPC_clearHostInterruptSource
757 *
758 * @b Description
759 * @n This function clears the interrupt source IDs by setting the SRCCx bit
760 * of the Host IPC Acknowledgment Register (IPCARH) and SRCSx bit of Host
761 * IPC Generation Register (IPCGRH) corresponding to the Source ID specified.
762 *
763 * @b Arguments
764 @verbatim
765 srcId Indicates which of the 0-27 SRCSx/SRCCx bits needs to be cleared
766 in the IPCGRH/IPCARH registers.
767 @endverbatim
768 *
769 * <b> Return Value </b>
770 * @n None
771 *
772 * <b> Pre Condition </b>
773 * @n None
774 *
775 * <b> Post Condition </b>
776 * @n SRCSx/SRCCx bits in the corresponding IPCGRH/IPCARH register are cleared.
777 *
778 * @b Writes
779 * @n IPC_IPCARH_SRCC0=0;
780 * IPC_IPCARH_SRCC1=0;
781 * IPC_IPCARH_SRCC2=0;
782 * IPC_IPCARH_SRCC3=0;
783 * IPC_IPCARH_SRCC4=0;
784 * IPC_IPCARH_SRCC5=0;
785 * IPC_IPCARH_SRCC6=0;
786 * IPC_IPCARH_SRCC7=0;
787 * IPC_IPCARH_SRCC8=0;
788 * IPC_IPCARH_SRCC9=0;
789 * IPC_IPCARH_SRCC10=0;
790 * IPC_IPCARH_SRCC11=0;
791 * IPC_IPCARH_SRCC12=0;
792 * IPC_IPCARH_SRCC13=0;
793 * IPC_IPCARH_SRCC14=0;
794 * IPC_IPCARH_SRCC15=0;
795 * IPC_IPCARH_SRCC16=0;
796 * IPC_IPCARH_SRCC17=0;
797 * IPC_IPCARH_SRCC18=0;
798 * IPC_IPCARH_SRCC19=0;
799 * IPC_IPCARH_SRCC20=0;
800 * IPC_IPCARH_SRCC21=0;
801 * IPC_IPCARH_SRCC22=0;
802 * IPC_IPCARH_SRCC23=0;
803 * IPC_IPCARH_SRCC24=0;
804 * IPC_IPCARH_SRCC25=0;
805 * IPC_IPCARH_SRCC26=0;
806 * IPC_IPCARH_SRCC27=0
807 *
808 * @b Affects
809 * @n IPC_IPCGRH_SRCS0=0;
810 * IPC_IPCGRH_SRCS1=0;
811 * IPC_IPCGRH_SRCS2=0;
812 * IPC_IPCGRH_SRCS3=0;
813 * IPC_IPCGRH_SRCS4=0;
814 * IPC_IPCGRH_SRCS5=0;
815 * IPC_IPCGRH_SRCS6=0;
816 * IPC_IPCGRH_SRCS7=0;
817 * IPC_IPCGRH_SRCS8=0;
818 * IPC_IPCGRH_SRCS9=0;
819 * IPC_IPCGRH_SRCS10=0;
820 * IPC_IPCGRH_SRCS11=0;
821 * IPC_IPCGRH_SRCS12=0;
822 * IPC_IPCGRH_SRCS13=0;
823 * IPC_IPCGRH_SRCS14=0;
824 * IPC_IPCGRH_SRCS15=0;
825 * IPC_IPCGRH_SRCS16=0;
826 * IPC_IPCGRH_SRCS17=0;
827 * IPC_IPCGRH_SRCS18=0;
828 * IPC_IPCGRH_SRCS19=0;
829 * IPC_IPCGRH_SRCS20=0;
830 * IPC_IPCGRH_SRCS21=0;
831 * IPC_IPCGRH_SRCS22=0;
832 * IPC_IPCGRH_SRCS23=0;
833 * IPC_IPCGRH_SRCS24=0;
834 * IPC_IPCGRH_SRCS25=0;
835 * IPC_IPCGRH_SRCS26=0;
836 * IPC_IPCGRH_SRCS27=0;
837 *
838 * @b Example
839 * @verbatim
840 Example 1: Clear the host interrupt raised by Gem 2.
841 Uint32 srcId = 2;
843 CSL_IPC_clearHostInterruptSource (srcId);
844 @endverbatim
845 * =============================================================================
846 */
847 static inline void CSL_IPC_clearHostInterruptSource (
848 Uint32 srcId
849 )
850 {
851 hIpc->IPCARH = CSL_FMKR (CSL_IPC_IPCGRH_SRCS0_SHIFT + srcId, CSL_IPC_IPCGRH_SRCS0_SHIFT + srcId, 1);
853 return;
854 }
856 #ifdef __cplusplus
857 }
858 #endif
860 /* @} */
862 #endif /*CSL_IPCAUX_H_*/