1 //
2 // $Source: /cvsstl/ti/pa/dec/dsd2/alpha/dsd_a.h,v $
3 // $Revision: 1.16 $
4 //
5 // DSD Decoder alpha codes
6 //
7 // Copyright 2004-2005, Texas Instruments, Inc. All rights reserved.
8 //
9 // $Log: dsd_a.h,v $
10 // Revision 1.16 2012/10/10 14:56:49 qinsu
11 // Added support for 5.6 MHz input.
12 //
13 // Revision 1.15 2006/06/19 20:41:05 jhheo
14 // Initial commit for MID 987
15 //
16 // Revision 1.18 2006/05/26 16:15:16 mwatson
17 // Fixing errant swapping of Bypass Enable/Disable in previous
18 // commit; MID 573.
19 //
20 // Revision 1.17 2006/05/26 13:48:01 mwatson
21 // Correcting Bypass Enable/Disable swap; MID 573.
22 //
23 // Revision 1.16 2006/05/26 12:55:23 mwatson
24 // Fixing whitespaces only; MID 573.
25 //
26 // Revision 1.15 2006/05/26 05:14:20 uparikh
27 // MID 573 - Use 'Bypass' instead of 'Use'
28 //
29 // Revision 1.14 2006/05/23 21:22:53 mwatson
30 // Replacing direct BETA IDs with MACRO definitions; adding acpbeta.h
31 // include; MID 507.
32 //
33 // Revision 1.13 2006/05/19 09:09:57 uparikh
34 // MID 573 - Use OperationalMode instead of OperationMode
35 //
36 // Revision 1.12 2005/11/18 20:25:19 jhheo
37 // Alpha code and Delay bug fixed
38 //
39 // Revision 1.11 2005/11/18 16:10:06 mwatson
40 // Fixing spelling, whitespaces.
41 //
42 // Revision 1.10 2005/11/16 22:14:16 jhheo
43 // DSD DelayUnit register support and support for delay size smaller than the frame size added
44 //
45 // Revision 1.9 2005/08/12 18:17:04 jhheo
46 // alpha code bugs fixed
47 //
48 // Revision 1.8 2005/08/07 21:23:22 mwatson
49 // Correcting errors.
50 //
51 // Revision 1.7 2005/08/05 16:05:52 mwatson
52 // Replacing tabs and updating readDSDControl for MID 451.
53 //
54 // Revision 1.6 2005/07/22 20:50:30 jhheo
55 // new status/control registers and alpha code added for DSD delay function
56 //
57 // Revision 1.5 2005/07/21 16:48:08 mwatson
58 // Header cleanup.
59 //
60 // Revision 1.4 2005/07/21 16:40:46 jhheo
61 // added STD_BETA_DSD
62 //
63 // Revision 1.3 2005/07/21 16:06:04 jhheo
64 // readDSDStatus/readDSDControl added
65 //
66 // Revision 1.1 2005/07/11 20:02:14 jhheo
67 // initial version for DSD2 for E001
68 //
69 // Revision 1.2 2005/04/27 13:43:19 jhheo
70 // log header cleaned up
71 //
72 // Revision 1.1 2005/04/22 22:10:42 jhheo
73 // initial version for DSD2
74 //
77 #ifndef _DSD_A
78 #define _DSD_A
80 #include <acpbeta.h>
82 #define readDSDChannelConfigurationProgram 0xc200+STD_BETA_DSD,0x0400
83 #define writeDSDChannelConfigurationProgramStereoUnknown 0xca00+STD_BETA_DSD,0x0400
84 #define writeDSDChannelConfigurationProgramSurround2Unknown_0 0xca00+STD_BETA_DSD,0x0401
85 #define writeDSDChannelConfigurationProgramSurround2Unknown_1 0xca00+STD_BETA_DSD,0x0402
87 #define readDSDOperationalMode 0xc200+STD_BETA_DSD,0x0500
88 #define writeDSDOperationalModeDecoding1X 0xca00+STD_BETA_DSD,0x0500
89 #define writeDSDOperationalModeDecoding2X 0xca00+STD_BETA_DSD,0x0501
90 #define writeDSDOperationalModeDecoding4X 0xca00+STD_BETA_DSD,0x0502
91 #define writeDSDOperationalModePASS 0xca00+STD_BETA_DSD,0x0503
93 #define writeDSDOperationalModeDecoding2822To44KHz writeDSDOperationalModeDecoding1X
94 #define writeDSDOperationalModeDecoding2822To88KHz writeDSDOperationalModeDecoding2X
95 #define writeDSDOperationalModeDecoding2822To176KHz writeDSDOperationalModeDecoding4X
96 #define writeDSDOperationalModeDecoding5644To44KHz 0xca00+STD_BETA_DSD,0x0504
97 #define writeDSDOperationalModeDecoding5644To88KHz 0xca00+STD_BETA_DSD,0x0505
98 #define writeDSDOperationalModeDecoding5644To176KHz 0xca00+STD_BETA_DSD,0x0506
101 #define readDSDModulationPercent 0xc200+STD_BETA_DSD,0x0600
102 #define writeDSDModulationPercent50 0xca00+STD_BETA_DSD,0x0600
103 #define writeDSDModulationPercent100 0xca00+STD_BETA_DSD,0x0601
105 #define readDSDSilenceStatus 0xc200+STD_BETA_DSD,0x0700
107 #define readDSDMute 0xc200+STD_BETA_DSD,0x0800
108 #define writeDSDMuteOff 0xca00+STD_BETA_DSD,0x0800
109 #define writeDSDMuteOn 0xca00+STD_BETA_DSD,0x0801
111 #define readDSDDelayBypass 0xc200+STD_BETA_DSD,0x0900
112 #define writeDSDDelayBypassEnable 0xca00+STD_BETA_DSD,0x0900
113 #define writeDSDDelayBypassDisable 0xca00+STD_BETA_DSD,0x0901
115 #define readDSDDelayUse readDSDDelayBypass
116 #define writeDSDDelayUseDisable writeDSDDelayBypassEnable
117 #define writeDSDDelayUseEnable writeDSDDelayBypassDisable
119 #define readDSDDelayLeft 0xc300+STD_BETA_DSD,0x000a
120 #define writeDSDDelayLeftN(NN) 0xcb00+STD_BETA_DSD,0x000a,NN
121 #define readDSDDelayRght 0xc300+STD_BETA_DSD,0x000c
122 #define writeDSDDelayRghtN(NN) 0xcb00+STD_BETA_DSD,0x000c,NN
123 #define readDSDDelayLsur 0xc300+STD_BETA_DSD,0x000e
124 #define writeDSDDelayLsurN(NN) 0xcb00+STD_BETA_DSD,0x000e,NN
125 #define readDSDDelayRsur 0xc300+STD_BETA_DSD,0x0010
126 #define writeDSDDelayRsurN(NN) 0xcb00+STD_BETA_DSD,0x0010,NN
127 #define readDSDDelayCntr 0xc300+STD_BETA_DSD,0x0012
128 #define writeDSDDelayCntrN(NN) 0xcb00+STD_BETA_DSD,0x0012,NN
129 #define readDSDDelaySubw 0xc300+STD_BETA_DSD,0x0014
130 #define writeDSDDelaySubwN(NN) 0xcb00+STD_BETA_DSD,0x0014,NN
132 #define readDSDDelayUnit 0xc200+STD_BETA_DSD,0x1600
133 #define writeDSDDelayUnitTimeSamples 0xca00+STD_BETA_DSD,0x1600
134 #define writeDSDDelayUnitTimeMilliseconds 0xca00+STD_BETA_DSD,0x1601
136 #define readDSDStatus 0xc508,STD_BETA_DSD
137 #define readDSDControl 0xc508,STD_BETA_DSD
139 #endif /* _DSD_A */