/* Copyright (c) 2016, Texas Instruments Incorporated - http://www.ti.com/ All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* * ======== config.bld ======== * */ var Build = xdc.useModule('xdc.bld.BuildEnvironment'); /* Memory Map for ti.platforms.evmTCI66AK2G02 * * Address Size Comment * ------------------------------------------------------------- * 0C00_0000 0008_0000 ( 512 KB) SR_MSMC (ipc:data) * 0C08_0000 0004_0000 ( 256 KB) HOST_MSMC (code, data) * 0C0C_0000 0004_0000 ( 256 KB) CORE_MSMC (code, data) * 8000_0000 0020_0000 ( 2 MB) SR_0 (ipc) * 8020_0000 0080_0000 ( 8 MB) SR_DDR3 (ipc:data) * 80A0_0000 0060_0000 ( 6 MB) COMMON_DDR3 (data) * 8100_0000 0100_0000 ( 16 MB) COMMON2_DDR3(code, data) // aligned to MAR memory region * 8200_0000 0320_0000 ( 50 MB) HOST_DDR3 (code, data) * 8520_0000 0400_0000 ( 64 MB) CORE0_DDR3 (code, data) * 8920_0000 76E0_0000 (1902 MB) DDR3 (code, data) */ var SR_MSMC = { name: "SR_MSMC", space: "data", access: "RW", base: 0x0C000000, len: 0x00080000, comment: "SR MSMC Memory (512 KB)" }; var SR_0 = { name: "SR_0", space: "data", access: "RW", base: 0x80000000, len: 0x00200000, comment: "SR#0 Memory" }; var SR_DDR3 = { name: "SR_DDR3", space: "data", access: "RW", base: 0x80200000, len: 0x00800000, comment: "SR DDR3 Memory" }; var COMMON_DDR3 = { name: "COMMON_DDR3", space: "data", access: "RW", base: 0x80A00000, len: 0x00600000, comment: "COMMON DDR3 Memory" }; var COMMON2_DDR3 = { // Common Structure for shared data, Non cacheable name: "COMMON2_DDR3", space: "data", access: "RW", base: 0x81000000, len: 0x01000000, comment: "COMMON 2 PP DDR3 Memory" }; var DDR3 = { name: "DDR3", space: "code/data", access: "RW", base: 0x89200000, len: 0x76E00000, comment: "DDR3 Memory" }; // This is ARM Build.platformTable["ti.platforms.evmTCI66AK2G02:host"] = { customMemoryMap: [ ["SR_MSMC", SR_MSMC], [ "HOST_MSMC", { name: "HOST_MSMC", space: "code/data", access: "RWX", base: 0x0C080000, len: 0x00040000, comment: "HOST MSMC SRAM" }], ["SR_0", SR_0], ["SR_DDR3", SR_DDR3], ["COMMON_DDR3", COMMON_DDR3], ["COMMON2_DDR3", COMMON2_DDR3], [ "HOST_DDR3", { name: "HOST_DDR3", space: "code/data", access: "RWX", base: 0x82000000, len: 0x03200000, comment: "HOST DDR3" }], ["DDR3", DDR3] ], codeMemory: "HOST_DDR3", dataMemory: "HOST_DDR3", stackMemory: "HOST_DDR3" }; // This is DSP Build.platformTable["ti.platforms.evmTCI66AK2G02:core0"] = { customMemoryMap: [ ["L2SRAM", { comment: "1MB L2 SRAM/CACHE", name: "L2SRAM", base: 0x00800000, len: 0x00100000, space: "code/data", access: "RWX" }], ["L1PSRAM", { comment: "32KB RAM/CACHE L1 program memory", name: "L1PSRAM", base: 0x00E00000, len: 0x00008000, space: "code", access: "RWX" }], ["L1DSRAM", { comment: "32KB RAM/CACHE L1 data memory", name: "L1DSRAM", base: 0x00F00000, len: 0x00008000, space: "data", access: "RW" }], ["SR_MSMC", SR_MSMC], [ "CORE0_MSMC", { name: "CORE0_MSMC", space: "code/data", access: "RWX", base: 0x0C0C0000, len: 0x00040000, comment: "CORE0 MSMC SRAM" }], ["SR_0", SR_0], ["SR_DDR3", SR_DDR3], ["COMMON_DDR3", COMMON_DDR3], ["COMMON2_DDR3", COMMON2_DDR3], [ "CORE0_DDR3", { name: "CORE0_DDR3", space: "code/data", access: "RWX", base: 0x85200000, len: 0x04000000, comment: "CORE0 DDR3" }], ["DDR3", DDR3] ], codeMemory: "CORE0_DDR3", dataMemory: "CORE0_DDR3", stackMemory: "CORE0_DDR3", l1DMode: "32k", l1PMode: "32k", l2Mode: "256k" };