PASDK-376:Clean up ARM linker command file

[processor-sdk/performance-audio-sr.git] / pasdk / shared / config.bld

diff --git a/pasdk/shared/config.bld b/pasdk/shared/config.bld
index f61e1b65f136da0a9b661238545ce7b876646b18..90c148118f777f9fed027798c69ed52cdec42c47 100644 (file)
--- a/pasdk/shared/config.bld
+++ b/pasdk/shared/config.bld
@@ -1,5 +1,5 @@
 /*
-Copyright (c) 2016, Texas Instruments Incorporated - http://www.ti.com/
+Copyright (c) 2017, Texas Instruments Incorporated - http://www.ti.com/
 All rights reserved.
 
 * Redistribution and use in source and binary forms, with or without 
@@ -45,14 +45,14 @@ var Build = xdc.useModule('xdc.bld.BuildEnvironment');
  *  -------------------------------------------------------------
  *    0C00_0000   0008_0000  ( 512 KB)  SR_MSMC     (ipc:data)
  *    0C08_0000   0004_0000  ( 256 KB)  HOST_MSMC   (code, data)
- *    0C0C_0000   0004_0000  ( 256 KB)  CORE_MSMC   (code, data)
+ *    0C0C_0000   0004_0000  ( 256 KB)  CORE0_MSMC  (code, data)
  *    8000_0000   0020_0000  (   2 MB)  SR_0        (ipc)
- *    8020_0000   0080_0000  (   8 MB)  SR_DDR3     (ipc:data)
- *    80A0_0000   0060_0000  (   6 MB)  COMMON_DDR3 (data)
+ *    8020_0000   0060_0000  (   6 MB)  COMMON_DDR3 (data)
  *    8100_0000   0100_0000  (  16 MB)  COMMON2_DDR3(code, data)      // aligned to MAR memory region  
- *    8200_0000   0320_0000  (  50 MB)  HOST_DDR3   (code, data)
- *    8520_0000   0400_0000  (  64 MB)  CORE0_DDR3  (code, data)
- *    8920_0000   76E0_0000  (1902 MB)  DDR3        (code, data)
+ *    8200_0000   0100_0000  (  16 MB)  SR_DDR3     (ipc:data)
+ *    8300_0000   0300_0000  (  48 MB)  HOST_DDR3   (code, data)
+ *    8600_0000   0400_0000  (  64 MB)  CORE0_DDR3  (code, data)
+ *    8A00_0000   7600_0000  (1888 MB)  DDR3        (code, data)
  */
 
 var SR_MSMC = {
@@ -69,13 +69,13 @@ var SR_0 = {
 
 var SR_DDR3 = {
         name: "SR_DDR3", space: "data", access: "RW",
-        base: 0x80200000, len: 0x00800000,
+        base: 0x82000000, len: 0x01000000,
         comment: "SR DDR3 Memory"
     };
 
 var COMMON_DDR3 = {
         name: "COMMON_DDR3", space: "data", access: "RW",
-        base: 0x80A00000, len: 0x00600000,
+        base: 0x80200000, len: 0x00600000,
         comment: "COMMON DDR3 Memory"
     };
     
@@ -87,7 +87,7 @@ var COMMON2_DDR3 = {  // Common Structure for shared data, Non cacheable
 
 var DDR3 = {
         name: "DDR3", space: "code/data", access: "RW",
-        base: 0x89200000, len: 0x76E00000,
+        base: 0x8A000000, len: 0x76000000,
         comment: "DDR3 Memory"
     };
 
@@ -112,7 +112,7 @@ Build.platformTable["ti.platforms.evmTCI66AK2G02:host"] = {
         
         [ "HOST_DDR3",  {
             name: "HOST_DDR3", space: "code/data", access: "RWX",
-            base: 0x82000000, len: 0x03200000,
+            base: 0x83000000, len: 0x03000000,
             comment: "HOST DDR3"
         }], 
         
@@ -172,7 +172,7 @@ Build.platformTable["ti.platforms.evmTCI66AK2G02:core0"] = {
         
         [ "CORE0_DDR3",  {
             name: "CORE0_DDR3", space: "code/data", access: "RWX",
-            base: 0x85200000, len: 0x04000000,
+            base: 0x86000000, len: 0x04000000,
             comment: "CORE0 DDR3"
         }],