Merge branch 'dev_pasdk_pp_pasdk69ArmDspCom' into 'dev_pasdk_pp_pasdk114matthdissue'

[processor-sdk/performance-audio-sr.git] / pasdk / test_arm / application / app.cfg

diff --git a/pasdk/test_arm/application/app.cfg b/pasdk/test_arm/application/app.cfg
index 6ec83cee94f0e9947454624704cb0c971bfe0232..3a989b1f0bfe044b801f014c015bd1f5c117ed91 100644 (file)
--- a/pasdk/test_arm/application/app.cfg
+++ b/pasdk/test_arm/application/app.cfg
@@ -76,6 +76,7 @@ xdc.useModule('ti.sdo.utils.MultiProc');
 xdc.global.SR0_cacheEnable = true;
 xdc.global.SrMsmcMem_cacheEnable = true;
 xdc.global.SrDDr3Mem_cacheEnable = true;
+xdc.global.SrDDr3_2Mem_cacheEnable = false;
 xdc.global.procName = "HOST";
 var ipc_cfg = xdc.loadCapsule("C:/ti/processor_audio_sdk_1_00_00_01/pasdk/shared/ipc.cfg.xs");
 
@@ -144,6 +145,40 @@ BIOS.heapSize = 0x2000; // from pa.cfg
 BIOS.heapSection = ".systemHeap";
 Program.sectMap[".systemHeap"] = "HOST_DDR3";
 
+if (xdc.global.SrDDr3_2Mem_cacheEnable == false)        
+{
+       // Disable cache on ARM for the shared memory region
+       var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
+       
+       // descriptor attribute structure
+       var attrs = new Mmu.DescriptorAttrs();
+       
+       // Note: If running in SMP mode, all page table entries for memory
+       //       shared between the SMP cores should mark the memory as
+       //       inner-shareable. This is to ensure that the cached copy of
+       //       the memory region is kept coherent accross cores.
+       
+       Mmu.initDescAttrsMeta(attrs);
+       attrs.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
+       attrs.shareable = 2; //3;                 // 2 - outer-sharerable
+       attrs.attrIndx = 0;//2;                   // MAIR0 Byte2 describes
+                                                 // memory attributes for
+                                                 // this level2 entry
+       
+       // write memory region attribute in mairRegAttr[2] i.e. MAIR0 Reg Byte2
+       Mmu.setMAIRMeta(0, 0x44);              // Mark mem regions as non-cacheable
+       
+       /* Get a handle to the C64P Target */
+       // TODO: remove hardcoded address and get correct values from .bld
+       var COMMON2_DDR3_base = 0x81000000;
+       var COMMON2_DDR3_end = 0x81000000 + 0x01000000;
+       // Set the descriptor for each entry in the address range
+       for (var i=COMMON2_DDR3_base; i < COMMON2_DDR3_end; i = i + 0x00200000) {
+           // Each 'BLOCK' descriptor entry spans a 2MB address range
+           Mmu.setSecondLevelDescMeta(i, i, attrs);
+       }
+}
+
 /*
  * Build a custom SYS/BIOS library from sources.
  */