index 964c4c7f018a92064eb51283d0b80a29b1b3a313..cd64a7b6b256761ab6dde7beea73f1e52a71d25d 100644 (file)
/*
-Copyright (c) 2016, Texas Instruments Incorporated - http://www.ti.com/
+Copyright (c) 2017, Texas Instruments Incorporated - http://www.ti.com/
All rights reserved.
* Redistribution and use in source and binary forms, with or without
var Text = xdc.useModule('xdc.runtime.Text');
var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var GateAll = xdc.useModule('ti.sysbios.gates.GateAll'); // Added for PFP
var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
var Timer = xdc.useModule('ti.sysbios.hal.Timer');
var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+var Swi = xdc.useModule('ti.sysbios.knl.Swi'); // Added for PFP, no SWIs on ARM
var Task = xdc.useModule('ti.sysbios.knl.Task');
var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
xdc.global.SR0_cacheEnable = true;
xdc.global.SrMsmcMem_cacheEnable = true;
xdc.global.SrDDr3Mem_cacheEnable = true;
+xdc.global.SrDDr3_2Mem_cacheEnable = false;
xdc.global.procName = "HOST";
-var ipc_cfg = xdc.loadCapsule("C:/ti/processor_audio_sdk_1_00_00_00/pasdk/shared/ipc.cfg.xs");
+var ipc_cfg = xdc.loadCapsule("C:/ti/processor_audio_sdk_1_00_00_04/pasdk/shared/ipc.cfg.xs");
/* select ipc libraries */
var Build = xdc.useModule('ti.sdo.ipc.Build');
BIOS.heapSection = ".systemHeap";
Program.sectMap[".systemHeap"] = "HOST_DDR3";
+if (xdc.global.SrDDr3_2Mem_cacheEnable == false)
+{
+ // Disable cache on ARM for the shared memory region
+ var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
+
+ // descriptor attribute structure
+ var attrs = new Mmu.DescriptorAttrs();
+
+ // Note: If running in SMP mode, all page table entries for memory
+ // shared between the SMP cores should mark the memory as
+ // inner-shareable. This is to ensure that the cached copy of
+ // the memory region is kept coherent accross cores.
+
+ Mmu.initDescAttrsMeta(attrs);
+ attrs.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor
+ attrs.shareable = 2; //3; // 2 - outer-sharerable
+ attrs.attrIndx = 0;//2; // MAIR0 Byte2 describes
+ // memory attributes for
+ // this level2 entry
+
+ // write memory region attribute in mairRegAttr[2] i.e. MAIR0 Reg Byte2
+ Mmu.setMAIRMeta(0, 0x44); // Mark mem regions as non-cacheable
+
+ /* Get a handle to the C64P Target */
+ // TODO: remove hardcoded address and get correct values from .bld
+ var COMMON2_DDR3_base = 0x81000000;
+ var COMMON2_DDR3_end = 0x81000000 + 0x01000000;
+ // Set the descriptor for each entry in the address range
+ for (var i=COMMON2_DDR3_base; i < COMMON2_DDR3_end; i = i + 0x00200000) {
+ // Each 'BLOCK' descriptor entry spans a 2MB address range
+ Mmu.setSecondLevelDescMeta(i, i, attrs);
+ }
+}
+
/*
* Build a custom SYS/BIOS library from sources.
*/
/* Add Audio Stream Decode Processing (ASDP) task */
var task0Params = new Task.Params();
task0Params.instance.name = "TaskAsdp";
-task0Params.stackSize = 0x4000;
+task0Params.stackSize = (0x8000+0x1000);
task0Params.stackSection = ".far:taskStackSectionAsdp";
//task0Params.arg0 = 0;
task0Params.arg0 = $externPtr("asdp_params_PA" + topo);
/* Add MSMC SRAM heap */ // formerly L3RAM
var heapMem1Params = new HeapMem.Params();
heapMem1Params.instance.name = "heapMemMsmcSram";
-heapMem1Params.size = 224*1024; //128*1024
+heapMem1Params.size = (224-4)*1024; //128*1024
heapMem1Params.sectionName = ".msmcSramHeap";
Program.global.heapMemMsmcSram = HeapMem.create(heapMem1Params);
Program.sectMap[".msmcSramHeap"] = "HOST_MSMC";
/* Add DDR3 heap */ // formerly SDRAM
var heapMem2Params = new HeapMem.Params();
heapMem2Params.instance.name = "heapMemDdr3";
-heapMem2Params.size = 4350528;
+heapMem2Params.size = 5350528+ (3*1024*1024); // Added 3 MB for DTS decoder;//4350528;
heapMem2Params.sectionName = ".ddr3Heap";
Program.global.heapMemDdr3 = HeapMem.create(heapMem2Params);
Program.sectMap[".ddr3Heap"] = "HOST_DDR3";
//Program.sectMap[".globalSectionPafAstConfig"] = "COMMON_DDR3";
//Program.sectMap[".globalSectionAcpStdBetaTable"] = "COMMON_DDR3";
+
+/* Define HWI Hook Set for PFP */
+Hwi.addHookSet({
+ registerFxn: '&pfpHwiRegister',
+ createFxn: '&pfpHwiCreate',
+ beginFxn: '&pfpHwiBegin',
+ endFxn: '&pfpHwiEnd',
+ deleteFxn: null,
+});
+
+/* Define SWI Hook Set for PFP */
+Swi.addHookSet({
+ registerFxn: '&pfpSwiRegister', // need this for Id for Hook context
+ createFxn: '&pfpSwiCreate', // malloc context storage space
+ readyFxn: '&pfpSwiReady',
+ beginFxn: '&pfpSwiBegin',
+ endFxn: '&pfpSwiEnd',
+ deleteFxn: null,
+});
+
+/* Define Task Hook Set for PFP */
+Task.addHookSet({
+ registerFxn: '&pfpTaskRegister',
+ createFxn: '&pfpTaskCreate',
+ readyFxn: '&pfpTaskReady',
+ switchFxn: '&pfpTaskSwitch',
+ exitFxn: null,
+ deleteFxn: null,
+});
+
+/* Added for PFP, not necessary */
+Hwi.common$.namedInstance=true;
+Swi.common$.namedInstance=true;
+Task.common$.namedInstance=true;