index cccf5ad36fee14e5381c6ff2348dd0a428889ea7..1efc084bbeeb002041b009a1a2a62fa2911f085e 100644 (file)
/*
-Copyright (c) 2016, Texas Instruments Incorporated - http://www.ti.com/
+Copyright (c) 2017, Texas Instruments Incorporated - http://www.ti.com/
All rights reserved.
* Redistribution and use in source and binary forms, with or without
var System = xdc.useModule('xdc.runtime.System');
var Text = xdc.useModule('xdc.runtime.Text');
+
var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var GateAll = xdc.useModule('ti.sysbios.gates.GateAll'); // Added for PFP
var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
var Cache = xdc.useModule('ti.sysbios.hal.Cache');
-var Cachec66 = xdc.useModule('ti.sysbios.family.c66.Cache');
+var Cachec66 = xdc.useModule('ti.sysbios.family.c66.Cache');
var Timer = xdc.useModule('ti.sysbios.hal.Timer');
var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var Idle = xdc.useModule('ti.sysbios.knl.Idle');
var Queue = xdc.useModule('ti.sysbios.knl.Queue');
var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Swi = xdc.useModule('ti.sysbios.knl.Swi'); // Added for PFP
var Task = xdc.useModule('ti.sysbios.knl.Task');
var Load = xdc.useModule('ti.sysbios.utils.Load');
xdc.global.SrDDr3Mem_cacheEnable = true;
xdc.global.SrDDr3_2Mem_cacheEnable = false;
xdc.global.procName = "CORE0";
-var ipc_cfg = xdc.loadCapsule("C:/ti/processor_audio_sdk_1_00_00_00/pasdk/shared/ipc.cfg.xs");
+/* var ipc_cfg = xdc.loadCapsule("C:/ti/processor_sdk_audio_1_01_00_01/pasdk/shared/ipc.cfg.xs"); */
+var ipc_cfg = xdc.loadCapsule("../../shared/ipc.cfg.xs");
+
/* select ipc libraries */
var Build = xdc.useModule('ti.sdo.ipc.Build');
/*
* Build a custom SYS/BIOS library from sources.
*/
-BIOS.libType = (RB ? BIOS.LibType_NonInstrumented : BIOS.LibType_Instrumented);
-// BIOS.libType = BIOS.LibType_Custom;
-// BIOS.libType = BIOS.LibType_Debug;
-
+
+var HsDevBuild = environment["HsDevBuild"];
+var hsDevBuild = (HsDevBuild == "1" ? true : false);
+if (HsDevBuild == true)
+{
+ /* HS device build */
+ /* Added per recommendation from CATAPPS-171 */
+ BIOS.useSK = true;
+ BIOS.setupSecureContext = true;
+ BIOS.libType = BIOS.LibType_Custom;
+}
+else
+{
+ /* GP device build */
+ BIOS.libType = (RB ? BIOS.LibType_NonInstrumented : BIOS.LibType_Instrumented);
+ //BIOS.libType = BIOS.LibType_Custom;
+ //BIOS.libType = BIOS.LibType_Debug;
+}
+
/* System stack size (used by ISRs and Swis) */
Program.stack = 0x2000;
Program.sectMap[".stack"] = "L2SRAM"
LoggingSetup.mainLoggerSize = 327680; //81960;
//LoggingSetup.memorySectionName = "CORE0_DDR3"; //"CORE0_MSMC";
-/* Configure Load Logging */ // FL: doesn't work
-//Load.taskEnabled = true;
-//Load.hwiEnabled = true;
-//Load.common$.diags_USER4 = Diags.ALWAYS_ON;
+// FL: CPU load logging via UIA doesn't work.
+// Below settings work for target-side load computation (no UIA) when LoggingSetup.loadLogging set to false, but not true.
+// Load.common$.diags_USER4 set to default or Diags.ALWAYS_ON makes no difference.
+/* Configure Load Logging */
+Load.updateInIdle = true; // default=true
+Load.windowInMs = 5.33; // 48KHz 256 @ 5.33ms // in msec., default=500
+Load.taskEnabled = true; // default=true
+Load.swiEnabled = false; // default=true
+Load.hwiEnabled = false; // default=true
+//Load.common$.diags_USER4 = Diags.ALWAYS_ON; // default=Diags.RUNTIME_ON
//Task.common$.diags_USER1 = Diags.ALWAYS_ON;
Task.common$.diags_INFO = Diags.ALWAYS_ON;
var ProjName = environment["ProjName"];
var topo = ProjName.replace( /pa_([a-z])[0-9]+_.*/, "$1");
-var AudioClockSim = environment["AudioClockSim"];
-var acSimBuild = (AudioClockSim == "1" ? true : false);
-var RxAlphaSim = environment["RxAlphaSim"];
-var rxAlphaSimBuild = (RxAlphaSim == "1" ? true : false);
-if (acSimBuild == false)
-{
- var drv = xdc.loadPackage('ti.sdo.edma3.drv');
- var rm = xdc.loadPackage ("ti.sdo.edma3.rm");
- var Edma = xdc.loadPackage ("ti.sdo.edma3.drv.sample");
- var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
-}
-else
-{
- //
- // SIO simulation
- //
-
- /* Add timer to simulate Rx audio DMA */
- var timer0Params = new Timer.Params();
- timer0Params.instance.name = "timerRxAudio";
- timer0Params.period = 5330;
- timer0Params.startMode = xdc.module("ti.sysbios.interfaces.ITimer").StartMode_USER;
- Program.global.timerRxAudio = Timer.create(1, null, timer0Params);
-
- /* Add timer to simulate Tx audio DMA */
- var timer1Params = new Timer.Params();
- timer1Params.instance.name = "timerTxAudio";
- timer1Params.startMode = xdc.module("ti.sysbios.interfaces.ITimer").StartMode_USER;
- timer1Params.period = 5330;
- Program.global.timerTxAudio = Timer.create(2, null, timer1Params);
-
- /* Add semaphore for Rx audio DMA */
- var semaphore0Params = new Semaphore.Params();
- semaphore0Params.instance.name = "semaphoreRxAudio";
- Program.global.semaphoreRxAudio = Semaphore.create(null, semaphore0Params);
-
- /* Add semaphore for Tx audio DMA */
- var semaphore1Params = new Semaphore.Params();
- semaphore1Params.instance.name = "semaphoreTxAudio";
- Program.global.semaphoreTxAudio = Semaphore.create(null, semaphore1Params);
-}
+var drv = xdc.loadPackage('ti.sdo.edma3.drv');
+var rm = xdc.loadPackage ("ti.sdo.edma3.rm");
+var Edma = xdc.loadPackage ("ti.sdo.edma3.drv.sample");
+var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
-if (rxAlphaSimBuild == false)
-{
- var devType = "k2g"
-
- var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
-
- /* Load the OSAL package */
- var osType = "tirtos";
- var Osal = xdc.useModule('ti.osal.Settings');
- Osal.osType = osType;
- Osal.socType = devType;
-
- /* Load the uart package */
- var Uart = xdc.loadPackage('ti.drv.uart');
- Uart.Settings.enableProfiling = false;
- Uart.Settings.socType = devType;
- Uart.Settings.useDma = "true";
-
- /* Load the spi package */
- var Spi = xdc.loadPackage('ti.drv.spi');
- Spi.Settings.enableProfiling = false;
- Spi.Settings.socType = devType;
-
- /* Load the i2c package */
- var I2c = xdc.loadPackage('ti.drv.i2c');
- I2c.Settings.enableProfiling = false;
- I2c.Settings.socType = devType;
-
- /* Load and use the CSL packages */
- var Csl = xdc.useModule('ti.csl.Settings');
- Csl.deviceType = devType;
-}
-else
-{
- //
- // Rx alpha commands simulation
- //
-
- /* Add clock for Rx alpha commands DMA */
- var clock0Params = new Clock.Params();
- clock0Params.instance.name = "clockRxAlpha";
- Program.global.clockRxAlpha = Clock.create("&clockRxAlphaFxn", 0, clock0Params);
-
- /* Add semaphore for Rx alpha commands DMA */
- var semaphore2Params = new Semaphore.Params();
- semaphore2Params.instance.name = "semaphoreRxAlpha";
- Program.global.semaphoreRxAlpha = Semaphore.create(null, semaphore2Params);
-}
+var devType = "k2g"
+
+var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
+
+/* Load the OSAL package */
+var osType = "tirtos";
+var Osal = xdc.useModule('ti.osal.Settings');
+Osal.osType = osType;
+Osal.socType = devType;
+
+/* Load the uart package */
+var Uart = xdc.loadPackage('ti.drv.uart');
+Uart.Settings.enableProfiling = false;
+Uart.Settings.socType = devType;
+Uart.Settings.useDma = "true";
+
+/* Load the spi package */
+var Spi = xdc.loadPackage('ti.drv.spi');
+Spi.Settings.enableProfiling = false;
+Spi.Settings.socType = devType;
+
+/* Load the i2c package */
+var I2c = xdc.loadPackage('ti.drv.i2c');
+I2c.Settings.enableProfiling = false;
+I2c.Settings.socType = devType;
+
+/* Load and use the CSL packages */
+var Csl = xdc.useModule('ti.csl.Settings');
+Csl.deviceType = devType;
/* Set default stack size for tasks */
Task.defaultStackSize = 2048;
task1Params.arg0 = 0;
task1Params.priority = -1; //2;
Program.global.TaskAip = Task.create("&taskAipFxn", task1Params);
-Program.sectMap[".far:taskStackSectionAip"] = "CORE0_MSMC"; // L3RAM in pa.cfg
+Program.sectMap[".far:taskStackSectionAip"] = "CORE0_DDR3"; // L3RAM in pa.cfg
/* Add Audio Stream Input Processing (ASIP) task */
var task2Params = new Task.Params();
task2Params.arg1 = $externPtr("asip_patchs_PA" + topo);
task2Params.priority = -1; //3;
Program.global.TaskAsip = Task.create("&taskAsipFxn", task2Params);
-Program.sectMap[".far:taskStackSectionAsip"] = "CORE0_MSMC";
+Program.sectMap[".far:taskStackSectionAsip"] = "CORE0_DDR3";
/* Add Audio Stream Output Processing (ASOP) task */
var task3Params = new Task.Params();
task3Params.arg1 = $externPtr("asop_patchs_PA" + topo);
task3Params.priority = -1; //3;
Program.global.TaskAsop = Task.create("&taskAsopFxn", task3Params);
-Program.sectMap[".far:taskStackSectionAsop"] = "CORE0_MSMC";
+Program.sectMap[".far:taskStackSectionAsop"] = "CORE0_DDR3";
/* Add System Initialization task */
var task4Params = new Task.Params();
task4Params.instance.name = "TaskSysInit";
task4Params.stackSize = 0x1000;
task4Params.stackSection = ".far:taskStackSectionSysInit";
-task4Params.priority = 4;
+task4Params.priority = 6; //5;
Program.global.TaskSysInit = Task.create("&taskSysInitFxn", task4Params);
Program.sectMap[".far:taskStackSectionSysInit"] = "CORE0_DDR3";
@@ -363,26 +333,22 @@ Program.global.TaskSystemStream = Task.create("&taskSystemStreamFxn", task5Param
Program.sectMap[".far:taskStackSectionAudioStream"] = "CORE0_DDR3";
/* Add idle functions */
-if (acSimBuild == false)
-{
- Idle.idleFxns[0] = "&SAP_watchDog"; // Idle function for DSP watchdog; formerly DAP_watchDog()
-}
-else
-{
- //
- // SIO simulation
- //
- Idle.idleFxns[0] = "&idleDapWatchDog"; // Idle function for DSP watchdog; formerly DAP_watchDog()
-}
-// Remark: Moved idleAudioStream (idle function) to taskSystemStreamFxn (task)
+// Remark: original idle functions
+//Idle.idleFxns[0] = "&SAP_watchDog"; // Idle function for DSP watchdog; formerly DAP_watchDog()
//Idle.idleFxns[1] = "&idleAudioStream"; // Idle function for audio stream; formerly audioStream1Idle()
//Idle.idleFxns[2] = "&idleNotifyInfoChange"; // Idle function for Notify Information Change (NIC); formerly customSystemStreamIdleNIC()
-Idle.idleFxns[1] = "&idleNotifyInfoChange"; // Idle function for Notify Information Change (NIC); formerly customSystemStreamIdleNIC()
+// Remark: Moved idleAudioStream (idle function) to taskSystemStreamFxn (task)
+//Idle.idleFxns[0] = "&SAP_watchDog"; // Idle function for DSP watchdog; formerly DAP_watchDog()
+//Idle.idleFxns[1] = "&idleNotifyInfoChange"; // Idle function for Notify Information Change (NIC); formerly customSystemStreamIdleNIC()
+//Idle.idleFxns[2] = "&idleDebug" // Idle function for debug code
+// Remark: Removed SAP watch dog
+Idle.idleFxns[0] = "&idleNotifyInfoChange"; // Idle function for Notify Information Change (NIC)
+Idle.idleFxns[1] = "&idleDebug" // Idle function for debug code
/* Add L2 SRAM heap */ // formerly IRAM
var heapMem0Params = new HeapMem.Params();
heapMem0Params.instance.name = "heapMemL2Sram";
-heapMem0Params.size = 256*1024; // 96000; // from pa.cfg
+heapMem0Params.size = 550*1024; // 550 kB temporary setting for OB in L2
heapMem0Params.sectionName = ".l2SramHeap";
Program.global.heapMemL2Sram = HeapMem.create(heapMem0Params);
Program.sectMap[".l2SramHeap"] = "L2SRAM";
heapMem1Params.size = 128*1024;
heapMem1Params.sectionName = ".msmcSramHeap";
Program.global.heapMemMsmcSram = HeapMem.create(heapMem1Params);
-Program.sectMap[".msmcSramHeap"] = "CORE0_MSMC";
+Program.sectMap[".msmcSramHeap"] = "CORE0_DDR3";
/* Add DDR3 heap */ // formerly SDRAM
var heapMem2Params = new HeapMem.Params();
heapMem2Params.instance.name = "heapMemDdr3";
-heapMem2Params.size = 4350528;
+heapMem2Params.size = 4350528 + (3*1024*1024); // Added 3 MB for DTS PARMA
heapMem2Params.sectionName = ".ddr3Heap";
Program.global.heapMemDdr3 = HeapMem.create(heapMem2Params);
Program.sectMap[".ddr3Heap"] = "CORE0_DDR3";
-/* FL: hack for DCS7, dcs7_cfg.c */
+/* For DCS7, dcs7_cfg.c */
Program.global.Heap = Program.global.heapMemDdr3;
-Program.sectMap["platform_lib"] = "L2SRAM";
//Program.sectMap[".stack"] = "L2SRAM";
-if (acSimBuild == false)
-{
- ECM.eventGroupHwiNum[0] = 7;
- ECM.eventGroupHwiNum[1] = 8; // FL: conflict w/ UART LLD (intr-callback)
- ECM.eventGroupHwiNum[2] = 9;
- ECM.eventGroupHwiNum[3] = 10;
- //Clock.tickPeriod = 100; // FL: UART LLD (intr-callback) unresponsive
-}
-else
-{
- ////
- //// For simulation
- //// This doesn't work-- events #34,36 aren't enabled in C66 EVTMASK1
- //
- //// Use EventCombiner module
- //var EventCombiner = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
- //
- //// Plug function and argument for event 31 (timer1) then enable it.
- //EventCombiner.events[34].fxn = '&timerRxFxn';
- //EventCombiner.events[34].arg = 34;
- //EventCombiner.events[34].unmask = true;
- //
- //// Plug function and argument for event 36 (timer2) then enable it.
- //EventCombiner.events[36].fxn = '&timerTxFxn';
- //EventCombiner.events[36].arg = 36;
- //EventCombiner.events[36].unmask = true;
- //
- //// Map event 1 (combine events 32-63) to vector 7
- //EventCombiner.eventGroupHwiNum[1] = 7;
-}
+/* Map C66x INTC Event Combiner EVT 0-3 to HWI numbers */
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8; // FL: conflict w/ UART LLD, intr-callback mode
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+
+/* Define HWI Hook Set for PFP */
+Hwi.addHookSet({
+ registerFxn: '&pfpHwiRegister',
+ createFxn: '&pfpHwiCreate',
+ beginFxn: '&pfpHwiBegin',
+ endFxn: '&pfpHwiEnd',
+ deleteFxn: null,
+});
+
+/* Define SWI Hook Set for PFP */
+Swi.addHookSet({
+ registerFxn: '&pfpSwiRegister', // need this for Id for Hook context
+ createFxn: '&pfpSwiCreate', // malloc context storage space
+ readyFxn: '&pfpSwiReady',
+ beginFxn: '&pfpSwiBegin',
+ endFxn: '&pfpSwiEnd',
+ deleteFxn: null,
+});
+
+/* Define Task Hook Set for PFP */
+Task.addHookSet({
+ registerFxn: '&pfpTaskRegister',
+ createFxn: '&pfpTaskCreate',
+ readyFxn: '&pfpTaskReady',
+ switchFxn: '&pfpTaskSwitch',
+ exitFxn: null,
+ deleteFxn: null,
+});
+
+/* Added for PFP, not necessary */
+Hwi.common$.namedInstance=true;
+Swi.common$.namedInstance=true;
+Task.common$.namedInstance=true;