[processor-sdk/performance-audio-sr.git] / pasdk / test_dsp / application / itopo / evmk2g / mcasp_cfg.c
diff --git a/pasdk/test_dsp/application/itopo/evmk2g/mcasp_cfg.c b/pasdk/test_dsp/application/itopo/evmk2g/mcasp_cfg.c
index c6dba5f10de5b49ff26a3df49eb7988d269aa5f2..ac16b5adfea1fc65b158b96dc24dcc9e25919a87 100644 (file)
extern void asopMcaspCallback(void* arg, MCASP_Packet *mcasp_packet);
#endif
-/* McASP HW setup that is common for receive and transmit. It is the same for
- * all of 3 McASP ports. */
-Mcasp_HwSetupGbl mcaspGblSetup = {
- (Uint32)0x0, /* pfunc */
- (Uint32)0x2000001, /* pdir */
- (Uint32)0x0, /* ctl */
- (Uint32)0x0, /* ditCtl */
- (Uint32)0x0, /* dlbMode */
- (Uint32)0x2, /* amute */
- {
- (Uint32)0x0, /* [0] */
- (Uint32)0x0, /* [1] */
- (Uint32)0x0, /* [2] */
- (Uint32)0x0, /* [3] */
- (Uint32)0x0, /* [4] */
- (Uint32)0x0, /* [5] */
- (Uint32)0x0, /* [6] */
- (Uint32)0x0, /* [7] */
- (Uint32)0x0, /* [8] */
- (Uint32)0x0, /* [9] */
- (Uint32)0x0, /* [10] */
- (Uint32)0x0, /* [11] */
- (Uint32)0x0, /* [12] */
- (Uint32)0x0, /* [13] */
- (Uint32)0x0, /* [14] */
- (Uint32)0x0, /* [15] */
- } /* serSetup */
-};
/* McASP HW setup for receive (ADC) */
Mcasp_HwSetupData mcaspRcvSetupADC = {
/* .rmask = */ 0xFFFFFFFF, /* 16 bits are to be used */
- /* .rfmt = */ 0x000180F2, /*
+ /* .rfmt = */ 0x0001C0F0, /*
* 0 bit delay from framesync
* MSB first
* No extra bit padding
/* .rstat = */ 0x000001FF, /* reset any existing status bits */
/* .revtctl = */ 0x00000000, /* DMA request is enabled */
{
- /* .aclkrctl = */ 0x000000A7,
- /* .ahclkrctl = */ 0x0000C000,
+ /* .aclkrctl = */ 0x000000A7, // Receiver samples data on the rising edge of the serial clock
+ // Internal receive clock source from output of programmable bit clock divider
+ // Receive bit clock divide ratio = 8
+ /* .ahclkrctl = */ 0x00008000, // Internal receive high-frequency clock source from output of programmable high clock divider.
+ // Falling edge. AHCLKR is inverted before programmable bit clock divider.
/* .rclkchk = */ 0x00000000
}
};
MCASP_DIR_RSTAT, /* .rstat: 0x000001FF */
MCASP_DIR_REVTCTL, /* .revtctl */
{
- MCASP_DIR_ACLKRCTL, /* .aclkrctl: 0x00000080 */
+ MCASP_DIR_ACLKRCTL, /* .aclkrctl: 0x00000080 */ // Receiver samples data on the rising edge of the serial clock
+ // External receive clock source from ACLKR pin.
+ // Receive bit clock divide ratio = 1
MCASP_DIR_AHCLKRCTL, /* .ahclkrctl: 0x00000000 */
MCASP_DIR_RCLKCHK /* .rclkchk: 0x00000000 */
}
/* .xstat = */ 0x000001FF, /* reset any existing status bits */
/* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */
{
- /* .aclkxctl = */ 0X000000E1,
- /* .ahclkxctl = */ 0x00004000 ,
+// /* .aclkxctl = */ 0X000000E1, // Transmit bit clock divide ratio = 2
+ /* .aclkxctl = */ 0X000000E7, // Transmit bit clock divide ratio = 8
+ /* .ahclkxctl = */ 0x00004000,
/* .xclkchk = */ 0x00000000
},
};
/* McASP HW setup for transmit (DAC slave) */
Mcasp_HwSetupData mcaspXmtSetupDACSlave = {
/* .xmask = */ 0xFFFFFFFF, /* 16 bits are to be used */
- /* .xfmt = */ 0x000180F6, /*
+ /* .xfmt = */ 0x000180F0, /*
* 0 bit delay from framesync
* MSB first
* No extra bit padding
* Reads from DMA port
* NO rotation
*/
- /* .afsxctl = */ 0x00000112, /* I2S mode - 2 slot TDM
+ /* .afsxctl = */ 0x00000113, /* I2S mode - 2 slot TDM
* Frame sync is one word
* Rising edge is start of frame
* Internally generated frame sync
mcaspRxParams.mcaspHwSetup.tx.clk.clkSetupClk = 0x63; // Asynchronous. Separate clock and frame sync used by transmit and receive sections.
#ifndef INPUT_SPDIF
- mcaspRxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Special case, since for HDMI input - mcasp0 is both Rx & Tx
- mcaspRxParams.mcaspHwSetup.glb.amute = 0x2; // this to ensure one doesn't overwrite the other (rx/tx)
- mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
- mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
+ mcaspRxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Special case, since for HDMI input - mcasp0 is both Rx & Tx
+ mcaspRxParams.mcaspHwSetup.glb.amute = 0x2; // this to ensure one doesn't overwrite the other (rx/tx)
+ mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
+ mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
#else
- mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
- mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
+ mcaspTxParams.mcaspHwSetup.glb.pdir |= 0x2000000; //Set Amute pin as output for Tx channel
+ mcaspTxParams.mcaspHwSetup.glb.amute = 0x2;
#endif
/* Set the HW interrupt number */
/** McASP LLD configuration parameters for all input and output interfaces */
mcaspLLDconfig LLDconfigRxDIR = // for SAP_D10_RX_DIR
{
- &mcaspGblSetup,
&mcaspRcvSetupDIR,
&mcaspRxChanParamDIR,
0x23,
- 0x23,
+ 0x63, // Asynchronous. Separate clock and frame sync used by transmit and receive sections.
+ 0x0,
+ 0x2,
CSL_MCASP_2,
MCASP_INPUT,
asipMcaspCallback,
mcaspLLDconfig LLDconfigRxADC = // for SAP_D10_RX_ADC_44100HZ, SAP_D10_RX_ADC_88200HZ
{
- &mcaspGblSetup,
&mcaspRcvSetupADC,
&mcaspRxChanParamADC,
0x23,
- 0x23,
+ 0x63,
+ 0x0,
+ 0x2,
CSL_MCASP_1,
MCASP_INPUT,
asipMcaspCallback,
mcaspLLDconfig LLDconfigRxADC6ch = // for SAP_D10_RX_ADC_6CH_44100HZ, SAP_D10_RX_ADC_6CH_88200HZ
{
- &mcaspGblSetup,
&mcaspRcvSetupADC,
&mcaspRxChanParamADC6ch,
0x23,
- 0x23,
+ 0x63,
+ 0x0,
+ 0x2,
CSL_MCASP_1,
MCASP_INPUT,
asipMcaspCallback,
mcaspLLDconfig LLDconfigRxADCStereo = // for SAP_D10_RX_ADC_STEREO_44100HZ, SAP_D10_RX_ADC_STEREO_88200HZ
{
- &mcaspGblSetup,
&mcaspRcvSetupADC,
&mcaspRxChanParamADCStereo,
0x23,
- 0x23,
+ 0x63,
+ 0x0,
+ 0x2,
CSL_MCASP_1,
MCASP_INPUT,
asipMcaspCallback,
mcaspLLDconfig LLDconfigRxHDMIStereo = // for SAP_D10_RX_HDMI_STEREO
{
- &mcaspGblSetup,
&mcaspRcvSetupDIR,
&mcaspRxChanParamHDMIStereo,
0x23,
0x63,
+ 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for DIR/HDMI
+ 0x2,
CSL_MCASP_0,
MCASP_INPUT,
asipMcaspCallback,
mcaspLLDconfig LLDconfigRxHDMI = // for SAP_D10_RX_HDMI
{
- &mcaspGblSetup,
&mcaspRcvSetupDIR,
&mcaspRxChanParamHDMI,
0x23,
0x63,
+ 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for DIR/HDMI
+ 0x2,
CSL_MCASP_0,
MCASP_INPUT,
asipMcaspCallback,
/*
mcaspLLDconfig LLDconfigTxDIT = // for SAP_D10_TX_DIT
{
- &mcaspGblSetup,
&mcaspXmtSetupDIT,
&mcaspTx0ChanParamDIT,
NULL,
mcaspLLDconfig LLDconfigTxDAC = // for SAP_D10_TX_DAC
{
- &mcaspGblSetup,
- &mcaspXmtSetupDAC,
+ &mcaspXmtSetupDAC,
&mcaspTx0ChanParamDAC,
0x23,
0x63,
+ 0x02000000, // Set Amute pin as output for Tx channel
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
mcaspLLDconfig LLDconfigTxDACSlave = // for SAP_D10_TX_DAC_SLAVE
{
- &mcaspGblSetup,
&mcaspXmtSetupDACSlave,
&mcaspTx0ChanParamDAC,
0x23,
0x63,
+ 0x02000000,
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
mcaspLLDconfig LLDconfigTxDACStereo = // for SAP_D10_TX_STEREO_DAC
{
- &mcaspGblSetup,
&mcaspXmtSetupDAC,
&mcaspTx0ChanParamDACStereo,
0x23,
0x63,
+ 0x02000000,
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
mcaspLLDconfig LLDconfigTxDACStereoSlave = // for SAP_D10_TX_STEREO_DAC_SLAVE
{
- &mcaspGblSetup,
&mcaspXmtSetupDACSlave,
&mcaspTx0ChanParamDACStereo,
0x23,
0x63,
+ 0x02000000,
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
mcaspLLDconfig LLDconfigTxDAC12ch = // for SAP_D10_TX_DAC_12CH
{
- &mcaspGblSetup,
&mcaspXmtSetupDAC,
&mcaspTx0ChanParamDAC12ch,
0x23,
0x63,
+ 0x02000000,
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
mcaspLLDconfig LLDconfigTxDAC16ch = // for SAP_D10_TX_DAC_16CH
{
- &mcaspGblSetup,
&mcaspXmtSetupDAC,
&mcaspTx0ChanParamDAC16ch,
0x23,
0x63,
+ 0x02000000,
+ 0x2,
CSL_MCASP_0,
MCASP_OUTPUT,
asopMcaspCallback,
int32_t status;
if(mcaspDevHandles[lldCfg->mcaspPort] == NULL) {
- /* Initialize McASP Tx and Rx parameters */
- mcaspParams = Mcasp_PARAMS;
+ /* Initialize McASP parameters */
+ mcaspParams = Mcasp_PARAMS; // Mcasp_PARAMS defined in McASP LLD
- //mcaspParams.mcaspHwSetup.tx.clk.clkSetupClk = 0x23; // not used
- //mcaspParams.mcaspHwSetup.rx.clk.clkSetupClk = 0x23; // not used
mcaspParams.mcaspHwSetup.rx.clk.clkSetupClk = lldCfg->clkSetupClkRx;
mcaspParams.mcaspHwSetup.tx.clk.clkSetupClk = lldCfg->clkSetupClkTx;
-
- mcaspParams.mcaspHwSetup.glb.pdir = lldCfg->mcaspSetupGbl->pdir;
- mcaspParams.mcaspHwSetup.glb.amute = lldCfg->mcaspSetupGbl->amute;
+ mcaspParams.mcaspHwSetup.glb.pdir |= lldCfg->pdirAmute;
+ mcaspParams.mcaspHwSetup.glb.amute = lldCfg->amute;
status = mcaspBindDev(&mcaspDevHandles[lldCfg->mcaspPort], lldCfg->mcaspPort, &mcaspParams);
if((status != MCASP_COMPLETED) || (mcaspDevHandles[lldCfg->mcaspPort] == NULL)) {
- //IFPRINT(platform_write("mcaspBindDev for Tx Failed\n"));
return (Audk2g_EFAIL);
}
}
lldCfg->mcaspChanParams->edmaHandle = hEdma1;
}
- /* Create McASP channel for Tx */
+ /* Create McASP channel */
*pChanHandle = NULL;
status = mcaspCreateChan(pChanHandle, lldCfg->hMcaspDev,
lldCfg->chanMode, lldCfg->mcaspChanParams,