Updates for DCS7 (UART SWI implementation). Fixed IPC init issue.

[processor-sdk/performance-audio-sr.git] / pasdk / test_dsp / framework / systemInit.c

diff --git a/pasdk/test_dsp/framework/systemInit.c b/pasdk/test_dsp/framework/systemInit.c
index b8d82156136c87a972d995d305275fd5adae776f..365b6cb8a51c7a2ef7570279d5244951ddfbb2af 100644 (file)
--- a/pasdk/test_dsp/framework/systemInit.c
+++ b/pasdk/test_dsp/framework/systemInit.c
@@ -72,11 +72,11 @@ extern PAF_ASOT_Fxns PAF_ASOT_params_fxns;
 
 Int gSysInit=0;
 
-#define TASK_AFP_PRI        ( 3 )//( 1 )  // (***) FL: temporary fix for PASDK-64
-#define TASK_AIP_PRI        ( 1 )//( 2 ) 
+#define TASK_AFP_PRI        ( 1 )//( 1 )  // (***) FL: temporary fix for PASDK-64
+#define TASK_AIP_PRI        ( 2 )//( 2 )
 #define TASK_SSP_PRI        ( 1 )
-#define TASK_ASIP_PRI       ( 2 )//( 3 ) 
-#define TASK_ASOP_PRI       ( 2 )//( 3 ) 
+#define TASK_ASIP_PRI       ( 3 )//( 3 )
+#define TASK_ASOP_PRI       ( 3 )//( 3 )
 
 #define __TASK_NAME__  "TaskSysInit"
 
@@ -96,6 +96,16 @@ Void taskSysInitFxn(Void)
 
     Log_info0("Enter taskSysInitFxn()");
 
+    // Create Shared DDR region as non-Cacheable, Before IPC attach
+    // TODO: remove hardcoded address and get correct values from .bld
+    {   // base: 0x81000000, len: 0x01000000,
+        UInt Common2_DDR3_MAR_base = 0x01848204;
+        UInt Common2_DDR3_base = 0x81000000;
+        UInt Common2_DDR3_len = 0x01000000;
+        // disable cache for common2 DDR3
+        Cache_setMar(Common2_DDR3_base, Common2_DDR3_len, Cache_Mar_DISABLE);
+    }
+
     //taskPriAfp = Task_setPri(TaskAfp, -1);
     //taskPriAip = Task_setPri(TaskAip, -1);
     //taskPriAsip = Task_setPri(TaskAsip, -1);
@@ -111,16 +121,6 @@ Void taskSysInitFxn(Void)
     //} while ((status < 0) && (status == Ipc_E_NOTREADY));
     } while (status != Ipc_S_SUCCESS);
 
-    // Create Shared DDR region as non-Cacheable
-    // TODO: remove hardcoded address and get correct values from .bld
-    {   // base: 0x81000000, len: 0x01000000,
-        UInt Common2_DDR3_MAR_base = 0x01848204;
-        UInt Common2_DDR3_base = 0x81000000;
-        UInt Common2_DDR3_len = 0x01000000;
-        // disable cache for common2 DDR3
-        Cache_setMar(Common2_DDR3_base, Common2_DDR3_len, Cache_Mar_DISABLE);
-    }
-
     /* Initialize (IPC) ASP master messaging */
     /* Note: MessageQ_open() called in this function.
              MessageQ_open() blocks. */