[processor-sdk/performance-audio-sr.git] / psdk_cust / ipc_3_43_00_00_eng / docs / cdoc / ti / sdo / ipc / family / tda3xx / InterruptIpu-src.html
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-<html><head><title>module ti.sdo.ipc.family.tda3xx.InterruptIpu</title>
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- 1 <span class="comment">/*
-</span> 2 <span class="comment"> * Copyright (c) 2014 Texas Instruments Incorporated - http://www.ti.com
-</span> 3 <span class="comment"> * All rights reserved.
-</span> 4 <span class="comment"> *
-</span> 5 <span class="comment"> * Redistribution and use in source and binary forms, with or without
-</span> 6 <span class="comment"> * modification, are permitted provided that the following conditions
-</span> 7 <span class="comment"> * are met:
-</span> 8 <span class="comment"> *
-</span> 9 <span class="comment"> * * Redistributions of source code must retain the above copyright
-</span> 10 <span class="comment"> * notice, this list of conditions and the following disclaimer.
-</span> 11 <span class="comment"> *
-</span> 12 <span class="comment"> * * Redistributions in binary form must reproduce the above copyright
-</span> 13 <span class="comment"> * notice, this list of conditions and the following disclaimer in the
-</span> 14 <span class="comment"> * documentation and/or other materials provided with the distribution.
-</span> 15 <span class="comment"> *
-</span> 16 <span class="comment"> * * Neither the name of Texas Instruments Incorporated nor the names of
-</span> 17 <span class="comment"> * its contributors may be used to endorse or promote products derived
-</span> 18 <span class="comment"> * from this software without specific prior written permission.
-</span> 19 <span class="comment"> *
-</span> 20 <span class="comment"> * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-</span> 21 <span class="comment"> * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-</span> 22 <span class="comment"> * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-</span> 23 <span class="comment"> * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-</span> 24 <span class="comment"> * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-</span> 25 <span class="comment"> * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-</span> 26 <span class="comment"> * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-</span> 27 <span class="comment"> * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-</span> 28 <span class="comment"> * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-</span> 29 <span class="comment"> * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-</span> 30 <span class="comment"> * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-</span> 31 <span class="comment"> */</span>
- 32 <span class="comment">/*
-</span> 33 <span class="comment"> * ======== InterruptIpu.xdc ========
-</span> 34 <span class="comment"> *
-</span> 35 <span class="comment"> */</span>
- 36
- 37 import ti.sdo.utils.MultiProc;
- 38
- 39 <span class="xdoc">/*!
-</span> 40 <span class="xdoc"> * ======== InterruptIpu ========
-</span> 41 <span class="xdoc"> * IPU interrupt manager
-</span> 42 <span class="xdoc"> */</span>
- 43 <span class=key>module</span> InterruptIpu <span class=key>inherits</span> ti.sdo.ipc.notifyDrivers.IInterrupt
- 44 {
- 45 <span class="xdoc">/*!
-</span> 46 <span class="xdoc"> * Maximum number of cores
-</span> 47 <span class="xdoc"> *
-</span> 48 <span class="xdoc"> * <b>@_nodoc</b>
-</span> 49 <span class="xdoc"> */</span>
- 50 <span class=key>const</span> UInt8 NUM_CORES = 5;
- 51
- 52 <span class="xdoc">/*!
-</span> 53 <span class="xdoc"> * Maximum number of EVE cores
-</span> 54 <span class="xdoc"> *
-</span> 55 <span class="xdoc"> * Although your device may have fewer EVE cores, `NUM_EVES` represents
-</span> 56 <span class="xdoc"> * the maximum number of EVEs that may be present on a system.
-</span> 57 <span class="xdoc"> */</span>
- 58 <span class=key>const</span> UInt8 NUM_EVES = 1;
- 59
- 60 <span class="xdoc">/*!
-</span> 61 <span class="xdoc"> * Maximum number of IPU cores
-</span> 62 <span class="xdoc"> *
-</span> 63 <span class="xdoc"> * <b>@_nodoc</b>
-</span> 64 <span class="xdoc"> */</span>
- 65 <span class=key>const</span> UInt8 NUM_Ipu_CORES = 2;
- 66
- 67 <span class="xdoc">/*!
-</span> 68 <span class="xdoc"> * Number of internal EVE mailboxes
-</span> 69 <span class="xdoc"> *
-</span> 70 <span class="xdoc"> * Each EVE core has 3 mailboxes.
-</span> 71 <span class="xdoc"> *
-</span> 72 <span class="xdoc"> * Although your device may have fewer EVE cores, `NUM_EVE_MBX` represents
-</span> 73 <span class="xdoc"> * the maximum number of EVE mailboxes (including all EVE cores) that may
-</span> 74 <span class="xdoc"> * be present.
-</span> 75 <span class="xdoc"> */</span>
- 76 <span class=key>const</span> UInt8 NUM_EVE_MBX = NUM_EVES * 2;
- 77
- 78 <span class="xdoc">/*!
-</span> 79 <span class="xdoc"> * Number of System mailboxes used by IPC
-</span> 80 <span class="xdoc"> *
-</span> 81 <span class="xdoc"> * This represents the number of System mailboxes used by IPC. IPC
-</span> 82 <span class="xdoc"> * currently uses system mailboxes 5, 6, 7 and 8.
-</span> 83 <span class="xdoc"> */</span>
- 84 <span class=key>const</span> UInt8 NUM_SYS_MBX = 1;
- 85
- 86 <span class="xdoc">/*!
-</span> 87 <span class="xdoc"> * Base address for the mailbox subsystems
-</span> 88 <span class="xdoc"> *
-</span> 89 <span class="xdoc"> * The `mailboxBaseAddr` array indicates the virtual addresses through
-</span> 90 <span class="xdoc"> * which IPC will access various mailboxes.
-</span> 91 <span class="xdoc"> *
-</span> 92 <span class="xdoc"> * Note that these mailboxes are not accessible at their physical
-</span> 93 <span class="xdoc"> * addresses (in the 0x4XXX_XXXX range). So default virtual addresses
-</span> 94 <span class="xdoc"> * through which these mailboxes will be accessed are assigned in the
-</span> 95 <span class="xdoc"> * 0x6XXX_XXXX range. Users must ensure these virtual addresses are
-</span> 96 <span class="xdoc"> * correctly mapped to the 0x4XXX_XXXX-based phys addrs in each IPUs AMMU.
-</span> 97 <span class="xdoc"> */</span>
- 98 <span class=key>config</span> UInt32 mailboxBaseAddr[NUM_EVE_MBX + NUM_SYS_MBX];
- 99
- 100 <span class="xdoc">/*!
-</span> 101 <span class="xdoc"> * Mailbox table for storing encoded Base Address, mailbox user Id,
-</span> 102 <span class="xdoc"> * and sub-mailbox index.
-</span> 103 <span class="xdoc"> *
-</span> 104 <span class="xdoc"> * <b>@_nodoc</b>
-</span> 105 <span class="xdoc"> */</span>
- 106 <span class=key>config</span> UInt32 mailboxTable[NUM_CORES * NUM_CORES];
- 107
- 108 <span class="xdoc">/*!
-</span> 109 <span class="xdoc"> * Base address for the Ducati CTRL register
-</span> 110 <span class="xdoc"> */</span>
- 111 <span class=key>config</span> UInt32 ducatiCtrlBaseAddr = 0x40001000;
- 112
- 113 <span class="xdoc">/*!
-</span> 114 <span class="xdoc"> * Processor Id table
-</span> 115 <span class="xdoc"> *
-</span> 116 <span class="xdoc"> * <b>@_nodoc</b>
-</span> 117 <span class="xdoc"> */</span>
- 118 <span class=key>config</span> UInt32 procIdTable[NUM_CORES];
- 119
- 120 <span class=key>internal</span>:
- 121
- 122 <span class="xdoc">/*! Statically retrieve procIds to avoid doing this at runtime */</span>
- 123 <span class=key>config</span> UInt eve1ProcId = MultiProc.INVALIDID;
- 124 <span class=key>config</span> UInt dsp1ProcId = MultiProc.INVALIDID;
- 125 <span class=key>config</span> UInt dsp2ProcId = MultiProc.INVALIDID;
- 126 <span class=key>config</span> UInt ipu1_0ProcId = MultiProc.INVALIDID;
- 127 <span class=key>config</span> UInt ipu1_1ProcId = MultiProc.INVALIDID;
- 128
- 129 <span class="xdoc">/*! Function table */</span>
- 130 <span class=key>struct</span> FxnTable {
- 131 Fxn func;
- 132 UArg arg;
- 133 }
- 134
- 135 <span class="xdoc">/*! Stub to be plugged for inter-ducati interrupts */</span>
- 136 Void intShmDucatiStub(UArg arg);
- 137
- 138 <span class="xdoc">/*! Stub to be plugged for intra-ducati interrupts */</span>
- 139 Void intShmMbxStub(UInt16 idx);
- 140
- 141 <span class=key>struct</span> Module_State {
- 142 <span class="comment">/*
-</span> 143 <span class="comment"> * Create a function table of length 8 (Total number of cores in the
-</span> 144 <span class="comment"> * System) for each M4 core.
-</span> 145 <span class="comment"> */</span>
- 146 FxnTable fxnTable[NUM_CORES];
- 147 };
- 148 }
-</pre>
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