[processor-sdk/performance-audio-sr.git] / psdk_cust / pdk_k2g_1_0_1_0_eng / packages / ti / board / src / idkAM572x / boardPadDelayTune.h
diff --git a/psdk_cust/pdk_k2g_1_0_1_0_eng/packages/ti/board/src/idkAM572x/boardPadDelayTune.h b/psdk_cust/pdk_k2g_1_0_1_0_eng/packages/ti/board/src/idkAM572x/boardPadDelayTune.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/**
- * Note: This file was auto-generated by TI PinMux on 3/1/2016 at 8:15:27 PM.
- *
- * \file boardPadDelayTune.h
- *
- * \brief This file contain manual/vritual iodelay mode definitions
- *
- * \copyright Copyright (CU) 2015 Texas Instruments Incorporated -
- * http://www.ti.com/
- */
-
-/**
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-
-
-
-/*#define VIP2_REC1 */ /* VIN3A/3B IOSET1 Rise-Edge Capture Mode */
-/*#define VIP2_FEC2 */ /* VIN3A/3B IOSET1, VIN4A IOSET1/2 Fall-Edge Capture Mode */
-/*#define VIP2_REC4 */ /* VIN4B Rise-Edge Capture Mode */
-#define VIP2_FEC5 /* VIN4B Fall-Edge Capture Mode */
-#define GMAC_RGMII0_MANUAL1 /* GMAC RGMII0 with Transmit Clock Internal Delay Enabled Timings */
-#define QSPI_MODE0_DEFAULT /* QSPI Mode 0 Default Timing Mode */
-/*#define QSPI_MODE3_ALT1 */ /* QSPI Mode 3 Alternate Timing Mode 1 */
-/*#define QSPI_MODE3_ALT2 */ /* QSPI Mode 3 Alternate Timing Mode 2 */
-/*#define DSS_ALT4 */ /* DPI1 Video Output Alternate */
-/*#define DSS_FEC */ /* DPI1/2/3 Video Output Default - Falling-edge Clock Reference */
-#define GPMC_ASYNC /* GPMC Asynchronous Mode (1/5 Load) Timings and Synchronous Mode (1 Load) */
-/*#define GPMC_SYNC_5 */ /* GPMC Synchronous Mode (5 Load) */
-#define MMC1_DS_PLB_SDR12_PLB_DEFAULT /* MMC1 DS (Pad Loopback) and SDR12 (Pad Loopback) Default Timings */
-/*#define MMC1_DDR50_PLB */ /* MMC1 DDR50 (Pad Loopback) Timings */
-/*#define MMC1_SDR_104 */ /* MMC1 SDR104 Timings */
-/*#define MMC1_HS_SDR12_ILB_SDR25 */ /* MMC1 HS (Internal Loopback and Pad Loopback), SDR12 (Internal Loopback), SDR25 Timings (Internal Loopback and Pad Loopback) */
-/*#define MMC1_SDR50_PLB */ /* MMC1 SDR50 (Pad Loopback) Timings */
-/*#define MMC1_DS_ILB */ /* MMC1 DS (Internal Loopback) Timings */
-/*#define MMC1_SDR50_ILB */ /* MMC1 SDR50 (Internal Loopback) Timings */
-/*#define MMC1_DDR50_ILB */ /* MMC1 DDR50 (Internal Loopback) Timings */
-#define PR2_PRU1_DIR_OUT2 /* PRU-ICSS2 PRU1 IOSET2 Direct Output Mode Timings */
-/*#define PRU_ICSS2_OUT */ /* PRU-ICSS2 Direct Output Mode Timings */
-#define PR2_PRU1_DIR_IN2 /* PRU-ICSS2 PRU1 IOSET2 Direct Input Mode Timings */
-/*#define PR2_PRU1_PAR_CAP2 */ /* PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode Timings */
-/*#define PRU_ICSS2_IN */ /* PRU-ICSS2 Direct Input Mode Timings */
-#define GMAC_RGMII1_MANUAL1 /* GMAC RGMII1 with Transmit Clock Internal Delay Enabled Timings */
-/*#define PR1_PRU1_DIR_OUT */ /* PRU-ICSS1 PRU1 Direct Output Mode Timings */
-/*#define PRU_ICSS1_OUT */ /* PRU-ICSS1 Direct Output Mode Timings */
-/*#define GMAC_RMII0 */ /* GMAC RMII0 Timings */
-/*#define GMAC_RMII1 */ /* GMAC RMII1 Timings */
-#define MMC2_STD_PLB_HS_PLB /* MMC2 Standard (Pad Loopback) and High Speed (Pad Loopback) Timings */
-/*#define MMC2_DDR_PLB */ /* MMC2 DDR (Pad Loopback) 1.8V and 3.3V Mode Timings */
-/*#define MMC2_DDR_ILB */ /* MMC2 DDR (Internal Loopback) Timings */
-/*#define MMC2_STD_ILB_HS_ILB */ /* MMC2 Standard (Internal Loopback), High Speed (Internal Loopback) Timings */
-/*#define MMC2_HS200 */ /* MMC2 HS200 Timings */
-
-/* MODE RE-DEFINITIONS */
-
-#ifdef VIP2_REC1
- #define VIP2_MANUAL1
-#endif
-#ifdef VIP2_FEC2
- #define VIP2_MANUAL2
-#endif
-#ifdef VIP2_REC4
- #define VIP2_4B_MANUAL1
-#endif
-#ifdef VIP2_FEC5
- #define VIP2_4B_MANUAL2
-#endif
-#ifdef GMAC_RGMII0_MANUAL1
- #define GMAC_RGMII0_MANUAL1
-#endif
-#ifdef QSPI_MODE0_DEFAULT
- #define QSPI_MODE0_MANUAL1
-#endif
-#ifdef QSPI_MODE3_ALT1
- #define QSPI1_VIRTUAL1
-#endif
-#ifdef QSPI_MODE3_ALT2
- #define QSPI1_VIRTUAL2
-#endif
-#ifdef DSS_ALT4
- #define VOUT1_MANUAL1
-#endif
-#ifdef DSS_FEC
- #define DSS_VIRTUAL1
-#endif
-#ifdef GPMC_ASYNC
- #define GPMC_DEFAULT
-#endif
-#ifdef GPMC_SYNC_5
- #define GPMC_VIRTUAL1
-#endif
-#ifdef MMC1_DS_PLB_SDR12_PLB_DEFAULT
- #define MMC1_DEFAULT
-#endif
-#ifdef MMC1_DDR50_PLB
- #define MMC1_DDR_MANUAL1
-#endif
-#ifdef MMC1_SDR_104
- #define MMC1_SDR104_MANUAL1
-#endif
-#ifdef MMC1_HS_SDR12_ILB_SDR25
- #define MMC1_VIRTUAL1
-#endif
-#ifdef MMC1_SDR50_PLB
- #define MMC1_VIRTUAL2
-#endif
-#ifdef MMC1_DS_ILB
- #define MMC1_VIRTUAL5
-#endif
-#ifdef MMC1_SDR50_ILB
- #define MMC1_VIRTUAL6
-#endif
-#ifdef MMC1_DDR50_ILB
- #define MMC1_VIRTUAL7
-#endif
-#ifdef PR2_PRU1_DIR_OUT2
- #define PR2_PRU1_DIR_OUT_MANUAL2
-#endif
-#ifdef PRU_ICSS2_OUT
- #define PRU_ICSS2_OUT_VIRTUAL1
-#endif
-#ifdef PR2_PRU1_DIR_IN2
- #define PR2_PRU1_DIR_IN_MANUAL2
-#endif
-#ifdef PR2_PRU1_PAR_CAP2
- #define PR2_PRU1_PAR_CAP_MANUAL2
-#endif
-#ifdef PRU_ICSS2_IN
- #define PRU_ICSS2_IN_VIRTUAL1
-#endif
-#ifdef GMAC_RGMII1_MANUAL1
- #define GMAC_RGMII1_MANUAL1
-#endif
-#ifdef PR1_PRU1_DIR_OUT
- #define PR1_PRU1_DIR_OUT_MANUAL
-#endif
-#ifdef PRU_ICSS1_OUT
- #define PRU_ICSS1_OUT_VIRTUAL1
-#endif
-#ifdef GMAC_RMII0
- #define GMAC_RMII0_MANUAL1
-#endif
-#ifdef GMAC_RMII1
- #define GMAC_RMII1_MANUAL1
-#endif
-#ifdef MMC2_STD_PLB_HS_PLB
- #define MMC2_DEFAULT
-#endif
-#ifdef MMC2_DDR_PLB
- #define MMC2_DDR_MANUAL1
-#endif
-#ifdef MMC2_DDR_ILB
- #define MMC2_DDR_LB_MANUAL1
-#endif
-#ifdef MMC2_STD_ILB_HS_ILB
- #define MMC2_STD_HS_LB_MANUAL1
-#endif
-#ifdef MMC2_HS200
- #define MMC2_HS200_MANUAL1
-#endif