PASDK-284:Merge branch 'dev_pasdk_govind_pasdk284' of ssh://bitbucket.itg.ti.com...
authorFrank Livingston <frank-livingston@ti.com>
Tue, 3 Oct 2017 19:49:46 +0000 (14:49 -0500)
committerFrank Livingston <frank-livingston@ti.com>
Tue, 3 Oct 2017 19:49:46 +0000 (14:49 -0500)
19 files changed:
pasdk/test_dsp/.cproject
pasdk/test_dsp/application/itopo/evmk2g/audio_dc_cfg.c [new file with mode: 0644]
pasdk/test_dsp/application/itopo/evmk2g/audio_dc_cfg.h [moved from pasdk/test_dsp/sap/audio_dc_cfg.h with 56% similarity]
pasdk/test_dsp/application/itopo/evmk2g/edma_cfg.c [moved from pasdk/test_dsp/sap/edma_cfg.c with 100% similarity]
pasdk/test_dsp/application/itopo/evmk2g/edma_cfg.h [moved from pasdk/test_dsp/sap/edma_cfg.h with 100% similarity]
pasdk/test_dsp/application/itopo/evmk2g/io.c
pasdk/test_dsp/application/itopo/evmk2g/platform_osal.c [moved from pasdk/test_dsp/sap/platform_osal.c with 100% similarity]
pasdk/test_dsp/application/itopo/evmk2g/sample_cs.c [moved from pasdk/test_dsp/sap/sample_cs.c with 100% similarity]
pasdk/test_dsp/application/itopo/evmk2g/sample_k2g_cfg.c [moved from pasdk/test_dsp/sap/sample_k2g_cfg.c with 100% similarity]
pasdk/test_dsp/application/itopo/evmk2g/sample_k2g_int_reg.c [moved from pasdk/test_dsp/sap/sample_k2g_int_reg.c with 100% similarity]
pasdk/test_dsp/application/itopo/evmk2g/sap_d10.c [moved from pasdk/test_dsp/sap/sap_d10.c with 98% similarity]
pasdk/test_dsp/application/itopo/evmk2g/sap_d10.h [moved from pasdk/test_dsp/sap/sap_d10.h with 100% similarity]
pasdk/test_dsp/application/itopo/evmk2g/vproccmds_a.h [moved from pasdk/test_dsp/sap/vproccmds_a.h with 100% similarity]
pasdk/test_dsp/framework/itopo/params.c
pasdk/test_dsp/mib/mib.c
pasdk/test_dsp/mob/mob.c
pasdk/test_dsp/sap/audio_dc_cfg.c [deleted file]
pasdk/test_dsp/sap/sap.c
pasdk/test_dsp/sap/sap_mcasp.c

index 5b1f5e4f9c63c4dcf453fb0da073a056fda37b1d..092f847882f7ea3263e51c249b7510801cc2fb14 100644 (file)
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diff --git a/pasdk/test_dsp/application/itopo/evmk2g/audio_dc_cfg.c b/pasdk/test_dsp/application/itopo/evmk2g/audio_dc_cfg.c
new file mode 100644 (file)
index 0000000..21bbf18
--- /dev/null
@@ -0,0 +1,666 @@
+
+/*
+Copyright (c) 2017, Texas Instruments Incorporated - http://www.ti.com/
+All rights reserved.
+
+* Redistribution and use in source and binary forms, with or without 
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+/**
+ * \file      audio_dc_config.c
+ *
+ * \brief     Configures Audio daughter card HW modules
+ *
+ */
+
+#include "audio_dc_cfg.h"
+#include "vproccmds_a.h"
+#include <stdarg.h>
+#include "string.h"
+#include <xdc/runtime/Log.h>
+#include "audk2g_audio.h"
+
+#define HSR4_I2C_ADDR 0x5D
+#define        HSR4_I2C_PORT_NUM CSL_I2C_1
+#define I2C_TRANSACTION_TIMEOUT         (2000U)
+
+I2C_Params i2cParams;
+I2C_Handle i2cHandle = NULL;
+I2C_Transaction i2cTransaction;
+uint32_t gI2cDelay=I2C_TRANSACTION_TIMEOUT;
+
+Audk2g_STATUS audioHDMIConfig(void);
+int alpha_i2c_write(unsigned short, ...);
+void set_audio_desc(unsigned char ,unsigned char ,unsigned char ,unsigned char ,unsigned char );
+void hrptredid();
+void  hdmi128();
+
+int gret_val=0;
+
+/* ------------------------------------------------------------------------ *
+ *  Prototypes                                                              *
+ * ------------------------------------------------------------------------ */
+
+/**
+ *  \brief    Initializes ADC module
+ *
+ *  This function initializes and configures the ADC modules
+ *  on audio daughter card
+ *
+ *  \param     devId  [IN]  ADC Device Id
+ *  \param     config [IN]  ADC configuration parameters
+ *
+ *  \return    Platform_EOK on Success or error code
+ */
+Audk2g_STATUS audioAdcConfig(Audk2gAdcDevId  devId, AdcConfig *config)
+{
+       Audk2g_STATUS status;
+
+       if(config == NULL)
+       {
+               IFPRINT(audk2g_write("Invalid Inputs\n"));
+               return (Audk2g_EINVALID);
+       }
+
+       /* Initialize all the HW instances of ADC */
+       status = audk2g_AudioAdcInit(devId);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcInit Failed\n"));
+               return (status);
+       }
+
+       /* Set ADC channel gain */
+       status = audk2g_AudioAdcSetGain(devId, AUDK2G_ADC_CH_ALL, config->gain);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcSetGain Failed\n"));
+               return (status);
+       }
+
+       /* Configure Left input mux for ADC1L */
+       status = audk2g_AudioAdcSetLeftInputMux(devId, AUDK2G_ADC_CH1_LEFT,
+                                                config->adc1LMux);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcSetLeftInputMux Failed\n"));
+               return (status);
+       }
+
+       /* Configure Left input mux for ADC2L*/
+       status = audk2g_AudioAdcSetLeftInputMux(devId, AUDK2G_ADC_CH2_LEFT,
+                                                config->adc2LMux);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcSetLeftInputMux Failed\n"));
+               return (status);
+       }
+
+       /* Configure Right input mux for ADC1R */
+       status = audk2g_AudioAdcSetRightInputMux(devId, AUDK2G_ADC_CH1_RIGHT,
+                                                 config->adc1RMux);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcSetRightInputMux Failed\n"));
+               return (status);
+       }
+
+       /* Configure Right input mux for ADC2R */
+       status = audk2g_AudioAdcSetRightInputMux(devId, AUDK2G_ADC_CH2_RIGHT,
+                                                 config->adc2RMux);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcSetRightInputMux Failed\n"));
+               return (status);
+       }
+
+       /* Configure audio data format */
+       status = audk2g_AudioAdcDataConfig(devId, config->wlen, config->format);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcDataConfig Failed\n"));
+               return (status);
+       }
+
+       /* Configure all the interrupts */
+       status = audk2g_AudioAdcConfigIntr(devId, AUDK2G_ADC_INTR_ALL,
+                                           config->intEnable);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcConfigIntr Failed\n"));
+               return (status);
+       }
+
+       return (status);
+}
+
+/**
+ *  \brief    Initializes DAC module
+ *
+ *  This function initializes and configures the DAC modules
+ *  on audio daughter card
+ *
+ *  \param     devId  [IN]  DAC Device Id
+ *  \param     config [IN]  DAC configuration parameters
+ *
+ *  \return    Platform_EOK on Success or error code
+ */
+Audk2g_STATUS audioDacConfig(Audk2gDacDevId devId, DacConfig *config)
+{
+       Audk2g_STATUS status;
+
+       if(config == NULL)
+       {
+               IFPRINT(audk2g_write("Invalid Inputs\n"));
+               return (Audk2g_EINVALID);
+       }
+
+       /* Initialize Audio DAC */
+       status = audk2g_AudioDacInit(devId);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacInit Failed\n"));
+               return (status);
+       }
+
+       /* Configure AMUTE control event */
+       status = audk2g_AudioDacAmuteCtrl(devId, config->amuteCtrl,
+                                          config->amuteEnable);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacAmuteCtrl Failed\n"));
+               return (status);
+       }
+
+       /* Set sampling mode */
+       status = audk2g_AudioDacSetSamplingMode(devId, config->samplingMode);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacSetSamplingMode Failed\n"));
+               return (status);
+       }
+
+       /* Set data format */
+       status = audk2g_AudioDacSetDataFormat(devId, config->dataFormat);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacSetDataFormat Failed\n"));
+               return (status);
+       }
+
+       /* Enable soft mute control */
+       status = audk2g_AudioDacSoftMuteCtrl(devId, AUDK2G_DAC_CHAN_ALL,
+                                             config->softMuteEnable);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacSoftMuteCtrl Failed\n"));
+               return (status);
+       }
+
+       /* Set attenuation mode */
+       status = audk2g_AudioDacSetAttnMode(devId, config->attnMode);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacSetAttnMode Failed\n"));
+               return (status);
+       }
+
+       /* Set De-emphasis control */
+       status = audk2g_AudioDacDeempCtrl(devId, config->deempCtrl);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacDeempCtrl Failed\n"));
+               return (status);
+       }
+
+       /* Set DAC volume */
+       status = audk2g_AudioDacSetVolume(devId, AUDK2G_DAC_CHAN_ALL, config->volume);
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacSetVolume Failed\n"));
+               return (status);
+       }
+
+       return (status);
+}
+
+/**
+ *  \brief    Initializes DIR module
+ *
+ *  This function initializes and configures the DIR modules
+ *  on audio daughter card
+ *
+ *  \return    Platform_EOK on Success or error code
+ */
+Audk2g_STATUS audioDirConfig(void)
+{
+       Audk2g_STATUS status;
+       int8_t          fsout;
+#ifdef CHECK_ERROR_STATUS
+       uint32_t        timeout;
+#endif
+
+       status = audk2g_AudioDirInit();
+       if(status != Audk2g_EOK)
+       {
+               IFPRINT(audk2g_write("audioDirConfig : Audio DIR Configuration Failed!\n"));
+               return (status);
+       }
+
+#ifdef CHECK_ERROR_STATUS
+       /* DIR should be in PLL mode.
+          Wait for ERROR signal to be low as DIR is configured for
+          AUTO mode */
+       timeout = ERROR_STATUS_WAIT_TIMEOUT;
+       while (timeout)
+       {
+               if(!audk2g_AudioDirGetErrStatus())
+               {
+                       IFPRINT(audk2g_write("audioDirConfig : DIR in PLL Mode\n"));
+                       break;
+               }
+
+               IFPRINT(audk2g_write("audioDirConfig : Waiting for DIR to Enter PLL Mode...\n"));
+               audk2g_delay(10);
+               timeout--;
+       }
+
+       if(!timeout)
+       {
+               IFPRINT(audk2g_write("audioDirConfig : DIR is not in PLL Mode!!\n"));
+               return (Platform_EFAIL);
+       }
+#endif
+
+       fsout = audk2g_AudioDirGetFsOut();
+       if(fsout == 2)
+       {
+               IFPRINT(audk2g_write("audioDirConfig : Out of Range Sampling Frequency\n"));
+       }
+       else if(fsout == 0)
+       {
+               IFPRINT(audk2g_write("audioDirConfig : Calculated Sampling Frequency Output is 43 kHz\9645.2 kHz\n"));
+       }
+       else if(fsout == 1)
+       {
+               IFPRINT(audk2g_write("audioDirConfig : Calculated Sampling Frequency Output is 46.8 kHz\9649.2 kHz\n"));
+       }
+       else if(fsout == 3)
+       {
+               IFPRINT(audk2g_write("audioDirConfig : Calculated Sampling Frequency Output is 31.2 kHz\9632.8 kHz\n"));
+       }
+       else
+       {
+               IFPRINT(audk2g_write("audioDirConfig : Error in Reading FSOUT status \n"));
+               status = Audk2g_EFAIL;
+       }
+
+       return (status);
+}
+
+/**
+ *  \brief    Prepare Alpha commands for serial (I2C) communication
+ *
+ *  This function parses the presented HSR41 alpha commands
+ *  and prepares CPM-formatted messages to be sent over the serial interface.
+ *
+ *  \return    '1' on completion
+ */
+
+int alpha_i2c_write(unsigned short var1, ...)
+{
+       unsigned short alpha_type,length,temp_var;
+       int i,offset,ret_val;
+       unsigned char cmd[50];
+       char *s;
+       va_list argp;
+       va_start(argp, var1);
+
+       alpha_type = var1>> 8;
+       switch(alpha_type)
+       {
+               case 0xca:
+               case 0xc2:
+               case 0xc3:
+               case 0xc4:
+                       length = 4;
+                       break;
+               case 0xcb:
+                       length = 6;
+                       break;
+               case 0xcc:
+                       length = 8;
+                       break;
+               case 0xcd:
+               case 0xc5:
+                       length= 8; // temporary - data starts after 8 bytes
+                       break;
+       }
+
+       cmd[0]=length;
+       temp_var=var1;
+       for(i=0;i<length-2;i+=2) // convert to bytes as per protocol
+       {
+               cmd[i+1]= temp_var & 0xff;
+               cmd[i+2]= temp_var >> 8;
+               temp_var=va_arg(argp, short);
+       }
+       cmd[i+1]= temp_var & 0xff;
+       cmd[i+2]= temp_var >> 8;
+
+
+       if(alpha_type == 0xcd) // special processing for variable length
+       {
+               offset=9;
+               s = va_arg(argp, char *); // remaining data is in form of string
+               length = temp_var; // last short indicates data length
+               cmd[0]+=length;
+               for(i=offset;i<offset+length;i++)
+                       cmd[i]=s[i-offset];
+       }
+va_end(argp);
+
+       do
+       {
+               I2C_transactionInit(&i2cTransaction);
+               i2cTransaction.slaveAddress = HSR4_I2C_ADDR;
+               i2cTransaction.writeBuf = cmd;
+               i2cTransaction.writeCount = cmd[0]+1;
+               i2cTransaction.timeout   = I2C_TRANSACTION_TIMEOUT;
+               ret_val = I2C_transfer(i2cHandle, &i2cTransaction);
+
+               if(ret_val !=I2C_STS_SUCCESS)
+               {
+                       gret_val++;
+                       I2C_control(i2cHandle, I2C_CMD_RECOVER_BUS, &gI2cDelay);
+               }
+       }while(ret_val !=I2C_STS_SUCCESS);
+
+return ret_val;
+}
+
+/**
+ *  \brief    Prepares audio format descriptors
+ *
+ *  This function prepares the configuration data to be programmed in HSR41's
+ *  audio format descriptor registers.
+ *
+ *
+ *  \return    none
+ */
+void set_audio_desc(unsigned char var1,unsigned char var2,unsigned char var3,unsigned char var4,unsigned char var5)
+{
+       int ret_val=I2C_STS_SUCCESS;
+
+       do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_FORMAT(var1, var2));}while (ret_val !=I2C_STS_SUCCESS);
+       do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_NUM_CHANNELS(var1, var3));}while (ret_val !=I2C_STS_SUCCESS);
+       do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_SAMPLE_RATES(var1, var4));}while (ret_val !=I2C_STS_SUCCESS);
+       do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_MISC(var1, var5));}while (ret_val !=I2C_STS_SUCCESS);
+}
+
+/**
+ *  \brief    Program HDMI CEA / EDID values, as necessary.
+ *
+ *  This function configures the HSR41 HDMI Repeater
+ *  with the necessary CEA/EDID information, enabling support for
+ *  the required audio formats.
+ *
+ *  \return    none
+ */
+
+void hrptredid()
+{
+       int ret_val=I2C_STS_SUCCESS;
+
+       do{ret_val=alpha_i2c_write(HSDIO_EDID_SPEAKER_ALLOCATION_BLOCK(0xFF));}while (ret_val !=I2C_STS_SUCCESS);
+       audk2g_delay(10);
+       do{ret_val=alpha_i2c_write(HSDIO_EDID_SPEAKER_ALLOCATION_BLOCK_2(0x7));}while (ret_val !=I2C_STS_SUCCESS);
+
+       set_audio_desc(0,1,2,0x7f,7);   // PCM 2 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4 KHz, 192 KHz, 16bit, 20bit, 24bit
+       set_audio_desc(1,1,8,0x7f,7);   // PCM 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4 KHz, 192 KHz, 16bit, 20bit, 24bit
+       set_audio_desc(2,2,6,0x7,80);   // AC3 6 channel, 32kHz, 44.1kHz, 48kHz, 640kHz max bit rate
+       set_audio_desc(3,10,8,0x07,1);  // Dolby Digital Plus, 8 channel, 32kHz, 44.1kHz, 48kHz, codec specific:1
+       set_audio_desc(4,12,8,0x7F,1);  // MAT(MPL)(Dolby TrueHD), 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz,
+                                                                       // 176.4kHz, 192kHz,  codec specific:1
+       set_audio_desc(5,7,6,0x1E,192); // DTS 6 channel, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 1,536kHz max bit rate
+       set_audio_desc(6,7,8,0x6,192);  // DTS 8 channel, 44.1kHz, 48kHz, 1,536kHz max bit rate
+       set_audio_desc(7,11,8,0x7F,3);  // DTS-HD, 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz,
+                                                                       // last byte is 3 for DTS:X, 1 otherwise.
+       set_audio_desc(8,11,8,0x7F,1);  // DTS-HD, 8 channel - same as above, but last byte = 1
+       set_audio_desc(9,6,6,0x1f,192); //AAC LC (9,6,6,0x1f,192);
+       set_audio_desc(10,0,0,0,0);
+       set_audio_desc(11,0,0,0,0);
+       set_audio_desc(12,0,0,0,0);
+       set_audio_desc(13,0,0,0,0);
+       set_audio_desc(14,0,0,0,0);
+       set_audio_desc(15,0,0,0,0);
+       set_audio_desc(16,0,0,0,0);
+       set_audio_desc(17,0,0,0,0);
+       set_audio_desc(18,0,0,0,0);
+       set_audio_desc(19,0,0,0,0);
+       do{ret_val=alpha_i2c_write(HSDIO_EDID_GO);}while (ret_val !=I2C_STS_SUCCESS);
+}
+
+/**
+ *  \brief    Configures HSR41's TO_HOST interface
+ *
+ *  This function configures the HDMI repeater for EXTRACT mode of operation
+ *  with the necessary HOST interface programming.
+ *
+ *  \return    None
+ */
+// Note: HDMI Tx/Out Port's state is not cared for, at all.
+
+void  hdmi128()
+{
+       int ret_val=I2C_STS_SUCCESS;
+
+       do{ret_val=alpha_i2c_write(HSDIO_ALERT(HSDIO_ALERT_INPUT_AUDIO_CHANGE_msk));}while (ret_val !=I2C_STS_SUCCESS);
+       do{ret_val=alpha_i2c_write(HSDIO_AUDIO_MCLK_TO_HOST(HSDIO_AudioMClk_128X));}while (ret_val !=I2C_STS_SUCCESS);
+       do{ret_val=alpha_i2c_write(HSDIO_AUDIO_UNMUTE_DELAY_TO_HOST(HSDIO_AudioUnMuteDelay_NO_DELAY));}while (ret_val !=I2C_STS_SUCCESS);
+       do{ret_val=alpha_i2c_write(HSDIO_AUDIO_FORMAT_TO_HOST(HSDIO_AudioFmt_I2S));}while (ret_val !=I2C_STS_SUCCESS);
+       do{ret_val=alpha_i2c_write(HSDIO_IMPLEMENT_AUDIO_TO_HOST_CMDS);}while (ret_val !=I2C_STS_SUCCESS);
+       do{ret_val=alpha_i2c_write(HSDIO_AUDIO_ROUTING(HSDIO_AudioRouting_HSDIOIN_NOOUT));}while (ret_val !=I2C_STS_SUCCESS);
+       do{ret_val=alpha_i2c_write(HSDIO_SYS_CFG_GO);}while (ret_val !=I2C_STS_SUCCESS);
+}
+
+/**
+ *  \brief    Fetch Video Sync Status from HSR41
+ *
+ *  This function retrieves the Video Sync status from HSR41
+ *  as part of the 'D10 initialization' sequence, prior to
+ *     any subsequent interaction.
+ *
+ *  \return    1 on Success
+ */
+
+unsigned int read_hdmi_videosyncstatus()
+{
+       unsigned char data[50];
+       Uint8 length=0;
+       int ret_val=0;
+
+       audk2g_delay(10);
+       ret_val=alpha_i2c_write(HSDIO_INPUT_SYNC_STS);
+       Log_info0("read_hdmi_videosyncstatus: After writing HSDIO_INPUT_SYNC_STS.");
+
+       if(ret_val ==I2C_STS_SUCCESS)
+       {
+               I2C_transactionInit(&i2cTransaction);
+               i2cTransaction.slaveAddress = HSR4_I2C_ADDR;
+               i2cTransaction.readBuf = &length;
+               i2cTransaction.readCount = 1;
+               i2cTransaction.timeout   = I2C_TRANSACTION_TIMEOUT;
+               ret_val = I2C_transfer(i2cHandle, &i2cTransaction);
+               if(ret_val ==I2C_STS_SUCCESS)
+               {
+                       Log_info1("read_hdmi_videosyncstatus: The read count is %d.",length);
+                       I2C_transactionInit(&i2cTransaction);
+                       i2cTransaction.slaveAddress = HSR4_I2C_ADDR;
+                       i2cTransaction.readBuf = &data[0];
+                       i2cTransaction.readCount = length;
+                       i2cTransaction.timeout   = I2C_TRANSACTION_TIMEOUT;
+                       ret_val = I2C_transfer(i2cHandle, &i2cTransaction);
+                       Log_info1("read_hdmi_videosyncstatus: returned status = 0x%x", data[2]);
+               }
+
+       }
+       else
+       {
+               gret_val++;
+               I2C_control(i2cHandle, I2C_CMD_RECOVER_BUS, &gI2cDelay);
+       }
+
+       if(ret_val == I2C_STS_SUCCESS) ret_val= data[2]; // 1-byte / indicates error status
+       else
+       {
+               gret_val++;
+               I2C_control(i2cHandle, I2C_CMD_RECOVER_BUS, &gI2cDelay);
+       }
+
+       return ret_val;
+}
+
+/**
+ *  \brief    Clear the HMINT status
+ *
+ *  This function clears the status of HMINT signal on HSR41.
+ *
+ *  \return    none
+ */
+void clear_hdmi_hmint()
+{
+       int ret_val=0;
+
+       audk2g_delay(10);
+       ret_val=alpha_i2c_write(HSDIO_ALERT_STS); //clear the interrupt on ~HMINT by reading the Alert Status register
+
+       if(ret_val !=I2C_STS_SUCCESS)
+               while(1);               // Control shouldn't be here
+
+       return;
+}
+
+/**
+ *  \brief    Retrieve the HDMI input interface rate
+ *
+ *  This function retrieves the input sample rate (or interface rate for bitstreams)
+ *  from the HSR41 card.
+ *
+ *  \return    HSDIO Sample Rate on Success
+ */
+Uint32 read_hdmi_samprate()
+{
+       unsigned char data[50];
+       Uint8 length;
+       int ret_val=7;
+
+       Log_info0("Audio DC CFG: Entered read_hdmi_samprate");
+       audk2g_delay(10);
+       ret_val=alpha_i2c_write(HSDIO_AUDIO_INPUT_FREQ_STS);\
+       if(ret_val==I2C_STS_SUCCESS)
+       {
+               I2C_transactionInit(&i2cTransaction);
+               i2cTransaction.slaveAddress = HSR4_I2C_ADDR;
+               i2cTransaction.readBuf = &length;
+               i2cTransaction.readCount = 1;
+               i2cTransaction.timeout   = I2C_TRANSACTION_TIMEOUT;
+               ret_val = I2C_transfer(i2cHandle, &i2cTransaction);
+               if(ret_val==I2C_STS_SUCCESS)
+               {
+                       I2C_transactionInit(&i2cTransaction);
+                       i2cTransaction.slaveAddress = HSR4_I2C_ADDR;
+                       i2cTransaction.readBuf = &data[0];
+                       i2cTransaction.readCount = length;
+                       i2cTransaction.timeout   = I2C_TRANSACTION_TIMEOUT;
+                       ret_val = I2C_transfer(i2cHandle, &i2cTransaction);
+               }
+
+       }
+       else
+               while(1);
+
+       Log_info0("Audio DC CFG: Leaving read_hdmi_samprate");
+
+       if(ret_val==I2C_STS_SUCCESS) ret_val= data[2]; // indicates sample rate
+       else
+       while(1);
+
+       return ret_val;
+}
+
+/**
+ *  \brief    Initializes the HSR41 HDMI repeater module
+ *
+ *  This function initializes and configures the HSR41 module
+ *  via the serial (I2C1) command interface for the necessary
+ *  audio operations.
+ *
+ *  \return    Audk2g_EOK on Success
+ */
+Audk2g_STATUS audioHDMIConfig(void)
+{
+       Audk2g_STATUS status = Audk2g_EOK;
+
+       I2C_HwAttrs   i2c_cfg;
+
+       /* Get the default I2C init configurations */
+       I2C_socGetInitCfg(HSR4_I2C_PORT_NUM, &i2c_cfg);
+
+       i2c_cfg.enableIntr = 0; // disable interrupt
+
+       /* Set the default I2C init configurations */
+       I2C_socSetInitCfg(HSR4_I2C_PORT_NUM, &i2c_cfg);
+
+    I2C_init();
+
+    I2C_Params_init(&i2cParams);
+    /* BitRate : 400 Kbps */
+    i2cParams.bitRate = I2C_400kHz;
+
+    i2cHandle = I2C_open(HSR4_I2C_PORT_NUM, &i2cParams);
+
+    Log_info0("Before EDID config.");
+    hrptredid();
+
+    Log_info0("Before HSR4 Clock config.");
+       hdmi128();
+
+       Log_info0("Before HSR4 Video Sync Detection.");
+
+       while((HSDIO_InSync_SYNC_DETECTED != read_hdmi_videosyncstatus()));
+
+       Log_info0("After HSR4 Video Sync Detection.");
+
+       return (status);
+}
+
+
+/* Nothing past this point */
similarity index 56%
rename from pasdk/test_dsp/sap/audio_dc_cfg.h
rename to pasdk/test_dsp/application/itopo/evmk2g/audio_dc_cfg.h
index c2fbb8cc3f38f920102263469d7f6c94306563a4..3199c94dc3899b6dfe7ff07bc461971b3e6442dd 100644 (file)
@@ -45,6 +45,10 @@ All rights reserved.
 
 #include "audk2g.h"
 #include "audk2g_audio.h"
+/* TI-RTOS Header files */
+#include <ti/drv/i2c/I2C.h>
+#include <ti/drv/i2c/soc/I2C_soc.h>
+
 /**
  *  \brief    ADC configuration parameter structure
  *
@@ -109,7 +113,7 @@ Audk2g_STATUS audioDacConfig(Audk2gDacDevId devId, DacConfig *config);
  *  This function initializes and configures the DIR modules
  *  on audio daughter card
  *
- *  \return    Platform_EOK on Success or error code
+ *  \return    Audk2g_STATUS on Success or error code
  */
 Audk2g_STATUS audioDirConfig(void);
 
@@ -119,18 +123,18 @@ Audk2g_STATUS audioDirConfig(void);
  *  This function initializes and configures the HDMI module
  *  with the audio daughter card
  *
- *  \return    Platform_EOK on Success or error code
+ *  \return    Audk2g_STATUS on Success
  */
 Audk2g_STATUS audioHDMIConfig(void);
 
 /**
- *  \brief    Read HDMI sampling rate
+ *  \brief    Read HDMI input sampling rate
  *
  */
 unsigned int read_hdmi_samprate();
 
 /**
- *  \brief    Clear HDMI interrupt on ~HMINT
+ *  \brief    Clear HDMI interrupt on ~HMINT line
  *
  */
 void clear_hdmi_hmint();
@@ -147,64 +151,7 @@ void clear_hdmi_hmint();
 #define Int32   int
 #define Int16   short
 #define Int8    char
-/* ------------------------------------------------------------------------ *
- *                                                                          *
- *  I2C Controller                                                          *
- *                                                                          *
- * ------------------------------------------------------------------------ */
-#define I2C_BASE                0x2530400U
-#define I2C_OAR                 *( volatile Uint32* )( I2C_BASE + 0x00 )
-#define I2C_ICIMR               *( volatile Uint32* )( I2C_BASE + 0x04 )
-#define I2C_ICSTR               *( volatile Uint32* )( I2C_BASE + 0x08 )
-#define I2C_ICCLKL              *( volatile Uint32* )( I2C_BASE + 0x0C )
-#define I2C_ICCLKH              *( volatile Uint32* )( I2C_BASE + 0x10 )
-#define I2C_ICCNT               *( volatile Uint32* )( I2C_BASE + 0x14 )
-#define I2C_ICDRR               *( volatile Uint32* )( I2C_BASE + 0x18 )
-#define I2C_ICSAR               *( volatile Uint32* )( I2C_BASE + 0x1C )
-#define I2C_ICDXR               *( volatile Uint32* )( I2C_BASE + 0x20 )
-#define I2C_ICMDR               *( volatile Uint32* )( I2C_BASE + 0x24 )
-#define I2C_ICIVR               *( volatile Uint32* )( I2C_BASE + 0x28 )
-#define I2C_ICEMDR              *( volatile Uint32* )( I2C_BASE + 0x2C )
-#define I2C_ICPSC               *( volatile Uint32* )( I2C_BASE + 0x30 )
-#define I2C_ICPID1              *( volatile Uint32* )( I2C_BASE + 0x34 )
-#define I2C_ICPID2              *( volatile Uint32* )( I2C_BASE + 0x38 )
-
-/* I2C Field Definitions */
-#define ICOAR_MASK_7                    0x007F
-#define ICOAR_MASK_10                   0x03FF
-#define ICSAR_MASK_7                    0x007F
-#define ICSAR_MASK_10                   0x03FF
-#define ICOAR_OADDR                     0x007f
-#define ICSAR_SADDR                     0x0050
-
-#define ICSTR_SDIR                      0x4000
-#define ICSTR_NACKINT                   0x2000
-#define ICSTR_BB                        0x1000
-#define ICSTR_RSFULL                    0x0800
-#define ICSTR_XSMT                      0x0400
-#define ICSTR_AAS                       0x0200
-#define ICSTR_AD0                       0x0100
-#define ICSTR_SCD                       0x0020
-#define ICSTR_ICXRDY                    0x0010
-#define ICSTR_ICRRDY                    0x0008
-#define ICSTR_ARDY                      0x0004
-#define ICSTR_NACK                      0x0002
-#define ICSTR_AL                        0x0001
-
-#define ICMDR_NACKMOD                   0x8000
-#define ICMDR_FREE                      0x4000
-#define ICMDR_STT                       0x2000
-#define ICMDR_IDLEEN                    0x1000
-#define ICMDR_STP                       0x0800
-#define ICMDR_MST                       0x0400
-#define ICMDR_TRX                       0x0200
-#define ICMDR_XA                        0x0100
-#define ICMDR_RM                        0x0080
-#define ICMDR_DLB                       0x0040
-#define ICMDR_IRS                       0x0020
-#define ICMDR_STB                       0x0010
-#define ICMDR_FDF                       0x0008
-#define ICMDR_BC_MASK                   0x0007
+
 
 #endif /* _AUDIO_DC_CFG_H_ */
 
index ecf000ac34943dd453e23a1e418ae58a51ce77c5..efc4046a0698ca3da96fbb0517b495cf3eb0c43a 100644 (file)
@@ -244,9 +244,6 @@ const struct
 // .............................................................................
 // execPAIOutNone
 #define CUS_SIGMA48_S \
-       rb32DECSourceSelect_3, \
-       writeDECSourceSelectNone, \
-       writePA3Await(rb32DECSourceDecode,ob32DECSourceDecodeNone), \
     writeOBSioSelectN(DEVOUT_NULL), \
     writePA3Await(rb32OBSioSelect,ob32OBSioSelect(DEVOUT_NULL)), \
     0xcdf0,execPAIOutNone
similarity index 98%
rename from pasdk/test_dsp/sap/sap_d10.c
rename to pasdk/test_dsp/application/itopo/evmk2g/sap_d10.c
index 66cb7cc82035b3d673cd2791c6df70a877b58049..92dfbbfb65c7a49ac6bebe68cdd0fcdf17f0904e 100644 (file)
@@ -47,8 +47,8 @@ All rights reserved.
 // a common control function (D10_sapControl), which handles the various
 // requests made by the PA framework.
 
-// A note about clocking. There are two different master clocks
-// available corresponding to the two primary input choices, DIR and ADC.
+// A note about clocking. There are three different master clocks
+// available corresponding to the three primary input choices: HDMI, DIR and ADC.
 //
 // DIR:
 //       . 512fs @ <= 48kHz
@@ -738,17 +738,21 @@ static inline XDAS_Int32 initD10 (DEV2_Handle device)
        status = audk2g_AudioInit(); // defined in in ti\addon\audk2g\src\audk2g.c
        if(status != Audk2g_EOK)
        {
-               Log_info0("Audio Init Failed!\n");
+               Log_info0("audk2g_AudioInit Failed!\n");
                return status;
        }
+       else
+               Log_info0("audk2g_AudioInit Passed!\n");
 
        status = (Audk2g_STATUS)audk2g_AudioInit_Extra();
        if(status != Audk2g_EOK)
        {
-               Log_info0("Audio Init Failed!\n");
+               Log_info0("audk2g_AudioInit_Extra Failed!\n");
                return status;
        }
-    
+       else
+               Log_info0("audk2g_AudioInit_Extra Passed!\n");
+
        /* Initialize Audio ADC module */
        status = audioAdcConfig(AUDK2G_ADC_DEVICE_ALL, &adcCfg);
        if(status != Audk2g_EOK)
@@ -756,6 +760,8 @@ static inline XDAS_Int32 initD10 (DEV2_Handle device)
                Log_info0("Audio ADC Configuration Failed!\n");
                return status;
        }
+       else
+               Log_info0("Audio ADC Configuration Passed!\n");
 
        /* Setup DIR 9001 for SPDIF input operation */
        //status = platformAudioSelectClkSrc(AUDIO_CLK_SRC_DIR);
@@ -765,9 +771,8 @@ static inline XDAS_Int32 initD10 (DEV2_Handle device)
                Log_info0("Audio DIR Init Failed!\n");
                return status;
        }
-       status = audk2g_AudioSelectClkSrc(AUDK2G_AUDIO_CLK_SRC_I2S);
-       audk2g_delay(5000); // Without delay between these 2 calls system aborts.
-       status = setAudioDacConfig();
+       else
+               Log_info0("Audio DIR Init Passed!\n");
 
 #if 1
        /* Setup HSR41 for HDMI input operation */
@@ -780,8 +785,14 @@ static inline XDAS_Int32 initD10 (DEV2_Handle device)
                Log_info0("Audio HDMI Init Failed!\n");
                return status;
        }
+       else
+               Log_info0("Audio HDMI Init Passed!\n");
 #endif
 
+       status = audk2g_AudioSelectClkSrc(AUDK2G_AUDIO_CLK_SRC_DIR);
+       audk2g_delay(50000); // Without delay between these 2 calls system aborts.
+       status = setAudioDacConfig();
+
        Log_info1("Leaving initD10 with status = %d", status);
 
     return status;
index 27039ab07db7bccaeca29af13fa21188ba408a5c..309f3f43d686ddb5fb88900424c386d38efcacac 100644 (file)
@@ -631,30 +631,14 @@ const IALG_MemRec inpMemTabPrimary[] =
     // SDRAM circular buffer
     // 2 buffers * 256 samples/buffer * 8 words/sample * 3 bytes/word
     {
-        (3 * 60 * 1024) + 2,                                    // size 184320 + 1 16-bit word for EDMA padding        // GJ Debug.
+        (3 * 60 * 1024) + 2,                                    // size 184320 + 1 16-bit word for EDMA padding
         //180 * 1024,                                           // size
         //6 * 60 * 1024,                                        // size
         128,                                                    // alignment
                IALG_SARAM_SHM, //IALG_EXTERNAL_SHM, //IALG_SARAM2, //IALG_SARAM1, //IALG_EXTERNAL,                           // space
         IALG_PERSIST,                                           // attrs
         NULL,                                                   // base
-     },
-
-        // GJ Debug: The below is not required; hence 0
-
-#if 0
-       // IRAM scratch memory for autodetection and stereo PCM input
-    // High watermark needs are set by the latter:
-    // double buffer stereo 32bit PCM input 512 max frame size
-    // 1 buffers * 512 samples/buffer * 2 words/sample * 4 bytes/word
-    {
-        0 * 1024,                                              // size
-        128,                                                   // alignment
-               IALG_EXTERNAL_SHM,                                            // space
-        IALG_SCRATCH,                                          // attrs
-        NULL,                                                  // base
-    }
-#endif
+     }
 
 };
 
index 08c4ba815bd13d19e5bd6997a4e3f43e107be43f..520db2d96249d578b47d249eb239238a09004074 100644 (file)
@@ -71,26 +71,7 @@ extern const ti_sysbios_heaps_HeapMem_Handle heapMemDdr3;
 #define HEAPMALLOC (IHeap_Handle)heapMemDdr3
 extern HeapMem_Handle DEV2_memSpaceToHeap (IALG_MemSpace space);
 
-#if 0
-#if ((PAF_DEVICE&0xFF000000) == 0xD8000000)
-#ifndef dMAX_CFG
-#include <dap_dmax.h>
-#else
-#include <dmax_struct.h>
-#include <dmax_params.h>
-#endif /* dMAX_CFG */
-#include "psdkaf_hjt.h"
-extern Uint32 DAT_cacheop_and_copy (void *src, void *dst, Uint16 byteCnt);
-#undef DAT_copy
-#define DAT_copy DAT_cacheop_and_copy
-#else
-#include "pafhjt.h"
-#include "dmax_dat.h" // this has to come after pafhjt
-#endif
-
-#else
 #include "pafhjt.h"
-#endif
 
 #include <ti/sysbios/knl/Clock.h>
 #include <xdc/runtime/Log.h>
@@ -283,9 +264,7 @@ static const MdUns iecFrameLength[23] =
 
 // This is used at a couple of locations to ensure the transfer
 // size is sufficiently long to be useful.
-//#define NOMINAL_XFERSIZE         128
 #define NOMINAL_XFERSIZE         128 //GJ Debug
-//#define NOMINAL_XFERSIZE         512 //GJ Debug
 
 #define min(a, b)  (((a) < (b)) ? (a) : (b))
 #define max(a, b)  (((a) > (b)) ? (a) : (b))
@@ -358,42 +337,7 @@ Int DIB_issue (DEV2_Handle device)
 
     Queue_put (device->fromdevice, (Queue_Elem *)srcFrame);
 
-//GJ: PAF_SIO_REQUEST_AUTO, Not Supported, yet.
-    if (srcFrame->arg == PAF_SIO_REQUEST_AUTO) {
-#if 0
-        // if not yet running, prime input buffer
-        if (pDevExt->syncState == SYNC_NONE) {
-
-            status = DIB_FTABLE_reset (device, pBufConfig);
-            if (status)
-                return status;
-
-            pDevExt->sourceProgram = PAF_SOURCE_UNKNOWN;
-
-            status = DIB_FTABLE_issueChild (device, &pDevExt->bufConfig, pDevExt->autoRequestSize, 0);
-            if (status)
-                return status;
-
-            // * also reset pDevExt->zeroCount, as in DIB_getSync()?
-            // just for PAF_SOURCE_PCMAUTO? *
-            pDevExt->pcmTimeout =
-                pDevExt->sourceSelect == PAF_SOURCE_PCMAUTO ? 0 :
-                2 * pBufConfig->pBufStatus->unknownTimeout;
-            pDevExt->syncState = SYNC_AUTO;
-
-            // allows PCM decoder to be used to generate zero-valued audio frames while scanning
-            pBufConfig->deliverZeros = 1;
-        }
-        // no action if already sync'ed
-        else if (pDevExt->syncState != SYNC_AUTO)
-            return 0;
-
-        status = DIB_FTABLE_issueChild (device, &pDevExt->bufConfig, pDevExt->autoRequestSize, 0);
-        if (status)
-            return status;
-#endif
-    }
-    else if (srcFrame->arg == PAF_SIO_REQUEST_NEWFRAME) {
+    if (srcFrame->arg == PAF_SIO_REQUEST_NEWFRAME) {
 
         // do nothing if not synced since syncing done in reclaim
         // This is executed in force modes from the first call to PAF_AST_decodeInit
@@ -413,8 +357,8 @@ Int DIB_issue (DEV2_Handle device)
 // Although interface allows for arbitrary BufConfigs we only support 1 -- so
 // we can assume the one on the fromdevice is the one we want
 
-extern int gIsrInputCnt; // GJ Debug
-extern int gIsrOutputCnt; // GJ Debug
+extern int gIsrInputCnt;
+extern int gIsrOutputCnt;
 
 Int DIB_reclaim (DEV2_Handle device)
 {
@@ -443,78 +387,9 @@ Int DIB_reclaim (DEV2_Handle device)
 
     // .........................................................................
 
-    if (dstFrame->arg == PAF_SIO_REQUEST_AUTO) {
-//GJ: PAF_SIO_REQUEST_AUTO - not supported, yet.
-#if 0
-        Log_info0("DIB: At case = PAF_SIO_REQUEST_AUTO"); // GJ Debug
-
-        // verify set up by prior DIB_issue()
-        // no action if already sync'ed
-        if (pDevExt->syncState == SYNC_NONE)
-            return DIBERR_AUTO;
-        else if (pDevExt->syncState != SYNC_AUTO)
-            return 0;
-
-        // get next block of data to scan
-        status = DIB_FTABLE_waitForData (device, &pDevExt->bufConfig, pDevExt->autoRequestSize);
-        if (status)
-            return status;
-
-        if (pDevExt->sourceSelect == PAF_SOURCE_NONE) {
-            IncrementPtr (pBufConfig, &pDevExt->bufConfig.pntr.pVoid, pDevExt->autoRequestSize);
-            return 0;
-        }
-
-        // this function updates the tail pointer; it WON'T reset to SYNC_NONE
-        status = DIB_FTABLE_syncScan (device, &pDevExt->bufConfig, &pDevExt->pcmTimeout);
-        if (status)
-            return status;
-
-        // if not yet sync'ed ...
-        if (pDevExt->syncState == SYNC_AUTO) {
-            // if timeout, harness tail of DIB_getSync()
-            if (!pDevExt->pcmTimeout) {
-
-                // checks pDevExt->zeroCount, runs DIB_reset(),
-                // updates pBufConfig->deliverZeros/sizeofElement/sizeofBuffer,
-                // sets pDevExt->sourceProgram = PAF_SOURCE_PCM/DSD?
-                //  and pDevExt->syncState = SYNC_PCM[_FORCED]
-                status = DIB_FTABLE_getSync (device, &pDevExt->bufConfig);
-                if (status)
-                    return status;
-            }
-        }
-
-        // if sync'ed to bitstream, this requests add'l input;
-        // if PCM, this "kickstarts" the input,
-        // using settings per above call to DIB_getSync()
-        if (pDevExt->syncState != SYNC_AUTO) {
-
-            status = DIB_FTABLE_initFrame (device, &pDevExt->bufConfig);
-            if (status)
-                return status;
-
-            // this situation may occur for various IEC types,
-            // w/ no matching PAF_SOURCE_ type is defined
-            // (see iecPafSource[] table for the latter mapping)
-            // most like cases are null & pause packets
-            if (pDevExt->sourceProgram == PAF_SOURCE_UNKNOWN)
-                return DIBERR_SYNC;
-
-            // request timing frame
-            status = DIB_FTABLE_requestFrame (device, &pDevExt->bufConfig);
-            if (status)
-                return status;
-        }
-
-#endif
-    } //dstFrame->arg == PAF_SIO_REQUEST_AUTO
-
-    // .........................................................................
-
     if ((pDevExt->syncState == SYNC_NONE) || (dstFrame->arg == PAF_SIO_REQUEST_SYNC)) {
 
-        Log_info0("DIB: At case: syncState == SYNC_NONE (or PAF_SIO_REQUEST_SYNC)");  // GJ Debug
+        Log_info0("DIB: At case: syncState == SYNC_NONE (or PAF_SIO_REQUEST_SYNC)");
 
         // pass in external buffer config which used to initialize the internal view
         status = DIB_FTABLE_reset (device, pBufConfig);
@@ -530,7 +405,7 @@ Int DIB_reclaim (DEV2_Handle device)
         // (i.e. no need to reset it here)
         if (pDevExt->syncState == SYNC_NONE)
         {
-            Log_info0("Returning DIBERR_SYNC after DIB_FTABLE_getSync"); // GJ Debug
+            Log_info0("Returning DIBERR_SYNC after DIB_FTABLE_getSync");
             return DIBERR_SYNC;
         }
 
@@ -539,7 +414,7 @@ Int DIB_reclaim (DEV2_Handle device)
 
         if (status)
         {
-            Log_info1("Returning %d after DIB_FTABLE_initFrame", status); // GJ Debug
+            Log_info1("Returning %d after DIB_FTABLE_initFrame", status);
             return status;
         }
 
@@ -547,7 +422,7 @@ Int DIB_reclaim (DEV2_Handle device)
         status = DIB_FTABLE_requestFrame (device, &pDevExt->bufConfig);
         if (status)
         {
-            Log_info1("Returning %d after DIB_FTABLE_requestFrame", status); // GJ Debug
+            Log_info1("Returning %d after DIB_FTABLE_requestFrame", status);
             return status;
         }
         // update external view of bufConfig. In particular for slave force PCM
@@ -562,13 +437,13 @@ Int DIB_reclaim (DEV2_Handle device)
 
     if (dstFrame->arg == PAF_SIO_REQUEST_NEWFRAME) {
 
-        Log_info0("DIB: At case = PAF_SIO_REQUEST_NEWFRAME"); // GJ Debug
+        Log_info0("DIB: At case = PAF_SIO_REQUEST_NEWFRAME");
 
         // wait for enough data to check for sync at expected location
         status = DIB_FTABLE_waitForData (device, &pDevExt->bufConfig, pDevExt->bufConfig.frameLength);
         if (status)
         {
-            Log_info2("DIB_reclaim.%d DIB_FTABLE_waitForData returned %d", __LINE__, status); // GJ Debug
+            Log_info2("DIB_reclaim.%d DIB_FTABLE_waitForData returned %d", __LINE__, status);
             //TRACE((&TR_MOD, "DIB_reclaim.%d DIB_FTABLE_waitForData returned %d\n", __LINE__, status));
             return status;
         }
@@ -601,7 +476,7 @@ Int DIB_reclaim (DEV2_Handle device)
                 status = DIB_FTABLE_syncScan (device, pBufConfig, &pDevExt->pcmTimeout);
                 if (status) {
                     pDevExt->sourceProgram = PAF_SOURCE_UNKNOWN;
-                    Log_info2("DIB_reclaim.%d DIB_FTABLE_syncScan returned %d", __LINE__, status); // GJ Debug
+                    Log_info2("DIB_reclaim.%d DIB_FTABLE_syncScan returned %d", __LINE__, status);
                     //TRACE((&TR_MOD, "DIB_reclaim.%d DIB_FTABLE_syncScan returned %d\n", __LINE__, status));
                     return status;
                 }
@@ -609,7 +484,7 @@ Int DIB_reclaim (DEV2_Handle device)
                 // if scan found something other than PCM, then exit with error
                 if (pDevExt->syncState != SYNC_PCM)
                 {
-                    Log_info1("DIB_reclaim.%d error: syncState != SYNC_PCM", __LINE__); // GJ Debug
+                    Log_info1("DIB_reclaim.%d error: syncState != SYNC_PCM", __LINE__);
                     //TRACE((&TR_MOD, "DIB_reclaim.%d error: syncState != SYNC_PCM\n", __LINE__));
                     return DIBERR_SYNC;
                 }
@@ -618,7 +493,7 @@ Int DIB_reclaim (DEV2_Handle device)
                 if ((ibMode == MODE_DEFAULT) &&
                     (pDevExt->zeroCount >= 2*pBufConfig->pBufStatus->zeroRunRestart)) {
                     // if zeroRunRestart me then reset input to unknown
-                    Log_info1("DIB_reclaim.%d error: zeroRunRestart, setting PAF_SOURCE_UNKNOWN", __LINE__); // GJ Debug
+                    Log_info1("DIB_reclaim.%d error: zeroRunRestart, setting PAF_SOURCE_UNKNOWN", __LINE__);
                     //TRACE((&TR_MOD, "DIB_reclaim.%d error: zeroRunRestart, setting PAF_SOURCE_UNKNOWN\n", __LINE__));
                     pDevExt->sourceProgram = PAF_SOURCE_UNKNOWN;
                     return DIBERR_SYNC;
@@ -649,14 +524,14 @@ Int DIB_reclaim (DEV2_Handle device)
         // since, at least for THD, it is needed by decoders.
         *pBufConfig = pDevExt->bufConfig;
         pBufConfig->lengthofData -= pDevExt->headerSize;
-        Log_info4("DIB_reclaim.%d lengthofData = %d; InISRCNT=%d; OutISRCNT=%d", __LINE__, pBufConfig->lengthofData, gIsrInputCnt, gIsrInputCnt); // GJ Debug
+        Log_info4("DIB_reclaim.%d lengthofData = %d; InISRCNT=%d; OutISRCNT=%d", __LINE__, pBufConfig->lengthofData, gIsrInputCnt, gIsrInputCnt);
         //TRACE((&TR_MOD, "DIB_reclaim.%d lengthofData = %d\n", __LINE__, pBufConfig->lengthofData));
 
         // HACK: for DSD the frameLength needs to be the number of samples to generate.
         if ((pDevExt->sourceSelect >= PAF_SOURCE_DSD1) &&
             (pDevExt->sourceSelect <= PAF_SOURCE_DSD3))
             pBufConfig->frameLength /= pBufConfig->stride;
-        Log_info2("DIB_reclaim.%d frameLength = %d", __LINE__, pBufConfig->frameLength); // GJ Debug
+        Log_info2("DIB_reclaim.%d frameLength = %d", __LINE__, pBufConfig->frameLength);
         //TRACE((&TR_MOD, "DIB_reclaim.%d frameLength = %d\n", __LINE__, pBufConfig->frameLength));
 
         // set external view to point at synch position of the frame guaranteed
@@ -683,13 +558,13 @@ Int DIB_reclaim (DEV2_Handle device)
         if (status) {
             if (pBufConfig->pBufStatus->lastFrameMask & (1 << pDevExt->sourceProgram)) {
                 pDevExt->deferredError = status;
-                Log_info1("DIB_reclaim.%d last frame\n", __LINE__); // GJ Debug
+                Log_info1("DIB_reclaim.%d last frame\n", __LINE__);
                 //TRACE((&TR_MOD, "DIB_reclaim.%d last frame\n", __LINE__));
                 pBufConfig->pBufStatus->lastFrameFlag = 1;
                 return 0;
             }
             else {
-                Log_info1("DIB_reclaim.%d setting PAF_SOURCE_UNKNOWN", __LINE__); // GJ Debug
+                Log_info1("DIB_reclaim.%d setting PAF_SOURCE_UNKNOWN", __LINE__);
                 //TRACE((&TR_MOD, "DIB_reclaim.%d setting PAF_SOURCE_UNKNOWN\n", __LINE__));
                 pDevExt->sourceProgram = PAF_SOURCE_UNKNOWN;
                 return status;
@@ -700,7 +575,7 @@ Int DIB_reclaim (DEV2_Handle device)
 
     // .........................................................................
 
-    Log_info4("DIB_reclaim.%d exit status = %d, InISRCNT = %d OutISRCNT = %d", __LINE__, status, gIsrInputCnt, gIsrOutputCnt); // GJ Debug
+    Log_info4("DIB_reclaim.%d exit status = %d, InISRCNT = %d OutISRCNT = %d", __LINE__, status, gIsrInputCnt, gIsrOutputCnt);
     //TRACE((&TR_MOD, "DIB_reclaim.%d exit status = %d\n", __LINE__, status));
 
     return status;
@@ -1010,7 +885,7 @@ Int DIB_getSync (DEV2_Handle device, PAF_InpBufConfig *pBufConfig )
             }
             else
             {
-                Log_info3("DIB: Inside DIB_getSync with syncState != SYNC_ONE. localTimeout = %d, syncBufSize  = %d, timeout = %d", localTimeout,syncBufSize, timeout); // GJ Debug
+                Log_info3("DIB: Inside DIB_getSync with syncState != SYNC_ONE. localTimeout = %d, syncBufSize  = %d, timeout = %d", localTimeout,syncBufSize, timeout);
                 localTimeout -= syncBufSize;
             }
         }
@@ -1173,11 +1048,11 @@ Int DIB_issueChild (DEV2_Handle device, PAF_InpBufConfig  *pBufConfig, int size,
                 return DIBERR_UNSPECIFIED;
 
             pBufConfig->futureHead.pVoid = endAddr[i];
-            // GJ Debug
+
             if (i==1)
             {
                gWrapCtr++;
-               Log_info4("DIB: Inside DIB_issueChild Wrap Around Point #%d, with Future Head: 0x%x, current addr: 0x%x, current size: %d", gWrapCtr, pBufConfig->futureHead.pVoid, dstFrame->addr, dstFrame->size ); // GJ Debug
+               Log_info4("DIB: Inside DIB_issueChild Wrap Around Point #%d, with Future Head: 0x%x, current addr: 0x%x, current size: %d", gWrapCtr, (xdc_IArg)pBufConfig->futureHead.pVoid, (xdc_IArg)dstFrame->addr, dstFrame->size );
 
             }
         }
@@ -1195,26 +1070,26 @@ Int DIB_reclaimChild (DEV2_Handle device, PAF_InpBufConfig *pBufConfig)
     DEV2_Frame              *srcFrame;
     int                     status, bufEnd;
 
-    //Log_info3("DIB_reclaimChild.%d: Inside DEV2_reclaim(pChild) pChild = 0x%x DEV2_reclaim = 0x%x", __LINE__, pChild, &pChild->fxns.reclaim); // GJ Debug
+    //Log_info3("DIB_reclaimChild.%d: Inside DEV2_reclaim(pChild) pChild = 0x%x DEV2_reclaim = 0x%x", __LINE__, pChild, &pChild->fxns.reclaim);
     //TRACE((&TR_MOD, "DIB_reclaimChild.%d: calling DEV2_reclaim(pChild) pChild = 0x%x DEV2_reclaim = 0x%x", __LINE__, pChild, &pChild->fxns.reclaim));
     status = DEV2_reclaim (pChild);
     if (status)
     {
-        Log_info2("DIB_reclaimChild.%d DEV2_reclaim() returned (%d) DIBERR_UNSPECIFIED", __LINE__, status); // GJ Debug
+        Log_info2("DIB_reclaimChild.%d DEV2_reclaim() returned (%d) DIBERR_UNSPECIFIED", __LINE__, status);
         //TRACE((&TR_MOD, "DIB_reclaimChild.%d DEV2_reclaim() returned (%d) DIBERR_UNSPECIFIED \n", __LINE__, status));
         return DIBERR_UNSPECIFIED;
     }
 
-    //Log_info1("DIB_reclaimChild.%d calling Queue_get()", __LINE__); // GJ Debug
+    //Log_info1("DIB_reclaimChild.%d calling Queue_get()", __LINE__);
     //TRACE((&TR_MOD, "DIB_reclaimChild.%d calling Queue_get()\n", __LINE__));
     srcFrame = Queue_get (pChild->fromdevice);
-    //Log_info2("DIB_reclaimChild.%d calling Queue_put(), srcFrame = 0x%x", __LINE__, srcFrame); // GJ Debug
+    //Log_info2("DIB_reclaimChild.%d calling Queue_put(), srcFrame = 0x%x", __LINE__, srcFrame);
     //TRACE((&TR_MOD, "DIB_reclaimChild.%d calling Queue_put(), srcFrame = 0x%x\n", __LINE__, srcFrame));
     Queue_put (Queue_handle(&((SIO2_Handle) pChild)->framelist), (Queue_Elem *)srcFrame);
 
     // Only for non-fill requests do we update ptrs
     if (srcFrame->addr != NULL) {
-        //Log_info2("DIB_reclaimChild.%d update pointers with srcFrame->size = %d", __LINE__, srcFrame->size); // GJ Debug
+        //Log_info2("DIB_reclaimChild.%d update pointers with srcFrame->size = %d", __LINE__, srcFrame->size);
         //TRACE((&TR_MOD, "DIB_reclaimChild.%d update pointers\n", __LINE__));
         pBufConfig->head.pVoid = (Ptr) ((int)srcFrame->addr + srcFrame->size);
 
@@ -1222,13 +1097,13 @@ Int DIB_reclaimChild (DEV2_Handle device, PAF_InpBufConfig *pBufConfig)
         bufEnd = (int) pBufConfig->base.pVoid + pBufConfig->sizeofBuffer;
         if( (int) pBufConfig->head.pVoid >= bufEnd )
         {
-            Log_info1("DIB_reclaimChild.%d wrap pointer", __LINE__); // GJ Debug
+            Log_info1("DIB_reclaimChild.%d wrap pointer", __LINE__);
             //TRACE((&TR_MOD, "DIB_reclaimChild.%d wrap pointer\n", __LINE__));
             pBufConfig->head.pVoid = (Ptr) ((int) pBufConfig->base.pVoid + (int) pBufConfig->head.pVoid - bufEnd);
         }
     }
 
-    Log_info2("DIB_reclaimChild.%d exit with status = %d", __LINE__, status); // GJ Debug
+    Log_info2("DIB_reclaimChild.%d exit with status = %d", __LINE__, status);
     //TRACE((&TR_MOD, "DIB_reclaimChild.%d exit with status = %d\n", __LINE__, status));
 
     return status;
@@ -1420,7 +1295,7 @@ Int DIB_syncScan (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt32
     // if scratch buffer present then assume it is needed for paging
     pageSize = numLeft*pBufConfig->sizeofElement;
 
-    Log_info3("DIB: Entered DIB_syncScan with pTail = 0x%x & numLeft = %d, timeout = %d", pTail, numLeft, *pTimeout); // GJ Debug
+    Log_info3("DIB: Entered DIB_syncScan with pTail = 0x%x & numLeft = %d, timeout = %d", (xdc_IArg)pTail, numLeft, *pTimeout);
 
 
     if ((pAlgConfig->numRec > 1) && pAlgConfig->pMemRec[1].base && (pAlgConfig->pMemRec[1].size >= pageSize)) {
@@ -1430,7 +1305,7 @@ Int DIB_syncScan (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt32
     }
 
     if (pBufConfig->sizeofElement == 4) {
-        Log_info0("DIB: SyncScan - Inside pBufConfig->sizeofElement == 4"); // GJ Debug
+        Log_info0("DIB: SyncScan - Inside pBufConfig->sizeofElement == 4");
         stride = 2;
         pTail += 1; // point at MSB
         pShadowTail += 1;
@@ -1446,7 +1321,7 @@ Int DIB_syncScan (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt32
     scanState = pDevExt->scanState;
     pSync     = pDevExt->pSync.pMdInt;
 
-    Log_info4("DIB: Entered DIB_syncScan with zeroCount = %d & scanState = %d, stride = %d, pSync = 0x%x", zeroCount, scanState, stride, pSync); // GJ Debug
+    Log_info4("DIB: Entered DIB_syncScan with zeroCount = %d & scanState = %d, stride = %d, pSync = 0x%x", zeroCount, scanState, stride, (xdc_IArg)pSync);
 
     // scan until out of available data or a sync found
     for (i=0; i < numLeft; i++) {
@@ -1488,7 +1363,7 @@ Int DIB_syncScan (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt32
             //    . the last sample was non-zero
             if (scanCount || (tail != 0x0000) || timeoutChanged)
             {
-                //Log_info3("DIB: DIB_syncScan scanCount = %d tail = %d timeoutChanged = %d", scanCount, tail, timeoutChanged); // GJ Debug
+                //Log_info3("DIB: DIB_syncScan scanCount = %d tail = %d timeoutChanged = %d", scanCount, tail, timeoutChanged);
                 scanCount += 1;
             }
 
@@ -1575,11 +1450,11 @@ Int DIB_syncScan (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt32
                 if (tail == IEC_PB) {
                     scanState = SCANNED_IEC_PB;
                     scanCount += 1;
-                    Log_info0("DIB: SyncScan Inside case - SCANNED_IEC_PA - if path"); // GJ Debug
+                    Log_info0("DIB: SyncScan Inside case - SCANNED_IEC_PA - if path");
                 }
                 else
                 {
-                    Log_info0("DIB: SyncScan Inside case - SCANNED_IEC_PA - else path"); // GJ Debug
+                    Log_info0("DIB: SyncScan Inside case - SCANNED_IEC_PA - else path");
                     scanState = SCANNED_NONE;
                 }
                 break;
@@ -1611,7 +1486,7 @@ Int DIB_syncScan (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt32
                 pc = *pLocalTail & 0x1F;
                 pDevExt->headerSize = IEC_HEADER_SIZE;
 
-                Log_info0("DIB: Sync Scan - Inside case: SCANNED_IEC_PC"); // GJ Debug
+                Log_info0("DIB: Sync Scan - Inside case: SCANNED_IEC_PC");
                 // Handle DTSHD subtype (LBR)
                 if (pc == 0x11) {
                     pDevExt->headerSize +=6;
@@ -1632,7 +1507,7 @@ Int DIB_syncScan (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt32
                 // don't know how to support other types
                 if (pc > 22)
                 {
-                    Log_info1("DIB:  Unknown IEC type 0x%x encountered.\n", pc); // GJ Debug
+                    Log_info1("DIB:  Unknown IEC type 0x%x encountered.\n", pc);
                     return DIBERR_SYNC;
                 }
 
@@ -1640,7 +1515,7 @@ Int DIB_syncScan (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt32
                 pBufConfig->pntr.pMdInt = pSync;
                 pDevExt->sourceProgram = iecPafSource[pc];
 
-                Log_info2("source is %d.  pc is %d.", iecPafSource[pc], pc); // GJ Debug 
+                Log_info2("source is %d.  pc is %d.", iecPafSource[pc], pc);
                 //TRACE((&TR_MOD, "source is %d.  pc is %d.\n", iecPafSource[pc], pc));
 
                 if (pc == 0x11 && DTSHDSubType == 3 && (PAF_ASP_sampleRateHzTable[pBufConfig->pBufStatus->sampleRateStatus][PAF_SAMPLERATEHZ_STD] <=48000.0))
@@ -1663,7 +1538,7 @@ Int DIB_syncScan (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt32
     // .............................................................................
 
 syncScanExit:
-    Log_info4("DIB inside syncScanExit.  pTimeout = %d, scanCount = %d, zeroCount = %d, numLeft = %d", *pTimeout,scanCount, zeroCount, numLeft ); // GJ Debug
+    Log_info4("DIB inside syncScanExit.  pTimeout = %d, scanCount = %d, zeroCount = %d, numLeft = %d", *pTimeout,scanCount, zeroCount, numLeft );
     pDevExt->zeroCount    = zeroCount;
     pDevExt->scanState    = scanState;
     pDevExt->pSync.pMdInt = pSync;
@@ -2001,7 +1876,7 @@ Int DIB_waitForData (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt
     DEV2_Handle            pChild = (DEV2_Handle) &pDevExt->child;
     Int status, lock;
 
-    Log_info2("DIB_waitForData.%d count = %d", __LINE__, count); // GJ Debug
+    Log_info2("DIB_waitForData.%d count = %d", __LINE__, count);
     //TRACE((&TR_MOD, "DIB_waitForData.%d count = %d\n", __LINE__, count));
 
     while (GetNumAvail(pBufConfig) < count) {
@@ -2012,7 +1887,7 @@ Int DIB_waitForData (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt
         status = SIO2_ctrl (pChild, (Uns)PAF_SIO_CONTROL_GET_INPUT_STATUS, (Arg) &inputStatus);
         if (status)
         {
-            Log_info2("DIB_waitForData.%d SIO2_ctrl() returned %d", __LINE__, status); // GJ Debug
+            Log_info2("DIB_waitForData.%d SIO2_ctrl() returned %d", __LINE__, status);
             //TRACE((&TR_MOD, "DIB_waitForData.%d SIO2_ctrl() returned %d\n", __LINE__, status));
             return status;
         }
@@ -2020,14 +1895,14 @@ Int DIB_waitForData (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt
 #ifndef IGNORE_LOCK_OVERRIDE
         if ((pBufConfig->pBufStatus->lockOverride & (XDAS_Int8)0x80) == 0)
         {
-            Log_info1("DIB_waitForData.%d lock = lockOverride\n", __LINE__); // GJ Debug
+            Log_info1("DIB_waitForData.%d lock = lockOverride\n", __LINE__);
             //TRACE((&TR_MOD, "DIB_waitForData.%d lock = lockOverride\n", __LINE__));
             lock = pBufConfig->pBufStatus->lockOverride;
         }
 #endif
         if (!lock)
         {
-            Log_info1("DIB_waitForData.%d no lock, return DIBERR_SYNC\n", __LINE__); // GJ Debug
+            Log_info1("DIB_waitForData.%d no lock, return DIBERR_SYNC\n", __LINE__);
             //TRACE((&TR_MOD, "DIB_waitForData.%d no lock, return DIBERR_SYNC\n", __LINE__));
             return DIBERR_SYNC;
         }
@@ -2036,18 +1911,18 @@ Int DIB_waitForData (DEV2_Handle device, PAF_InpBufConfig *pBufConfig, XDAS_UInt
         if (pDevExt->pDecodeStatus) {
             if (pDevExt->pDecodeStatus->sourceSelect == PAF_SOURCE_NONE)
             {
-                Log_info1("DIB_waitForData.%d sourceSelect is NONE, return DIBERR_SYNC", __LINE__); // GJ Debug
+                Log_info1("DIB_waitForData.%d sourceSelect is NONE, return DIBERR_SYNC", __LINE__);
                 //TRACE((&TR_MOD, "DIB_waitForData.%d sourceSelect is NONE, return DIBERR_SYNC\n", __LINE__));
                 return DIBERR_SYNC;
             }
         }
 
-        Log_info1("DIB_waitForData.%d calling DIB_FTABLE_reclaimChild()", __LINE__); // GJ Debug
+        Log_info1("DIB_waitForData.%d calling DIB_FTABLE_reclaimChild()", __LINE__);
         //TRACE((&TR_MOD, "DIB_waitForData.%d calling DIB_FTABLE_reclaimChild()\n", __LINE__));
         status = DIB_FTABLE_reclaimChild (device, pBufConfig);
         if(status)
         {
-            Log_info2("DIB_waitForData.%d DIB_FTABLE_reclaimChild() returned %d", __LINE__, status); // GJ Debug
+            Log_info2("DIB_waitForData.%d DIB_FTABLE_reclaimChild() returned %d", __LINE__, status);
             //TRACE((&TR_MOD, "DIB_waitForData.%d DIB_FTABLE_reclaimChild() returned %d\n", __LINE__, status));
             return status;
         }
index 7eac297a288dba5f215aea8a1e66faf53df6c973..e4c29da4c6ed88852d157ea5e387215376896c22 100644 (file)
@@ -168,7 +168,7 @@ Int DOB_close (DEV2_Handle device)
     return (SIO2_EBADIO);
 } // DOB_close
 
-// GJ Debug Counters
+// Debug Counters
 Uint32 gMobStart_Idle=0;
 Uint32 gMobIdle_Ctrl=0;
 Uint32 gMobIdle_API=0;
diff --git a/pasdk/test_dsp/sap/audio_dc_cfg.c b/pasdk/test_dsp/sap/audio_dc_cfg.c
deleted file mode 100644 (file)
index 51d5ec7..0000000
+++ /dev/null
@@ -1,801 +0,0 @@
-
-/*
-Copyright (c) 2017, Texas Instruments Incorporated - http://www.ti.com/
-All rights reserved.
-
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-*/
-
-/**
- * \file      audio_dc_config.c
- *
- * \brief     Configures Audio daughter card HW modules
- *
- */
-
-#include "audio_dc_cfg.h"
-#include "vproccmds_a.h"
-#include <stdarg.h>
-#include "string.h"
-#include <xdc/runtime/Log.h>
-#include "audk2g_audio.h"
-
-
-Audk2g_STATUS audioHDMIConfig(void);
-
-#define HSR4_I2C_ADDR 0x5D
-#define        HSR4_I2C_PORT_NUM I2C_PORT_1
-
-Int16 DA10x_I2C_init();
-Int16 DA10x_I2C_close();
-void DA10x_waitusec( Uint32);
-Int16 DA10x_I2C_reset();
-Int16 DA10x_I2C_write( Uint16, Uint8*, Uint16);
-Int16 DA10x_I2C_read( Uint16, Uint8*, Uint16);
-/* ------------------------------------------------------------------------ *
- *  Prototypes                                                              *
- * ------------------------------------------------------------------------ */
-
-/**
- *  \brief    Initializes ADC module
- *
- *  This function initializes and configures the ADC modules
- *  on audio daughter card
- *
- *  \param     devId  [IN]  ADC Device Id
- *  \param     config [IN]  ADC configuration parameters
- *
- *  \return    Platform_EOK on Success or error code
- */
-Audk2g_STATUS audioAdcConfig(Audk2gAdcDevId  devId, AdcConfig *config)
-{
-       Audk2g_STATUS status;
-
-       if(config == NULL)
-       {
-               IFPRINT(audk2g_write("Invalid Inputs\n"));
-               return (Audk2g_EINVALID);
-       }
-
-       /* Initialize all the HW instances of ADC */
-       status = audk2g_AudioAdcInit(devId);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcInit Failed\n"));
-               return (status);
-       }
-
-       /* Set ADC channel gain */
-       status = audk2g_AudioAdcSetGain(devId, AUDK2G_ADC_CH_ALL, config->gain);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcSetGain Failed\n"));
-               return (status);
-       }
-
-       /* Configure Left input mux for ADC1L */
-       status = audk2g_AudioAdcSetLeftInputMux(devId, AUDK2G_ADC_CH1_LEFT,
-                                                config->adc1LMux);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcSetLeftInputMux Failed\n"));
-               return (status);
-       }
-
-       /* Configure Left input mux for ADC2L*/
-       status = audk2g_AudioAdcSetLeftInputMux(devId, AUDK2G_ADC_CH2_LEFT,
-                                                config->adc2LMux);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcSetLeftInputMux Failed\n"));
-               return (status);
-       }
-
-       /* Configure Right input mux for ADC1R */
-       status = audk2g_AudioAdcSetRightInputMux(devId, AUDK2G_ADC_CH1_RIGHT,
-                                                 config->adc1RMux);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcSetRightInputMux Failed\n"));
-               return (status);
-       }
-
-       /* Configure Right input mux for ADC2R */
-       status = audk2g_AudioAdcSetRightInputMux(devId, AUDK2G_ADC_CH2_RIGHT,
-                                                 config->adc2RMux);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcSetRightInputMux Failed\n"));
-               return (status);
-       }
-
-       /* Configure audio data format */
-       status = audk2g_AudioAdcDataConfig(devId, config->wlen, config->format);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcDataConfig Failed\n"));
-               return (status);
-       }
-
-       /* Configure all the interrupts */
-       status = audk2g_AudioAdcConfigIntr(devId, AUDK2G_ADC_INTR_ALL,
-                                           config->intEnable);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioAdcConfig : audk2g_AudioAdcConfigIntr Failed\n"));
-               return (status);
-       }
-
-       return (status);
-}
-
-/**
- *  \brief    Initializes DAC module
- *
- *  This function initializes and configures the DAC modules
- *  on audio daughter card
- *
- *  \param     devId  [IN]  DAC Device Id
- *  \param     config [IN]  DAC configuration parameters
- *
- *  \return    Platform_EOK on Success or error code
- */
-Audk2g_STATUS audioDacConfig(Audk2gDacDevId devId, DacConfig *config)
-{
-       Audk2g_STATUS status;
-
-       if(config == NULL)
-       {
-               IFPRINT(audk2g_write("Invalid Inputs\n"));
-               return (Audk2g_EINVALID);
-       }
-
-       /* Initialize Audio DAC */
-       status = audk2g_AudioDacInit(devId);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacInit Failed\n"));
-               return (status);
-       }
-
-       /* Configure AMUTE control event */
-       status = audk2g_AudioDacAmuteCtrl(devId, config->amuteCtrl,
-                                          config->amuteEnable);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacAmuteCtrl Failed\n"));
-               return (status);
-       }
-
-       /* Set sampling mode */
-       status = audk2g_AudioDacSetSamplingMode(devId, config->samplingMode);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacSetSamplingMode Failed\n"));
-               return (status);
-       }
-
-       /* Set data format */
-       status = audk2g_AudioDacSetDataFormat(devId, config->dataFormat);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacSetDataFormat Failed\n"));
-               return (status);
-       }
-
-       /* Enable soft mute control */
-       status = audk2g_AudioDacSoftMuteCtrl(devId, AUDK2G_DAC_CHAN_ALL,
-                                             config->softMuteEnable);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacSoftMuteCtrl Failed\n"));
-               return (status);
-       }
-
-       /* Set attenuation mode */
-       status = audk2g_AudioDacSetAttnMode(devId, config->attnMode);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacSetAttnMode Failed\n"));
-               return (status);
-       }
-
-       /* Set De-emphasis control */
-       status = audk2g_AudioDacDeempCtrl(devId, config->deempCtrl);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacDeempCtrl Failed\n"));
-               return (status);
-       }
-
-       /* Set DAC volume */
-       status = audk2g_AudioDacSetVolume(devId, AUDK2G_DAC_CHAN_ALL, config->volume);
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioDacConfig : audk2g_AudioDacSetVolume Failed\n"));
-               return (status);
-       }
-
-       return (status);
-}
-
-/**
- *  \brief    Initializes DIR module
- *
- *  This function initializes and configures the DIR modules
- *  on audio daughter card
- *
- *  \return    Platform_EOK on Success or error code
- */
-Audk2g_STATUS audioDirConfig(void)
-{
-       Audk2g_STATUS status;
-       int8_t          fsout;
-#ifdef CHECK_ERROR_STATUS
-       uint32_t        timeout;
-#endif
-
-       status = audk2g_AudioDirInit();
-       if(status != Audk2g_EOK)
-       {
-               IFPRINT(audk2g_write("audioDirConfig : Audio DIR Configuration Failed!\n"));
-               return (status);
-       }
-
-#ifdef CHECK_ERROR_STATUS
-       /* DIR should be in PLL mode.
-          Wait for ERROR signal to be low as DIR is configured for
-          AUTO mode */
-       timeout = ERROR_STATUS_WAIT_TIMEOUT;
-       while (timeout)
-       {
-               if(!audk2g_AudioDirGetErrStatus())
-               {
-                       IFPRINT(audk2g_write("audioDirConfig : DIR in PLL Mode\n"));
-                       break;
-               }
-
-               IFPRINT(audk2g_write("audioDirConfig : Waiting for DIR to Enter PLL Mode...\n"));
-               audk2g_delay(10);
-               timeout--;
-       }
-
-       if(!timeout)
-       {
-               IFPRINT(audk2g_write("audioDirConfig : DIR is not in PLL Mode!!\n"));
-               return (Platform_EFAIL);
-       }
-#endif
-
-       fsout = audk2g_AudioDirGetFsOut();
-       if(fsout == 2)
-       {
-               IFPRINT(audk2g_write("audioDirConfig : Out of Range Sampling Frequency\n"));
-       }
-       else if(fsout == 0)
-       {
-               IFPRINT(audk2g_write("audioDirConfig : Calculated Sampling Frequency Output is 43 kHz\9645.2 kHz\n"));
-       }
-       else if(fsout == 1)
-       {
-               IFPRINT(audk2g_write("audioDirConfig : Calculated Sampling Frequency Output is 46.8 kHz\9649.2 kHz\n"));
-       }
-       else if(fsout == 3)
-       {
-               IFPRINT(audk2g_write("audioDirConfig : Calculated Sampling Frequency Output is 31.2 kHz\9632.8 kHz\n"));
-       }
-       else
-       {
-               IFPRINT(audk2g_write("audioDirConfig : Error in Reading FSOUT status \n"));
-               status = Audk2g_EFAIL;
-       }
-
-       return (status);
-}
-
-int alpha_i2c_write(unsigned short, ...);
-void set_audio_desc(unsigned char ,unsigned char ,unsigned char ,unsigned char ,unsigned char );
-void hrptredid();
-void  hdmi128();
-
-
-int gret_val=0;
-int gI2cWrite_errCnt=0;
-int alpha_i2c_write(unsigned short var1, ...)
-{
-       unsigned short alpha_type,length,temp_var;
-       int i,offset,ret_val;
-       unsigned char cmd[50];
-       char *s;
-       va_list argp;
-       va_start(argp, var1);
-
-       alpha_type = var1>> 8;
-       switch(alpha_type)
-       {
-               case 0xca:
-               case 0xc2:
-               case 0xc3:
-               case 0xc4:
-                       length = 4;
-                       break;
-               case 0xcb:
-                       length = 6;
-                       break;
-               case 0xcc:
-                       length = 8;
-                       break;
-               case 0xcd:
-               case 0xc5:
-                       length= 8; // temporary - data starts after 8 bytes
-                       break;
-       }
-
-       cmd[0]=length;
-       temp_var=var1;
-       for(i=0;i<length-2;i+=2) // convert to bytes as per protocol
-       {
-               cmd[i+1]= temp_var & 0xff;
-               cmd[i+2]= temp_var >> 8;
-               temp_var=va_arg(argp, short);
-       }
-       cmd[i+1]= temp_var & 0xff;
-       cmd[i+2]= temp_var >> 8;
-
-
-       if(alpha_type == 0xcd) // special processing for variable length
-       {
-               offset=9;
-               s = va_arg(argp, char *); // remaining data is in form of string
-               length = temp_var; // last short indicates data length
-               cmd[0]+=length;
-               for(i=offset;i<offset+length;i++)
-                       cmd[i]=s[i-offset];
-       }
-va_end(argp);
-
-#define DA10x_I2C      1
-
-#ifdef DA10x_I2C
-do
-{
-       ret_val = DA10x_I2C_write(HSR4_I2C_ADDR, cmd, cmd[0]+1);
-
-       if(ret_val !=I2C_RET_OK)
-       {
-               gret_val++;
-               gI2cWrite_errCnt++;
-               DA10x_I2C_reset();
-       }
-}while(ret_val !=I2C_RET_OK);
-
-#else
-do
-{
-ret_val = i2cWrite(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR, cmd, cmd[0]+1, I2C_RELEASE_BUS);
-if(ret_val !=I2C_RET_OK)
-       {
-               gret_val++;
-               gI2cWrite_errCnt++;
-               i2cConfig(HSR4_I2C_PORT_NUM);
-       }
-}while(ret_val !=I2C_RET_OK);
-ret_val = i2cWrite(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR, cmd, cmd[0]+1, I2C_RELEASE_BUS);
-if(ret_val !=I2C_RET_OK)
-               gret_val++;
-#endif
-
-return ret_val;
-}
-
-void set_audio_desc(unsigned char var1,unsigned char var2,unsigned char var3,unsigned char var4,unsigned char var5)
-{
-       int ret_val=I2C_RET_OK;
-
-       audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_FORMAT(var1, var2));}while (ret_val !=I2C_RET_OK);
-       audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_NUM_CHANNELS(var1, var3));}while (ret_val !=I2C_RET_OK);
-       audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_SAMPLE_RATES(var1, var4));}while (ret_val !=I2C_RET_OK);
-       audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_MISC(var1, var5));}while (ret_val !=I2C_RET_OK);
-}
-
-int gI2Ccnt=0;
-
-// Program HDMI CEA / EDID values, as necessary.
-void hrptredid()
-{
-       int ret_val=I2C_RET_OK;
-
-       /*do{
-               platform_delay(10);
-               ret_val=alpha_i2c_write(HSDIO_EDID_SPEAKER_ALLOCATION_BLOCK(0xFF));
-        if (ret_val !=I2C_RET_OK)
-        {
-               gI2Ccnt++;
-#ifdef DA10x_I2C
-               DA10x_I2C_reset();
-#else
-               i2cConfig(HSR4_I2C_PORT_NUM);
-#endif
-        }
-            
-       }while (ret_val !=I2C_RET_OK); */
-       do{ret_val=alpha_i2c_write(HSDIO_EDID_SPEAKER_ALLOCATION_BLOCK(0xFF));}while (ret_val !=I2C_RET_OK);
-       audk2g_delay(10);
-       do{ret_val=alpha_i2c_write(HSDIO_EDID_SPEAKER_ALLOCATION_BLOCK_2(0x7));}while (ret_val !=I2C_RET_OK);
-
-       set_audio_desc(0,1,2,0x7f,7);   // PCM 2 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4 KHz, 192 KHz, 16bit, 20bit, 24bit
-       set_audio_desc(1,1,8,0x7f,7);   // PCM 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4 KHz, 192 KHz, 16bit, 20bit, 24bit
-       set_audio_desc(2,2,6,0x7,80);   // AC3 6 channel, 32kHz, 44.1kHz, 48kHz, 640kHz max bit rate
-       set_audio_desc(3,10,8,0x07,1);  // Dolby Digital Plus, 8 channel, 32kHz, 44.1kHz, 48kHz, codec specific:1
-       set_audio_desc(4,12,8,0x7F,1);  // MAT(MPL)(Dolby TrueHD), 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz,
-                                                                       // 176.4kHz, 192kHz,  codec specific:1
-       set_audio_desc(5,7,6,0x1E,192); // DTS 6 channel, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 1,536kHz max bit rate
-       set_audio_desc(6,7,8,0x6,192);  // DTS 8 channel, 44.1kHz, 48kHz, 1,536kHz max bit rate
-       set_audio_desc(7,11,8,0x7F,3);  // DTS-HD, 8 channel, 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz,
-                                                                       // last byte is 3 for DTS:X, 1 otherwise.
-       set_audio_desc(8,11,8,0x7F,1);  // DTS-HD, 8 channel - same as above, but last byte = 1
-       set_audio_desc(9,0,0,0,0);
-       set_audio_desc(10,0,0,0,0);
-       set_audio_desc(11,0,0,0,0); //AAC LC (5,6,6,0x1f,192);
-       set_audio_desc(12,0,0,0,0);
-       set_audio_desc(13,0,0,0,0);
-       set_audio_desc(14,0,0,0,0);
-       set_audio_desc(15,0,0,0,0);
-       set_audio_desc(16,0,0,0,0);
-       set_audio_desc(17,0,0,0,0);
-       set_audio_desc(18,0,0,0,0);
-       set_audio_desc(19,0,0,0,0);
-       audk2g_delay(10);
-       do{ret_val=alpha_i2c_write(HSDIO_EDID_GO);}while (ret_val !=I2C_RET_OK);
-}
-
-// Configure the HOST port of HSR41 for EXTRACT mode of operation.
-// Note: HDMI Tx/Out Port's state is not cared for, at all.
-void  hdmi128()
-{
-       int ret_val=I2C_RET_OK;
-
-       audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_ALERT(HSDIO_ALERT_INPUT_AUDIO_CHANGE_msk));}while (ret_val !=I2C_RET_OK);
-       //audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_ALERT(HSDIO_ALERT_INPUT_AUDIO_MUTE_msk));}while (ret_val !=I2C_RET_OK);
-       audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_AUDIO_MCLK_TO_HOST(HSDIO_AudioMClk_128X));}while (ret_val !=I2C_RET_OK);
-       audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_AUDIO_UNMUTE_DELAY_TO_HOST(HSDIO_AudioUnMuteDelay_NO_DELAY));}while (ret_val !=I2C_RET_OK);
-       audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_AUDIO_FORMAT_TO_HOST(HSDIO_AudioFmt_I2S));}while (ret_val !=I2C_RET_OK);
-       audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_IMPLEMENT_AUDIO_TO_HOST_CMDS);}while (ret_val !=I2C_RET_OK);
-       audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_AUDIO_ROUTING(HSDIO_AudioRouting_HSDIOIN_NOOUT));}while (ret_val !=I2C_RET_OK);
-       audk2g_delay(10);do{ret_val=alpha_i2c_write(HSDIO_SYS_CFG_GO);}while (ret_val !=I2C_RET_OK);
-}
-
-//
-// Fetch Video Sync Status from HSR41
-unsigned int read_hdmi_videosyncstatus()
-{
-       unsigned char data[50];
-       Uint8 length;
-       int ret_val=0;
-
-       ret_val=alpha_i2c_write(HSDIO_INPUT_SYNC_STS);
-#ifdef DA10x_I2C
-       if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&length,1);
-       if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&data[0],length);
-#else
-       if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,1,1);
-       if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,1,length);
-#endif
-       if(!ret_val) ret_val= data[2]; // 1-byte / indicates error status
-
-       return ret_val;
-}
-
-//
-// Fetch Audio Present Status from HSR41
-unsigned int read_hdmi_audiostatus()
-{
-       unsigned char data[50];
-       Uint8 length;
-       int ret_val=0;
-
-       ret_val=alpha_i2c_write(HSDIO_AUDIO_INPUT_PRESENT_STS);
-#ifdef DA10x_I2C
-       if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&length,1);
-       if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&data[0],length);
-#else
-       if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,1,1);
-       if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,1,length);
-#endif
-       if(!ret_val) ret_val= data[2]; // 1-byte / indicates error status
-
-       return ret_val;
-}
-
-// Fetch Clock Status from HSR41
-unsigned int read_hdmi_clockstatus()
-{
-       unsigned char data[50];
-       Uint8 length;
-       int ret_val=0;
-
-       ret_val=alpha_i2c_write(HSDIO_GET_AUDIO_MCLK_TO_HOST);
-#ifdef DA10x_I2C
-       if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&length,1);
-       if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&data[0],length);
-#else
-       if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,1,1);
-       if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,1,length);
-#endif
-       if(!ret_val) ret_val= data[2]; // 1-byte / indicates clock status
-
-       return ret_val;
-}
-
-// Fetch Error Status from HSR41
-unsigned int read_hdmi_errstatus()
-{
-       unsigned char data[50];
-       Uint8 length;
-       int ret_val=0;
-
-       ret_val=alpha_i2c_write(HSDIO_AUDIO_INPUT_ERROR_STS);
-#ifdef DA10x_I2C
-       if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&length,1);
-       if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&data[0],length);
-#else
-       if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,1,1);
-       if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,1,length);
-#endif
-       if(!ret_val) ret_val= data[2]; // 1-byte / indicates error status
-
-       return ret_val;
-}
-
-void clear_hdmi_hmint()
-{
-       int ret_val=0;
-
-       ret_val=alpha_i2c_write(HSDIO_ALERT_STS); //clear the interrupt on ~HMINT by reading the Alert Status register
-
-       if(ret_val)
-               while(1);               // Control shouldn't be here
-
-       return;
-}
-
-unsigned int read_hdmi_samprate()
-{
-       unsigned char data[50];
-       Uint8 length;
-       int ret_val=7;
-
-       Log_info0("Audio DC CFG: Entered read_hdmi_samprate");
-       ret_val=alpha_i2c_write(HSDIO_AUDIO_INPUT_FREQ_STS);
-
-#ifdef DA10x_I2C
-       if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&length,1);
-       if(!ret_val) DA10x_I2C_read(HSR4_I2C_ADDR,&data[0],length);
-#else
-       if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,1,1);
-       if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,1,length);
-#endif
-
-       Log_info0("Audio DC CFG: Leaving read_hdmi_samprate");
-
-       if(!ret_val) ret_val= data[2]; // indicates sample rate
-       else
-       ret_val = 0;
-
-       return ret_val;
-}
-
-
-Audk2g_STATUS audioHDMIConfig(void)
-{
-       Audk2g_STATUS status = Audk2g_EOK;
-
-       DA10x_I2C_init();
-       hrptredid();
-
-       hdmi128();
-
-       //while((HSDIO_InSync_SYNC_DETECTED != read_hdmi_videosyncstatus()) || (HSDIO_AudioMClk_128X != read_hdmi_clockstatus()));// || (HSDIO_AudioPresent_HAS_AUDIO != read_hdmi_audiostatus()));
-       while((HSDIO_InSync_SYNC_DETECTED != read_hdmi_videosyncstatus()));
-       //while((HSDIO_AudioMClk_128X != read_hdmi_clockstatus()) || (HSDIO_AudioErr_NO_ERROR != read_hdmi_errstatus()));
-
-       return (status);
-}
-
-/* ------------------------------------------------------------------------ *
- *                                                                          *
- * DA10x_wait( delay )                                                  *
- *                                                                          *
- *      Wait in a software loop for 'x' delay                               *
- *                                                                          *
- * ------------------------------------------------------------------------ */
-void DA10x_wait( Uint32 delay )
-{
-    volatile Uint32 i;
-    for ( i = 0 ; i < delay ; i++ ){ };
-}
-
-/* ------------------------------------------------------------------------ *
- *                                                                          *
- *  DA10x_waitusec( usec )                                               *
- *                                                                          *
- *      Wait in a software loop for 'x' microseconds                        *
- *                                                                          *
- * ------------------------------------------------------------------------ */
-void DA10x_waitusec( Uint32 usec )
-{
-    DA10x_wait( usec * 3 );
-}
-Int32 i2c_timeout = 0x10000;
-
-/* ------------------------------------------------------------------------ *
- *                                                                          *
- *  _I2C_init( )                                                            *
- *                                                                          *
- *      Enable and initalize the I2C module                                 *
- *      The I2C clk is set to run at 400 (384) KHz                          *
- *                                                                          *
- * ------------------------------------------------------------------------ */
-Int16 DA10x_I2C_init()
-{
-    I2C_ICMDR   = 0;                // Reset I2C
-    I2C_ICPSC   = 9;               // Prescale to get 10MHz I2C internal
-    I2C_ICCLKL  = 7;               // Config clk LOW for 400kHz
-    I2C_ICCLKH  = 7;               // Config clk HIGH for 400kHz
-    I2C_ICMDR  |= ICMDR_IRS;        // Release I2C from reset
-    return 0;
-}
-
-/* ------------------------------------------------------------------------ *
- *                                                                          *
- *  _I2C_close( )                                                           *
- *                                                                          *
- * ------------------------------------------------------------------------ */
-Int16 DA10x_I2C_close()
-{
-        I2C_ICMDR = 0;                      // Reset I2C
-        return 0;
-}
-
-/* ------------------------------------------------------------------------ *
- *                                                                          *
- *  _I2C_reset( )                                                           *
- *                                                                          *
- * ------------------------------------------------------------------------ */
-Int16 DA10x_I2C_reset( )
-{
-    DA10x_I2C_close( );
-    DA10x_I2C_init( );
-    return 0;
-}
-
-/* ------------------------------------------------------------------------ *
- *                                                                          *
- *  _I2C_write( i2c_addr, data, len )                                       *
- *                                                                          *
- *      I2C write in Master mode                                            *
- *                                                                          *
- *      i2c_addr    <- I2C slave address                                    *
- *      data        <- I2C data ptr                                         *
- *      len         <- # of bytes to write                                  *
- *                                                                          *
- * ------------------------------------------------------------------------ */
-Int16 DA10x_I2C_write( Uint16 i2c_addr, Uint8* data, Uint16 len )
-{
-    Int32 timeout, i;
-
-        I2C_ICCNT = len;                    // Set length
-        I2C_ICSAR = i2c_addr;               // Set I2C slave address
-        I2C_ICMDR = ICMDR_STT               // Set for Master Write
-                  | ICMDR_TRX
-                  | ICMDR_MST
-                  | ICMDR_IRS
-                  | ICMDR_FREE;
-
-        DA10x_wait( 10 );                        // Short delay
-
-        for ( i = 0 ; i < len ; i++ )
-        {
-
-            I2C_ICDXR = data[i];            // Write
-
-            timeout = i2c_timeout;
-            do
-            {
-               DA10x_wait( 10);
-                if ( timeout-- < 0  )
-                {
-                    DA10x_I2C_reset( );
-                    return -1;
-                }
-            } while ( ( I2C_ICSTR & ICSTR_ICXRDY ) == 0 );// Wait for Tx Ready
-
-        }
-
-        I2C_ICMDR |= ICMDR_STP;             // Generate STOP
-
-        return 0;
-
-}
-
-/* ------------------------------------------------------------------------ *
- *                                                                          *
- *  _I2C_read( i2c_addr, data, len )                                        *
- *                                                                          *
- *      I2C read in Master mode                                             *
- *                                                                          *
- *      i2c_addr    <- I2C slave address                                    *
- *      data        <- I2C data ptr                                         *
- *      len         <- # of bytes to write                                  *
- *                                                                          *
- *      Returns:    0: PASS                                                 *
- *                 -1: FAIL Timeout                                         *
- *                                                                          *
- * ------------------------------------------------------------------------ */
-Int16 DA10x_I2C_read( Uint16 i2c_addr, Uint8* data, Uint16 len )
-{
-    Int32 timeout, i;
-
-    I2C_ICCNT = len;                    // Set length
-    I2C_ICSAR = i2c_addr;               // Set I2C slave address
-    I2C_ICMDR = ICMDR_STT               // Set for Master Read
-              | ICMDR_MST
-              | ICMDR_IRS
-              | ICMDR_FREE;
-
-    DA10x_wait( 10 );                        // Short delay
-
-    for ( i = 0 ; i < len ; i++ )
-    {
-        timeout = i2c_timeout;
-
-        /* Wait for Rx Ready */
-        do
-        {
-               DA10x_wait( 10 );
-            if ( timeout-- < 0 )
-            {
-                DA10x_I2C_reset( );
-                return -1;
-            }
-        } while ( ( I2C_ICSTR & ICSTR_ICRRDY ) == 0 );// Wait for Rx Ready
-
-        data[i] = I2C_ICDRR;            // Read
-
-    }
-
-      I2C_ICMDR |= ICMDR_STP;             // Generate STOP
-
-        return 0;
-}
-
-
-
-/* Nothing past this point */
index 899fb976ecf538897d86909ab6ef003c66c7c081..3ac2e5b175ed4a5801818bda00f63b2b107b1e2b 100644 (file)
@@ -41,7 +41,7 @@ All rights reserved.
 //
 
 #ifndef SAP_CACHE_SUPPORT
-  // if you rebuild dap.c in your project without this defined, 
+  // if you rebuild sap.c in your project without this defined,
   // the result is quite hard to find:  Occasional glitches in the sound.
   #define SAP_CACHE_SUPPORT  // typically defined in the project
 #endif
@@ -73,13 +73,12 @@ All rights reserved.
 
 // This works to set a breakpoint
 #define SW_BREAKPOINT       asm( " SWBP 0" );
-/* Software Breakpoint to Code Composer */
-// SW_BREAKPOINT;
 
 // global allocated in bios_edma3_drv_sample_init.c
 extern EDMA3_DRV_Handle hEdma0;
 extern EDMA3_DRV_Handle hEdma1;
 
+// global variables for debug-assist
 int gStartError;
 int gIsrInputCnt;
 int gIsrOutputCnt;
@@ -171,7 +170,7 @@ void SAP_EDMA_dumpParams(int tag_place)
        Log_info5("PARAM0x4Ab(%d): SRC: 0x%08x, A_B_CNT: 0x%08x, DST: 0x%08x,  SRC_DST_BIDX: 0x%08x", tag_place, ptrPARAM0x4A[1], ptrPARAM0x4A[2], ptrPARAM0x4A[3], ptrPARAM0x4A[4]);
        Log_info4("PARAM0x4Ac(%d): LINK_BCNTRLD: 0x%08x, SRC_DST_CIDX: 0x%08x, CCNT: 0x%08x", tag_place, ptrPARAM0x4A[5], ptrPARAM0x4A[6], ptrPARAM0x4A[7]);
 
-       Log_info1("TCC0: ERR reg %x", *((unsigned int *)0x02760120)); //DJDBG
+       Log_info1("TCC0: ERR reg %x", *((unsigned int *)0x02760120));
 }
 #endif
 // .............................................................................
@@ -192,13 +191,11 @@ SAP_DriverObject sapDrv;
 // needed since SAP_watchDog is called before SAP_init
 Int SAP_initialized = 0;
 
-//Int  SAP_close(DEV2_Handle);
 Int  SAP_ctrl(DEV2_Handle, Uns, Arg);
 Int  SAP_idle(DEV2_Handle, Bool);
 Int  SAP_issue(DEV2_Handle);
 Int  SAP_open(DEV2_Handle, String);
 void SAP_isrCallback (Uint32 tcc, EDMA3_RM_TccStatus status, Ptr context);
-//Bool SAP_ready(DEV2_Handle, SEM_Handle);
 Int  SAP_reclaim(DEV2_Handle);
 Int  SAP_shutdown(DEV2_Handle);
 Int  SAP_start(DEV2_Handle);
@@ -467,14 +464,9 @@ Int SAP_ctrl (DEV2_Handle device, Uns code, Arg arg)
             Log_info0 ("SAP PAF_SIO_CONTROL_IDLE_WITH_CLOCKS; PAF_SIO_ERROR_IDLE_STAGE1");
             pDevExt->errorState = PAF_SIO_ERROR_IDLE_STAGE1;
 
-#if 1
-            //DJDBG, if below enableTransfer() is commented, input side continuous working.
-     if (pDevExt->activeEdma != EDMA_HINV) {
-               //EDMA3_DRV_disableTransfer (hEdma0, pDevExt->activeEdma, EDMA3_DRV_TRIG_MODE_EVENT);
-            //if(*((unsigned int *)0x02701000) & 0x01000000) *((unsigned int *)0x02701008) = 0x01000000; //Clear pending even in bit 24! //DJDBG
-            EDMA3_DRV_enableTransfer (hEdma, pDevExt->activeEdma, EDMA3_DRV_TRIG_MODE_EVENT);
-     }
-#endif
+            if (pDevExt->activeEdma != EDMA_HINV)
+               EDMA3_DRV_enableTransfer (hEdma, pDevExt->activeEdma, EDMA3_DRV_TRIG_MODE_EVENT);
+
             //TRACE_GEN((&TR_MOD, "SAP_ctrl.%d: (0x%x) errorState = PAF_SIO_ERROR_IDLE_STAGE1 0x%x.", __LINE__, device, PAF_SIO_ERROR_IDLE_STAGE1));
 
             break;
@@ -635,7 +627,7 @@ Int SAP_start (DEV2_Handle device)
     int result;
     EDMA3_DRV_Handle hEdma;
 
-    Log_info2("SAP_start.%d (0x%x)", __LINE__, device);
+    Log_info2("SAP_start.%d (0x%x)", __LINE__, (xdc_IArg)device);
 
     // Assume todevice queue is not empty -- how else could we be here?
     pFrame = (DEV2_Frame *) Queue_get (device->todevice);
@@ -789,33 +781,21 @@ Int SAP_issue (DEV2_Handle device)
                            __LINE__, pParam->hEdmaParam, parentEdma, pDevExt->errorEdma);
     }
 
-
-    /*if ((device->mode != DEV2_INPUT) && (gDmaParamsidx <=16))
-       {
-       gDmaParamsarray[gDmaParamsidx][0] = pParam->hEdma;
-               gDmaParamsarray[gDmaParamsidx][1] = parentEdma;
-               gDmaParamsarray[gDmaParamsidx++][2] = gisrOutput;
-       } */
-
        if ((pDevExt->errorState == PAF_SIO_ERROR_IDLE_STAGE1) && (device->mode == DEV2_OUTPUT))
                pDevExt->errorState = PAF_SIO_ERROR_NONE;
 
         pDevExt->shutDown = 0;
 
-        //if (device->mode == DEV2_OUTPUT)
-                       //SAP_EDMA_dumpParams(5);
-
     // special case enables when not yet started
     if (pDevExt->runState == 0) {
        gSAPSpecialCase++;
         result = SAP_FTABLE_start (device);
         if (result) {
-            //SAP_DMA_FTABLE_unlock (device);
                  Hwi_restore (key);
             return result;
         }
     }
-    Hwi_restore (key); //DJDBG
+    Hwi_restore (key);
 
     return result;
 } // SAP_issue
@@ -854,7 +834,7 @@ void swapHdmi(Ptr Input, int size)
 
        }
 
-       Log_info3("SAP: Exiting swapHdmi with Frame->Addr: 0x%x, p1->addr: 0x%x, p2->addr: 0x%x ", (xdc_IArg)Input, p1, p2);
+       Log_info3("SAP: Exiting swapHdmi with Frame->Addr: 0x%x, p1->addr: 0x%x, p2->addr: 0x%x ", (xdc_IArg)Input, (xdc_IArg)p1, (xdc_IArg)p2);
 
        return;
 }
@@ -876,14 +856,7 @@ Int SAP_reclaim (DEV2_Handle device)
         return SIO2_EBADIO;
     }
 
-    // idle if necessary
-        if (pDevExt->errorState == PAF_SIO_ERROR_FATAL) {
-               Log_info1("SAP_reclaim: PAF_SIO_ERROR_FATAL,  Before Idle for device 0x%x  ", device->mode);
-            DEV2_idle (device, 1);
-            return SIO2_EBADIO;
-        }
-
-       Log_info1("SAP_reclaim: Before SEM Pend for mode: 0x%x", device->mode);
+    Log_info1("SAP_reclaim: Before SEM Pend for mode: 0x%x", device->mode);
 
     // wait for ISR to signal block completion
     //TRACE_VERBOSE((&TR_MOD, "SAP_reclaim.%d wait for ISR to signal block completion", __LINE__));
@@ -894,7 +867,6 @@ Int SAP_reclaim (DEV2_Handle device)
     }
     Log_info1("SAP_reclaim: After SEM Pend for mode: 0x%x", device->mode);
 
-#if 1
     // return error (owner must idle)
     if (pDevExt->errorState == PAF_SIO_ERROR_FATAL)
     {
@@ -902,14 +874,13 @@ Int SAP_reclaim (DEV2_Handle device)
         Log_info2("SAP_reclaim.%d, PAF_SIO_ERROR_FATAL: 0x%x", __LINE__, pDevExt->errorState);
         return PAF_SIO_ERROR_FATAL;
     }
-#endif
 
 #ifdef SAP_CACHE_SUPPORT
     // invalidate CACHE region if input -- use clean since
     //    Dont clean if was for fill.
     // since pend returned we know that head of fromdevice is valid
     pFrame = Queue_head (device->fromdevice);
-    Log_info2("SAP: Inside SAP_Reclaim with From Device Frame->Addr: 0x%x and Frame->Size: %d", pFrame->addr, pFrame->size);
+    Log_info2("SAP: Inside SAP_Reclaim with From Device Frame->Addr: 0x%x and Frame->Size: %d", (xdc_IArg)pFrame->addr, pFrame->size);
     if ((device->mode == DEV2_INPUT) && (pFrame->addr != NULL))
     {
         if(pDevExt->edmaWordSize == 2 && pDevExt->numSers == 4)
@@ -1031,7 +1002,7 @@ Int SAP_config (DEV2_Handle device, const SAP_Params *pParams)
     EDMA3_DRV_Result     edmaResult;
     Uint32                                     reqTcc;
     EDMA3_DRV_Handle   hEdma;
-    Log_info2("SAP_config.%d (0x%x)", __LINE__, device);
+    Log_info2("SAP_config.%d (0x%x)", __LINE__, (xdc_IArg)device);
 
     // cannot configure if transfer started
     if (pDevExt->runState == 1)
@@ -1228,19 +1199,12 @@ Int SAP_shutdown (DEV2_Handle device)
     
     pDevExt->shutDown = 1;
     pDevExt->numParamSetup = 0;
-    
-    /*result = SAP_DMA_FTABLE_unlock (device);
-    if (result)
-    {
-        //TRACE_TERSE((&TR_MOD, "%s.%d: SAP_DMA_FTABLE_unlock returned %d.\n", __FUNCTION__, __LINE__, result));
-        return result;
-    } */
 
     return SIO2_OK;
 } // SAP_shutdown
 
 // -----------------------------------------------------------------------------
-int gSapWatchDogThrottle = 0; //DJDBG
+int gSapWatchDogThrottle = 0;
 int gSapWatchDogIn =0;
 int gSapWatchDogOut = 0;
 int gSapWatchDogInSemPost = 0;
@@ -1257,7 +1221,7 @@ Void SAP_watchDog (Void)
     // do nothing if SAP_init not yet called
     if (!SAP_initialized)
     {
-        Log_info2("%s.%d: SAP_init not yet called.\n", __FUNCTION__, __LINE__);
+        Log_info2("%s.%d: SAP_init not yet called.\n", (xdc_IArg)__FUNCTION__, __LINE__);
         return;
     }
 
@@ -1292,19 +1256,10 @@ Void SAP_watchDog (Void)
             if(device->mode == DEV2_INPUT)
                gSapWatchDogIn++;
             else
-            {
-               //if (gSapWatchDogOut == 0)
-                       //SAP_EDMA_dumpParams(1);
                gSapWatchDogOut++;
-            }
 
             //TRACE_TERSE((&TR_MOD, "SAP_watchDog.%d, PAF_SIO_ERROR_FATAL: 0x%x", __LINE__, pDevExt->errorState));
-           /* if(gSapWatchDogThrottle == 0) //DJDBG
-            {
-               Log_info3("SAP_watchDog.%d (0x%x); THROTTLED result = 0x%x", __LINE__, device, result);
-            }
-            gSapWatchDogThrottle ++;
-            if(gSapWatchDogThrottle > 10) gSapWatchDogThrottle = 0; */
+
             // if outstanding pend then post to free owner thead
             if (!Semaphore_pend(pDevExt->sync, 0))
             {
@@ -1386,12 +1341,6 @@ void SAP_isrCallback (Uint32 tcc, EDMA3_RM_TccStatus status, Ptr context)
             //Log_info2("Before SEM_post for device: 0x%x gIsrOutput: %d", device->mode, gisrOutput);
             // signal user thread
             Semaphore_post (pDevExt->sync);
-#if 0
-            if(gIsrCnt > 10) { //DJDBG
-               Log_info1("SAP isrCallback enough interrupts! %d", gIsrCnt);
-
-            }
-#endif
         }
         else
                gIsrElseCnt++;
@@ -1439,29 +1388,29 @@ Int SAP_EDMA_setupXfer (DEV2_Handle device, XDAS_UInt32 targetEdma, XDAS_UInt32
 
     // TODO: shouldn't this just be tcc interrupt disable?
     // at least until linkage phase...
-    unsigned int key = Hwi_disable (); //DJDBG
+    unsigned int key = Hwi_disable ();
 
     if(targetEdma == NULL)
     {
        Log_info0("targetEdma is NULL");
     }
     // configure transfer
-    if(pFrame->addr == NULL) //DJDBG
+    if(pFrame->addr == NULL)
     {
         Log_info0("pFrame has NULL address?");
     }
     SAP_DMA_FTABLE_setupParam (device, targetEdma, childEdma, (XDAS_UInt32) pFrame->addr, pFrame->size);
 
     if (device->mode == DEV2_OUTPUT)
-       Log_info4("SAP: Inside SAP_EDMA_setupXfer with childEdma=0x%x & targetEdma = 0x%x; pFrame->addr = 0x%x, pFrame->size=0x%x", childEdma, targetEdma, pFrame->addr, pFrame->size);
+       Log_info4("SAP: Inside SAP_EDMA_setupXfer with childEdma=0x%x & targetEdma = 0x%x; pFrame->addr = 0x%x, pFrame->size=0x%x", childEdma, targetEdma, (xdc_IArg)pFrame->addr, pFrame->size);
 
     if (parentEdma != EDMA_HINV)
         EDMA3_DRV_linkChannel (hEdma, parentEdma, targetEdma);
 
     if (device->mode == DEV2_OUTPUT)
-               Log_info3("SAP: Inside SAP_EDMA_setupXfer linked targetEdma = 0x%x with parentEdma=0x%x on Edma=0x%x", targetEdma, parentEdma, hEdma);
+               Log_info3("SAP: Inside SAP_EDMA_setupXfer linked targetEdma = 0x%x with parentEdma=0x%x on Edma=0x%x", targetEdma, parentEdma, (xdc_IArg)hEdma);
 
-    Hwi_restore (key); //DJDBG
+    Hwi_restore (key);
 
     return SIO2_OK;
 } // SAP_setupXfer
@@ -1488,7 +1437,7 @@ Int SAP_EDMA_setupParam (DEV2_Handle device, XDAS_UInt32 targetEdma, XDAS_UInt32
    //Log_info3("%s.%d: Entered SAP_EDMA_setupParam for Target: 0x%x.\n", (xdc_IArg)__FUNCTION__, __LINE__, targetEdma);
 
     // Init opt parameter to 0 which, without being overriden, configures as:
-    //    A synchronized transfer (no FIFO mode on src or dst)
+    //    AB synchronized transfer
     //    no chaining or intermediate interrupts
     //    param is not static
     //    normal completion
@@ -1499,15 +1448,11 @@ Int SAP_EDMA_setupParam (DEV2_Handle device, XDAS_UInt32 targetEdma, XDAS_UInt32
     edmaConfig.destCIdx = 0;
     edmaConfig.srcCIdx = 0;
 
-    edmaConfig.opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK (EDMA3_DRV_SYNC_AB); //DJDBG!
-    if (device->mode == DEV2_OUTPUT) {
-      //edmaConfig.opt |= EDMA3_DRV_OPT_DAM_SET_MASK (EDMA3_DRV_ADDR_MODE_FIFO); //DJDBG!!!
-      edmaConfig.opt |= 2;
-    }
-    else {
-       //edmaConfig.opt |= EDMA3_DRV_OPT_SAM_SET_MASK (EDMA3_DRV_ADDR_MODE_FIFO); //DJDBG!!!
-       edmaConfig.opt |= 1;
-    }
+    edmaConfig.opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK (EDMA3_DRV_SYNC_AB);
+    if (device->mode == DEV2_OUTPUT)
+       edmaConfig.opt |= 2;            //DAM=CONST addr mode
+    else
+       edmaConfig.opt |= 1;            //SAM=CONST addr mode
 
     // if regular transfer then enable interrupt with tcc code
     if (targetEdma != pDevExt->errorEdma) {
@@ -1536,8 +1481,6 @@ Int SAP_EDMA_setupParam (DEV2_Handle device, XDAS_UInt32 targetEdma, XDAS_UInt32
                edmaConfig.cCnt= (size)/((edmaConfig.aCnt * edmaConfig.bCnt)/2);
         }
         else {
-               //if(pDevExt->edmaWordSize == 2)
-               //edmaConfig.srcAddr= (unsigned int)edmaConfig.srcAddr+ 2;
             edmaConfig.destBIdx = 0;
             edmaConfig.destAddr = (unsigned int) &sap_OVER_4LANE;
             edmaConfig.cCnt = 1;
@@ -1550,15 +1493,10 @@ Int SAP_EDMA_setupParam (DEV2_Handle device, XDAS_UInt32 targetEdma, XDAS_UInt32
         if (addr) {
             edmaConfig.srcCIdx  = pDevExt->edmaWordSize * pDevExt->numSers ;
             edmaConfig.srcAddr  = addr;
-            //Edma3_CacheFlush ((unsigned int) addr, (size+3)/4);
         }
         else {
             edmaConfig.srcBIdx  = 0;
             edmaConfig.srcAddr  = (unsigned int) &sap_UNDER[0];
-#if 0
-            //edmaConfig.cCnt = (SAP_UNDER_LEN * sizeof(int))/(edmaConfig.aCnt * edmaConfig.bCnt); //DJDBG
-            edmaConfig.cCnt = SAP_UNDER_LEN; //DJDBG, if underrun have frame of silence
-#endif
         }
     }
     edmaConfig.srcAddr  = (unsigned int) getGlobalAddr(edmaConfig.srcAddr);
@@ -1572,7 +1510,7 @@ Int SAP_EDMA_setupParam (DEV2_Handle device, XDAS_UInt32 targetEdma, XDAS_UInt32
 
     if (device->mode == DEV2_OUTPUT) {
         Log_info5("SAP: Inside SAP_EDMA_setupParam: size=0x%x, targetEdma = 0x%x, CCNT = %d with dest-addr: 0x%x and OPT=0x%x", size, targetEdma, edmaConfig.cCnt, edmaConfig.destAddr, edmaConfig.opt);
-        Log_info5("SAP: Inside SAP_EDMA_setupParam: aCnt=0x%x, bCnt = 0x%x; linked targetEdma = 0x%x with childEdma=0x%x on Edma=0x%x", edmaConfig.aCnt, edmaConfig.bCnt, targetEdma, childEdma, hEdma );
+        Log_info5("SAP: Inside SAP_EDMA_setupParam: aCnt=0x%x, bCnt = 0x%x; linked targetEdma = 0x%x with childEdma=0x%x on Edma=0x%x", edmaConfig.aCnt, edmaConfig.bCnt, targetEdma, childEdma, (xdc_IArg)hEdma );
         }
 
     return SIO2_OK;
index 747e7666cf98b7f4f354d17dfde56d890f203b6b..e7c6a64a40f1d8dde9714bcb6a58d54c2fe5ea73 100644 (file)
@@ -588,7 +588,7 @@ Int SAP_MCASP_reset (DEV2_Handle device)
     {
        //TRACE_TERSE1(( "SAP_MCASP_reset(0x%x) input device.", device));
         // disable FIFO if present
-        Log_info1("SAP_MCASP_reset(0x%x) input device.", device);
+        Log_info1("SAP_MCASP_reset(0x%x) input device.", (xdc_IArg)device);
         if (sapMcaspDrv.fifoPresent[mcaspNum])
             fifoBase[_MCASP_RFIFOCTL_OFFSET] &=
                 ~(MCASP_RFIFOCTL_RENA_ENABLE << _MCASP_RFIFOCTL_RENA_SHIFT);
@@ -626,7 +626,7 @@ Int SAP_MCASP_reset (DEV2_Handle device)
     else 
     {
        //TRACE_TERSE1(("SAP_MCASP_reset(0x%x) output device.", device));
-        Log_info1("SAP_MCASP_reset(0x%x) output device.", device);
+        Log_info1("SAP_MCASP_reset(0x%x) output device.", (xdc_IArg)device);
         // disable FIFO if present
         if (sapMcaspDrv.fifoPresent[mcaspNum])
             fifoBase[_MCASP_WFIFOCTL_OFFSET] &=