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raw | patch | inline | side by side (parent: 6793dc2)
raw | patch | inline | side by side (parent: 6793dc2)
author | Chitresh Gupta <chitresh.g@pathpartnertech.com> | |
Fri, 23 Dec 2016 11:02:33 +0000 (16:32 +0530) | ||
committer | Chitresh Gupta <chitresh.g@pathpartnertech.com> | |
Fri, 23 Dec 2016 11:02:33 +0000 (16:32 +0530) |
Update dcs7_params.c for using the DCS7 code after review.
Took UART LLD cancel() improvement from Latest PDK code base.
Took UART LLD cancel() improvement from Latest PDK code base.
index 3e933dd39c24b52dc732d4e1a7720ec7224a9a43..cccf5ad36fee14e5381c6ff2348dd0a428889ea7 100644 (file)
Program.sectMap[".ddr3Heap"] = "CORE0_DDR3";
/* FL: hack for DCS7, dcs7_cfg.c */
-Program.global.SDRAMHeap = Program.global.heapMemDdr3;
+Program.global.Heap = Program.global.heapMemDdr3;
Program.sectMap["platform_lib"] = "L2SRAM";
//Program.sectMap[".stack"] = "L2SRAM";
diff --git a/pasdk/test_dsp/application/itopo/evmk2g/dcs7_params.c b/pasdk/test_dsp/application/itopo/evmk2g/dcs7_params.c
index c1d6aa47e34a9421e2a1a1d826fd80706d4c3816..c46edc2a96760b82debe6209fe7b34ef98e68f2d 100644 (file)
//
//
-#include <dcs7.h>
-#include <dcs7_params.h>
+/* I2C LLD Header files */
+#include <ti/drv/i2c/I2C.h>
+/* SPI LLD Header files */
+#include <ti/drv/spi/SPI.h>
+/* UART LLD Header files */
+#include <ti/drv/uart/UART.h>
+#include "dcs7.h"
+#include "dcs7_params.h"
+#include "dcs7_priv.h"
#include "dcs7_medialayer.h"
-#ifdef UARTCALLBACK
-extern void UART_transferCallback(UART_Handle handle,
- void *buffer, size_t count);
-#endif
-
-#ifdef SPICALLBACK
-extern void SPI_transferCallback(UART_Handle handle,
- void *buffer, size_t count);
-#endif
/* SPI parameters structure Slave mode*/
SPI_Params spiParams =
{
#ifdef SPICALLBACK
- SPI_MODE_CALLBACK, /* transferMode */
-#else
- SPI_MODE_BLOCKING, /* transferMode */
+ SPI_MODE_CALLBACK, /* transferMode */
+#else
+ SPI_MODE_BLOCKING, /* transferMode */
#endif
Semaphore_PendState_WAIT_FOREVER, /* transferTimeout */
#ifdef SPICALLBACK
- &SPI_transferCallback,
+ (SPI_CallbackFxn)&SPI_transferCallback,
#else
- NULL, /* transferCallbackFxn */
+ NULL, /* transferCallbackFxn */
#endif
- SPI_SLAVE, /* mode */
- 1000000, /* bitRate */
- 8, /* dataSize */
- SPI_POL0_PHA0, /* frameFormat */
- NULL /* custom */
+ SPI_SLAVE, /* mode */
+ 1000000, /* bitRate */
+ DCS7_PARAMS_DEV_SPI_CLEN_16, /* dataSize */
+ SPI_POL0_PHA0, /* frameFormat */
+ NULL /* custom */
};
const DCS7_Params_Dev_Spi DCS7_PARAMS_DEV_SPI =
{
- sizeof(DCS7_Params_Dev_Spi),
- NULL,
- &spiParams,
- {0, NULL, NULL, NULL}
+ sizeof(DCS7_Params_Dev_Spi), /* size of the structure */
+ DCS7_PARAMS_DEV_SPI_NP_4_SCS, /* number of pins */
+ DCS7_PARAMS_DEV_SPI_ENAHIZ_DIS, /* SPIENA pin mode */
+ 0,0,
+ 0, /* error mask */
+ NULL, /* handle to SPI lld */
+ &spiParams, /* SPI Initialization param */
+ {0, NULL, NULL, NULL} /* SPI transfer info */
};
const DCS7_Params_Dev_I2c DCS7_PARAMS_DEV_I2C =
{
- sizeof(DCS7_Params_Dev_I2c),
- NULL,
- {I2C_MODE_BLOCKING, NULL, I2C_100kHz, NULL, I2C_SLAVE},
- {NULL, 0, NULL, 0, 0, NULL, NULL},
- 0x11
+ sizeof(DCS7_Params_Dev_I2c), /* size of the structure */
+ NULL, /* handle to I2C lld, only dynamic init parameter */
+ {I2C_MODE_BLOCKING, NULL, I2C_100kHz, NULL, I2C_SLAVE}, /* I2C Initialization parameters */
+ {NULL, 0, NULL, 0, 0, NULL, NULL}, /* I2C transfer info */
+ 0x11, /* Own slave address of K2G */
+ 0,0,0, /* reserved */
+ 0 /* Error mask */
};
const DCS7_Params_Dev_Uart DCS7_PARAMS_DEV_UART =
{
- sizeof(DCS7_Params_Dev_Uart),
- 0, // emask
- NULL, // hUart
+ sizeof(DCS7_Params_Dev_Uart), // size of the structure
+ 0, // emask
+ NULL, // hUart
#ifdef UARTCALLBACK
- &UART_transferCallback, // transferCallbackFxn
+ &UART_transferCallback, // transferCallbackFxn
+ NULL, // hSwi
+ NULL, // hCallback
#endif
- 0, // isEMDAConfigured
- SRECORD_RES_MAX_S1_CNT * 72 /*ASCII_SRECORD_S1_MAX_SIZE*/, // scratchBufSize
- NULL, // scratchBuf
- {0}, // uartParams
- 19200
+ 0, // isEMDAConfigured
+ SRECORD_RES_MAX_S1_CNT * ASCII_SRECORD_S1_MAX_SIZE, // scratchBufSize
+ NULL, // scratchBuf
+ {0}, // uartParams
+ 19200 // Baudrate
};
const DCS7_Params_Dev DCS7_PARAMS_DEV =
512,
/* DCS7 device parameters */
(DCS7_Params_Dev*)&DCS7_PARAMS_DEV,
- /* DCS7 log param */
- (void*) &DCS7Trace,
};
void DCS7_errorInit()
index b8d82156136c87a972d995d305275fd5adae776f..365b6cb8a51c7a2ef7570279d5244951ddfbb2af 100644 (file)
Int gSysInit=0;
-#define TASK_AFP_PRI ( 3 )//( 1 ) // (***) FL: temporary fix for PASDK-64
-#define TASK_AIP_PRI ( 1 )//( 2 )
+#define TASK_AFP_PRI ( 1 )//( 1 ) // (***) FL: temporary fix for PASDK-64
+#define TASK_AIP_PRI ( 2 )//( 2 )
#define TASK_SSP_PRI ( 1 )
-#define TASK_ASIP_PRI ( 2 )//( 3 )
-#define TASK_ASOP_PRI ( 2 )//( 3 )
+#define TASK_ASIP_PRI ( 3 )//( 3 )
+#define TASK_ASOP_PRI ( 3 )//( 3 )
#define __TASK_NAME__ "TaskSysInit"
Log_info0("Enter taskSysInitFxn()");
+ // Create Shared DDR region as non-Cacheable, Before IPC attach
+ // TODO: remove hardcoded address and get correct values from .bld
+ { // base: 0x81000000, len: 0x01000000,
+ UInt Common2_DDR3_MAR_base = 0x01848204;
+ UInt Common2_DDR3_base = 0x81000000;
+ UInt Common2_DDR3_len = 0x01000000;
+ // disable cache for common2 DDR3
+ Cache_setMar(Common2_DDR3_base, Common2_DDR3_len, Cache_Mar_DISABLE);
+ }
+
//taskPriAfp = Task_setPri(TaskAfp, -1);
//taskPriAip = Task_setPri(TaskAip, -1);
//taskPriAsip = Task_setPri(TaskAsip, -1);
//} while ((status < 0) && (status == Ipc_E_NOTREADY));
} while (status != Ipc_S_SUCCESS);
- // Create Shared DDR region as non-Cacheable
- // TODO: remove hardcoded address and get correct values from .bld
- { // base: 0x81000000, len: 0x01000000,
- UInt Common2_DDR3_MAR_base = 0x01848204;
- UInt Common2_DDR3_base = 0x81000000;
- UInt Common2_DDR3_len = 0x01000000;
- // disable cache for common2 DDR3
- Cache_setMar(Common2_DDR3_base, Common2_DDR3_len, Cache_Mar_DISABLE);
- }
-
/* Initialize (IPC) ASP master messaging */
/* Note: MessageQ_open() called in this function.
MessageQ_open() blocks. */
diff --git a/psdk_cust/pdk_k2g_1_0_1_0_eng/packages/ti/drv/uart/src/v0/UARTDMA_v0.c b/psdk_cust/pdk_k2g_1_0_1_0_eng/packages/ti/drv/uart/src/v0/UARTDMA_v0.c
index 983b63a66683c3b52c49eb367876df7bb5646ee7..63cf3dc952a617a38dc81817754d7e6e2c4fde25 100644 (file)
object->readCount = 0;
UART_osalHardwareIntRestore(key);
}
+
+ /* Flush the RX FIFO */
+ while (UART_charGetNonBlocking_v0(hwAttrs->baseAddr) != (int8_t)(-1));
+
return;
}
diff --git a/psdk_cust/pdk_k2g_1_0_1_0_eng/packages/ti/drv/uart/src/v0/UART_v0.c b/psdk_cust/pdk_k2g_1_0_1_0_eng/packages/ti/drv/uart/src/v0/UART_v0.c
index e3eec6c38853c1211273c2ad4f234270351cb717..addc1254c08d13511298efa89787ebc7b58ab4d3 100644 (file)
{
uint32_t key;
UART_V0_Object *object;
+ UART_HwAttrs const *hwAttrs = handle->hwAttrs;
/* Get the pointer to the object */
object = handle->object;
((UART_HwAttrs const *)(handle->hwAttrs))->baseAddr,
object->readCount);
}
+
+ /* Flush the RX FIFO */
+ while (UART_charGetNonBlocking_v0(hwAttrs->baseAddr) != (int8_t)(-1));
+
return;
}