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raw | patch | inline | side by side (from parent 1: ca948e1)
author | Frank Livingston <frank-livingston@ti.com> | |
Wed, 6 Jun 2018 21:09:19 +0000 (16:09 -0500) | ||
committer | Frank Livingston <frank-livingston@ti.com> | |
Wed, 6 Jun 2018 21:09:19 +0000 (16:09 -0500) |
pasdk/test_dsp/framework/audioStreamOutIo.c | patch | blob | history |
diff --git a/pasdk/test_dsp/framework/audioStreamOutIo.c b/pasdk/test_dsp/framework/audioStreamOutIo.c
index fbc05c0d78720a5b21f68ec10578d708b3c3b1ab..7a5b129509b046950ca8e7f97ff712e15d57321c 100644 (file)
// configure stride according to selected McASP LLD configuration
pOut->stride = pReqLldCfg->mcaspChanParams->noOfSerRequested *
pReqLldCfg->mcaspChanParams->noOfChannels;
+
+ pOut->rateX = 1.; // intialize rateX
}
else
{
return ((getVal & 0xff) | ASPERR_RATE_CHECK);
}
#endif // FL, New IO
- // FL: ugly little experiment
- //*(volatile UInt32 *)0x23400B0 |= 7; // set CLKXDIV to 7
+ if (pOut->rateX != rateX)
+ {
+ UInt32 regVal;
+
+ //
+ // "Proof on concept" code for McASP LLD API to change bit clock divider.
+ //
+
+ // Initialize divider value.
+ // This works for AHCLKX input from HDMI & sample rate = 44.1,48,88.2,96,192 kHz.
+ divider = 2;
+
+ // Update divider based on calculated rateX
+ divider /= rateX;
+
+ // Experimental code: directly write CLKXDIV
+ regVal = *(volatile UInt32 *)0x23400B0;
+ regVal &= ~0x1F; // mask off CLKXDIV bits
+ //regVal |= 7; // set CLKXDIV for 48 kHz
+ //regVal |= 3; // set CLKXDIV for 96 kHz
+ //regVal |= 1; // set CLKXDIV for 192 kHz
+ regVal |= (divider-1); // set CLKXDIV
+ *(volatile UInt32 *)0x23400B0 = regVal;
+
+ pOut->rateX = rateX;
+ }
}
}