PASDK69: Created Non-Cacheable memory region.
authorChitresh Gupta <chitresh.g@pathpartnertech.com>
Thu, 1 Dec 2016 09:31:41 +0000 (15:01 +0530)
committerChitresh Gupta <chitresh.g@pathpartnertech.com>
Thu, 1 Dec 2016 09:31:41 +0000 (15:01 +0530)
pasdk/shared/config.bld
pasdk/shared/ipc.cfg.xs
pasdk/test_arm/application/app.cfg
pasdk/test_dsp/application/app.cfg
pasdk/test_dsp/application/main.c

index 19b23f1133355a8987cf906874813828392905b9..f61e1b65f136da0a9b661238545ce7b876646b18 100644 (file)
@@ -48,8 +48,9 @@ var Build = xdc.useModule('xdc.bld.BuildEnvironment');
  *    0C0C_0000   0004_0000  ( 256 KB)  CORE_MSMC   (code, data)
  *    8000_0000   0020_0000  (   2 MB)  SR_0        (ipc)
  *    8020_0000   0080_0000  (   8 MB)  SR_DDR3     (ipc:data)
- *    80A0_0000   0080_0000  (   8 MB)  COMMON_DDR3 (data)
- *    8120_0000   0400_0000  (  64 MB)  HOST_DDR3   (code, data)
+ *    80A0_0000   0060_0000  (   6 MB)  COMMON_DDR3 (data)
+ *    8100_0000   0100_0000  (  16 MB)  COMMON2_DDR3(code, data)      // aligned to MAR memory region  
+ *    8200_0000   0320_0000  (  50 MB)  HOST_DDR3   (code, data)
  *    8520_0000   0400_0000  (  64 MB)  CORE0_DDR3  (code, data)
  *    8920_0000   76E0_0000  (1902 MB)  DDR3        (code, data)
  */
@@ -74,9 +75,15 @@ var SR_DDR3 = {
 
 var COMMON_DDR3 = {
         name: "COMMON_DDR3", space: "data", access: "RW",
-        base: 0x80A00000, len: 0x00800000,
+        base: 0x80A00000, len: 0x00600000,
         comment: "COMMON DDR3 Memory"
     };
+    
+var COMMON2_DDR3 = {  // Common Structure for shared data, Non cacheable
+        name: "COMMON2_DDR3", space: "data", access: "RW",
+        base: 0x81000000, len: 0x01000000,
+        comment: "COMMON 2 PP DDR3 Memory"
+    };
 
 var DDR3 = {
         name: "DDR3", space: "code/data", access: "RW",
@@ -101,9 +108,11 @@ Build.platformTable["ti.platforms.evmTCI66AK2G02:host"] = {
         
         ["COMMON_DDR3", COMMON_DDR3], 
         
+        ["COMMON2_DDR3", COMMON2_DDR3], 
+        
         [ "HOST_DDR3",  {
             name: "HOST_DDR3", space: "code/data", access: "RWX",
-            base: 0x81200000, len: 0x04000000,
+            base: 0x82000000, len: 0x03200000,
             comment: "HOST DDR3"
         }], 
         
@@ -159,6 +168,8 @@ Build.platformTable["ti.platforms.evmTCI66AK2G02:core0"] = {
         
         ["COMMON_DDR3", COMMON_DDR3], 
         
+        ["COMMON2_DDR3", COMMON2_DDR3], 
+        
         [ "CORE0_DDR3",  {
             name: "CORE0_DDR3", space: "code/data", access: "RWX",
             base: 0x85200000, len: 0x04000000,
index 727a293a36f689d33b2829007d146423c6df176e..505f3268fe71395c07200839daa126652b7dcf0d 100644 (file)
@@ -53,6 +53,8 @@ Ipc.sr0MemorySetup = true;
 /* shared region configuration */
 var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
 
+SharedRegion.numEntries = 4;
+
 /* configure SharedRegion #0 (IPC) */
 var Sr0Mem = Program.cpu.memoryMap["SR_0"];
 
@@ -96,3 +98,18 @@ SharedRegion.setEntryMeta(2,
         createHeap:     true
     })
 );
+
+/* configure SharedRegion #3 (DDR3) */
+var SrDDr3_2Mem = Program.cpu.memoryMap["COMMON2_DDR3"];
+
+SharedRegion.setEntryMeta(3,
+    new SharedRegion.Entry({
+        name:           "COMMON2_DDR3",
+        base:           SrDDr3_2Mem.base,
+        len:            SrDDr3_2Mem.len,
+        ownerProcId:    1,
+        isValid:        true,
+        cacheEnable:    false,
+        createHeap:     true
+    })
+);
index 9ac159597358b6573a4bf44262fd452bf6795048..eb71a43066ed48962d43f837443147fb537ee455 100644 (file)
@@ -144,6 +144,39 @@ BIOS.heapSize = 0x2000; // from pa.cfg
 BIOS.heapSection = ".systemHeap";
 Program.sectMap[".systemHeap"] = "HOST_DDR3";
 
+if (1)        // Disable cache on ARM for the shared memory region
+{
+       var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
+       
+       // descriptor attribute structure
+       var attrs = new Mmu.DescriptorAttrs();
+       
+       // Note: If running in SMP mode, all page table entries for memory
+       //       shared between the SMP cores should mark the memory as
+       //       inner-shareable. This is to ensure that the cached copy of
+       //       the memory region is kept coherent accross cores.
+       
+       Mmu.initDescAttrsMeta(attrs);
+       attrs.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
+       attrs.shareable = 2; //3;                      // 3 - inner-sharerable
+       attrs.attrIndx = 0;//2;                       // MAIR0 Byte2 describes
+                                                 // memory attributes for
+                                                 // this level2 entry
+       
+       // write memory region attribute in mairRegAttr[2] i.e. MAIR0 Reg Byte2
+       Mmu.setMAIRMeta(0/*2*/, 0x44/*0xff*/);              // Mark mem regions as non-cacheable
+       
+       /* Get a handle to the C64P Target */
+       //var COMMON2_DDR3 = "" + java.lang.System.getenv("COMMON2_DDR3");
+       var COMMON2_DDR3_base = 0x81000000;
+       var COMMON2_DDR3_end = 0x81000000 + 0x01000000;
+       // Set the descriptor for each entry in the address range
+       for (var i=COMMON2_DDR3_base; i < COMMON2_DDR3_end; i = i + 0x00200000) {
+           // Each 'BLOCK' descriptor entry spans a 2MB address range
+           Mmu.setSecondLevelDescMeta(i, i, attrs);
+       }
+}
+
 /*
  * Build a custom SYS/BIOS library from sources.
  */
index 49a8a7750357f8293e1bbfd879e3785e5ea50012..8a21a9ed944988e3e7d50929112c1fd1ab8fd019 100644 (file)
@@ -58,6 +58,7 @@ var Text            = xdc.useModule('xdc.runtime.Text');
 var BIOS            = xdc.useModule('ti.sysbios.BIOS');
 var Hwi             = xdc.useModule('ti.sysbios.hal.Hwi');
 var Cache           = xdc.useModule('ti.sysbios.hal.Cache');
+var Cachec66       = xdc.useModule('ti.sysbios.family.c66.Cache');
 var Timer           = xdc.useModule('ti.sysbios.hal.Timer');
 var HeapBuf         = xdc.useModule('ti.sysbios.heaps.HeapBuf');
 var HeapMem         = xdc.useModule('ti.sysbios.heaps.HeapMem');
index f549f004843d2b9ddc13cddaf6720919e89da40c..539176f5395d42d445af59ba908e9a3f46220e7e 100644 (file)
@@ -43,6 +43,8 @@ All rights reserved.
 #include <xdc/runtime/System.h>
 #include <ti/sysbios/BIOS.h>
 #include <ti/ipc/Ipc.h>
+#include <ti/sysbios/hal/Cache.h>
+#include <ti/sysbios/family/c66/Cache.h>
 
 #include "fwkSim.h"
 
@@ -132,6 +134,14 @@ Int main()
     initDev2();
 #endif // SIMULATE_SIO
     
+    {   // base: 0x81000000, len: 0x01000000,
+        UInt Common2_DDR3_MAR_base = 0x01848204;
+        UInt Common2_DDR3_base = 0x81000000;
+        UInt Common2_DDR3_len = 0x01000000;
+        // disable cache for common2 DDR3
+        Cache_setMar(Common2_DDR3_base, Common2_DDR3_len, Cache_Mar_DISABLE);
+    }
+
     Log_info0("IPC start");
     // Initialize IPC
     status = Ipc_start();