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raw | patch | inline | side by side (parent: 0dbc6ed)
raw | patch | inline | side by side (parent: 0dbc6ed)
author | Jianzhong Xu <a0869574@ti.com> | |
Tue, 12 Jun 2018 14:35:03 +0000 (10:35 -0400) | ||
committer | Jianzhong Xu <a0869574@ti.com> | |
Tue, 12 Jun 2018 14:35:03 +0000 (10:35 -0400) |
diff --git a/pasdk/test_dsp/application/itopo/evmk2g/atboot.c b/pasdk/test_dsp/application/itopo/evmk2g/atboot.c
index 3140c4bdddd33354df7c0c15ad7a3ef6de008ca7..270de83b30dad748578cdd5c89a2e22028d5fd08 100644 (file)
writeVOLOffsetMasterN(0x7fff), \
writeSYSRecreationModeDirect, \
writeSYSChannelConfigurationRequestSurround4_1, \
writeVOLOffsetMasterN(0x7fff), \
writeSYSRecreationModeDirect, \
writeSYSChannelConfigurationRequestSurround4_1, \
- execPAIInHDMIStereo, \
- execPAIOutAnalog
+ execPAIInAnalog, \
+ execPAIOutAnalogSlave
#else
//Not DTS_ATBOOT_CFG
#else
//Not DTS_ATBOOT_CFG
diff --git a/pasdk/test_dsp/application/itopo/evmk2g/mcasp_cfg.c b/pasdk/test_dsp/application/itopo/evmk2g/mcasp_cfg.c
index b3f1f14f3c96149c007e236092fff16124e6b7c9..bf4886aa02e1102621d8d1437e25fd9023d8e79f 100644 (file)
/* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */
{
// /* .aclkxctl = */ 0X000000E1, // Transmit bit clock divide ratio = 2 --> works for 48khz PCM but not for DDP
/* .xevtctl = */ 0x00000000, /* DMA request is enabled or disabled */
{
// /* .aclkxctl = */ 0X000000E1, // Transmit bit clock divide ratio = 2 --> works for 48khz PCM but not for DDP
- /* .aclkxctl = */ 0X000000E7, // Transmit bit clock divide ratio = 8 --> working for DDP/MAT/THD 48khz but not for PCM
-// /* .aclkxctl = */ 0X000000E3, // Transmit bit clock divide ratio = 4 --> THD 96khz
-// /* .aclkxctl = */ 0X000000E1, // Transmit bit clock divide ratio = 2 --> THD 192khz
+ /* .aclkxctl = */ 0X000000E7, // Transmit bit clock divide ratio = 8 --> working for Dolby/DTS 48khz but not for PCM
+// /* .aclkxctl = */ 0X000000E3, // Transmit bit clock divide ratio = 4 --> Dolby/DTS 96khz
+// /* .aclkxctl = */ 0X000000E1, // Transmit bit clock divide ratio = 2 --> Dolby/DTS 192khz
/* .ahclkxctl = */ 0x00004000,
/* .xclkchk = */ 0x00000000
},
/* .ahclkxctl = */ 0x00004000,
/* .xclkchk = */ 0x00000000
},
&mcaspRxChanParamHDMIStereo,
0x23,
0x63,
&mcaspRxChanParamHDMIStereo,
0x23,
0x63,
- 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for DIR/HDMI
+ 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for HDMI
0x2,
CSL_MCASP_0,
MCASP_INPUT,
0x2,
CSL_MCASP_0,
MCASP_INPUT,
&mcaspRxChanParamHDMI,
0x23,
0x63,
&mcaspRxChanParamHDMI,
0x23,
0x63,
- 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for DIR/HDMI
+ 0x02000000, // Set Amute pin as output since mcasp0 is both Rx & Tx for HDMI
0x2,
CSL_MCASP_0,
MCASP_INPUT,
0x2,
CSL_MCASP_0,
MCASP_INPUT,
return (Aud_EOK);
} /* mcasplldChanCreate */
return (Aud_EOK);
} /* mcasplldChanCreate */
+
/* Nothing past this point */
/* Nothing past this point */
index 0c8ab2d8efde5e754c5f182ff6363f5e038a0312..01a35510dca9d63974f9ac7b7b90d8e94d53e377 100644 (file)
Int status;
Aud_STATUS AudStatus;
Int k;
Int status;
Aud_STATUS AudStatus;
Int k;
- //Board_initCfg cfg;
+ Board_initCfg cfg;
Log_info0("Enter main()");
Log_info0("Enter main()");
#endif
/* initialize board */
#endif
/* initialize board */
- // board init is handled by GEL files or SBL
- //cfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK;
- //Board_init(cfg);
+ cfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK;
+ Board_init(cfg);
evmI2CInit(I2C_PORT_0);
evmI2CInit(I2C_PORT_1);
evmI2CInit(I2C_PORT_2);
evmI2CInit(I2C_PORT_0);
evmI2CInit(I2C_PORT_1);
evmI2CInit(I2C_PORT_2);
diff --git a/pasdk/test_dsp/framework/audioStreamInpProcNewIO.c b/pasdk/test_dsp/framework/audioStreamInpProcNewIO.c
index f1d7dc41b699b0f3830cbb1069a512f9050821e5..e5b962961cbc7912e2cada5dff78f42ac2c6a84f 100644 (file)
// always point to PCM data from 1st I2S (out of 4 for HDMI 4xI2S)
ioBuffAdjustDelay(pInp->hIoBuff, pInp->phyXferSize);
// always point to PCM data from 1st I2S (out of 4 for HDMI 4xI2S)
ioBuffAdjustDelay(pInp->hIoBuff, pInp->phyXferSize);
+ // Mute decoder output during PCM transition
+ pAstCfg->xInp[zMD].inpBufConfig.deliverZeros = TRUE;
+
// Go to transition state to switch to PCM
pInp->asipState = ASIT_PCM_TRANSITION;
TRACE_VERBOSE0("PCM stream detected. Go to PCM transition. ");
// Go to transition state to switch to PCM
pInp->asipState = ASIT_PCM_TRANSITION;
TRACE_VERBOSE0("PCM stream detected. Go to PCM transition. ");
pInp->pcmSwitchHangOver--;
if(pInp->pcmSwitchHangOver == 0) {
pInp->asipState = ASIT_DECODE_PROCESSING;
pInp->pcmSwitchHangOver--;
if(pInp->pcmSwitchHangOver == 0) {
pInp->asipState = ASIT_DECODE_PROCESSING;
+
+ // Unmute decoder output after PCM transition
+ pAsitCfg->pAstCfg->xInp[zMD].inpBufConfig.deliverZeros = FALSE;
}
else {
; // stay in this state
}
else {
; // stay in this state
sourceConfig = (Int)sharedMemReadInt8(&(pAstCfg->xDec[zMD].decodeStatus.sourceSelect),
GATEMP_INDEX_DEC);
sourceConfig = (Int)sharedMemReadInt8(&(pAstCfg->xDec[zMD].decodeStatus.sourceSelect),
GATEMP_INDEX_DEC);
- if(autoDetStatus->syncState == IODATA_SYNC_PCM) {
- // Bitstream preamble is not found and it times out -> assume this is PCM
- deliverZeros = autoDetStatus->deliverZeros;
- if (sourceConfig == PAF_SOURCE_PCM || sourceConfig == PAF_SOURCE_DSD1 ||
- sourceConfig == PAF_SOURCE_DSD2 || sourceConfig == PAF_SOURCE_DSD3) {
- // set to one -- ensures that PCM decode calls made before data is
- // available will result in zero output.
- // (mostly needed for PA15 since, currently, all other frameworks
- // require a frame of data before the first decode call.
- deliverZeros = TRUE; // override deliverZeros returned by ioDataControl
- }
-
- // update input buffer config structure
- pBufConfig->deliverZeros = deliverZeros;
- }
-
- //JXTODO: decide what to do with hRxSio
- //temporary - does ARM use hRxSio or just check if it is not NULL?
+ // temporary - does ARM use hRxSio or just check if it is not NULL?
pAstCfg->xInp[zMD].hRxSio = pInp->hIoData;
pAstCfg->xInp[zMD].pInpBuf = &(pAstCfg->xInp[zMD].inpBufConfig);
pAstCfg->xInp[zMD].hRxSio = pInp->hIoData;
pAstCfg->xInp[zMD].pInpBuf = &(pAstCfg->xInp[zMD].inpBufConfig);