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raw | patch | inline | side by side (from parent 1: 57d1180)
raw | patch | inline | side by side (from parent 1: 57d1180)
author | Frank Livingston <frank-livingston@ti.com> | |
Thu, 11 Aug 2016 20:07:59 +0000 (15:07 -0500) | ||
committer | Frank Livingston <frank-livingston@ti.com> | |
Thu, 11 Aug 2016 20:07:59 +0000 (15:07 -0500) |
In UART LLD interrupt implementation (callback mode) the write callback
function does not always mean completion of UART Tx operation.
Write callback is invoked when THR is empty, but it does not indicate both
the transmitter FIFO and the transmitter shift register (UART_TSR) are
empty. Under such condition if UART is closed, it will terminate the UART
previous ongoing transfer.
function does not always mean completion of UART Tx operation.
Write callback is invoked when THR is empty, but it does not indicate both
the transmitter FIFO and the transmitter shift register (UART_TSR) are
empty. Under such condition if UART is closed, it will terminate the UART
previous ongoing transfer.
pdk_k2g_1_0_1/packages/ti/drv/uart/src/v0/UART_v0.c | patch | blob | history |
diff --git a/pdk_k2g_1_0_1/packages/ti/drv/uart/src/v0/UART_v0.c b/pdk_k2g_1_0_1/packages/ti/drv/uart/src/v0/UART_v0.c
index 07dbee3e5a8e663871e185cbd7da6cb9d376a77b..e3eec6c38853c1211273c2ad4f234270351cb717 100644 (file)
object->writeSize = UART_writeData_v0((UART_Handle)arg, object->writeSize);
if ((object->writeSize) == 0U)
{
+ while (!UART_fifoEmpty_v0(hwAttrs->baseAddr));
UART_intDisable_v0(hwAttrs->baseAddr, UART_INT_THR);
/* Reset the write buffer so we can pass it back */
object->writeBuf = (uint8_t *)object->writeBuf - object->writeCount;
UART_drv_log2("UART:(%p) Write finished, "
"%d bytes written",
hwAttrs->baseAddr, object->writeCount);
+
}
}