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raw | patch | inline | side by side (parent: fcd53e6)
raw | patch | inline | side by side (parent: fcd53e6)
author | Govind Jeyaram <govind.j@ti.com> | |
Wed, 20 Sep 2017 22:46:01 +0000 (15:46 -0700) | ||
committer | Govind Jeyaram <govind.j@ti.com> | |
Wed, 20 Sep 2017 22:46:01 +0000 (15:46 -0700) |
pasdk/test_dsp/sap/audio_dc_cfg.c | patch | blob | history | |
pasdk/test_dsp/sap/audio_dc_cfg.h | patch | blob | history |
index 51d5ec71cdf1b492adf937c46fccf322e3153cd2..6c5a1bbecb75da99d665e4c316cb493a1370ec05 100644 (file)
* The I2C clk is set to run at 400 (384) KHz *
* *
* ------------------------------------------------------------------------ */
+
+CSL_I2cRegsOvly pI2CBase = (CSL_I2cRegsOvly)CSL_I2C_1_DATA_CFG_REGS;
+
Int16 DA10x_I2C_init()
{
- I2C_ICMDR = 0; // Reset I2C
- I2C_ICPSC = 9; // Prescale to get 10MHz I2C internal
- I2C_ICCLKL = 7; // Config clk LOW for 400kHz
- I2C_ICCLKH = 7; // Config clk HIGH for 400kHz
- I2C_ICMDR |= ICMDR_IRS; // Release I2C from reset
+ pI2CBase->ICMDR = 0; // Reset I2C
+ pI2CBase->ICPSC = 9; // Prescale to get 10MHz I2C internal
+ pI2CBase->ICCLKL = 7; // Config clk LOW for 400kHz
+ pI2CBase->ICCLKH = 7; // Config clk HIGH for 400kHz
+ pI2CBase->ICMDR |= ICMDR_IRS; // Release I2C from reset
return 0;
}
* ------------------------------------------------------------------------ */
Int16 DA10x_I2C_close()
{
- I2C_ICMDR = 0; // Reset I2C
+ pI2CBase->ICMDR = 0; // Reset I2C
return 0;
}
{
Int32 timeout, i;
- I2C_ICCNT = len; // Set length
- I2C_ICSAR = i2c_addr; // Set I2C slave address
- I2C_ICMDR = ICMDR_STT // Set for Master Write
+ pI2CBase->ICCNT = len; // Set length
+ pI2CBase->ICSAR = i2c_addr; // Set I2C slave address
+ pI2CBase->ICMDR = ICMDR_STT // Set for Master Write
| ICMDR_TRX
| ICMDR_MST
| ICMDR_IRS
for ( i = 0 ; i < len ; i++ )
{
- I2C_ICDXR = data[i]; // Write
+ pI2CBase->ICDXR = data[i]; // Write
timeout = i2c_timeout;
do
DA10x_I2C_reset( );
return -1;
}
- } while ( ( I2C_ICSTR & ICSTR_ICXRDY ) == 0 );// Wait for Tx Ready
+ } while ( ( pI2CBase->ICSTR & ICSTR_ICXRDY ) == 0 );// Wait for Tx Ready
}
- I2C_ICMDR |= ICMDR_STP; // Generate STOP
+ pI2CBase->ICMDR |= ICMDR_STP; // Generate STOP
return 0;
{
Int32 timeout, i;
- I2C_ICCNT = len; // Set length
- I2C_ICSAR = i2c_addr; // Set I2C slave address
- I2C_ICMDR = ICMDR_STT // Set for Master Read
+ pI2CBase->ICCNT = len; // Set length
+ pI2CBase->ICSAR = i2c_addr; // Set I2C slave address
+ pI2CBase->ICMDR = ICMDR_STT // Set for Master Read
| ICMDR_MST
| ICMDR_IRS
| ICMDR_FREE;
DA10x_I2C_reset( );
return -1;
}
- } while ( ( I2C_ICSTR & ICSTR_ICRRDY ) == 0 );// Wait for Rx Ready
+ } while ( ( pI2CBase->ICSTR & ICSTR_ICRRDY ) == 0 );// Wait for Rx Ready
- data[i] = I2C_ICDRR; // Read
+ data[i] = pI2CBase->ICDRR; // Read
}
- I2C_ICMDR |= ICMDR_STP; // Generate STOP
+ pI2CBase->ICMDR |= ICMDR_STP; // Generate STOP
return 0;
}
index c2fbb8cc3f38f920102263469d7f6c94306563a4..1d394c9460a1f1a7dec1a20dc260095637320498 100644 (file)
#include "audk2g.h"
#include "audk2g_audio.h"
+
+#include <ti/csl/cslr_i2c.h>
+#include <ti/csl/soc.h>
/**
* \brief ADC configuration parameter structure
*
#define Int32 int
#define Int16 short
#define Int8 char
+
/* ------------------------------------------------------------------------ *
* *
* I2C Controller *
* *
* ------------------------------------------------------------------------ */
-#define I2C_BASE 0x2530400U
-#define I2C_OAR *( volatile Uint32* )( I2C_BASE + 0x00 )
-#define I2C_ICIMR *( volatile Uint32* )( I2C_BASE + 0x04 )
-#define I2C_ICSTR *( volatile Uint32* )( I2C_BASE + 0x08 )
-#define I2C_ICCLKL *( volatile Uint32* )( I2C_BASE + 0x0C )
-#define I2C_ICCLKH *( volatile Uint32* )( I2C_BASE + 0x10 )
-#define I2C_ICCNT *( volatile Uint32* )( I2C_BASE + 0x14 )
-#define I2C_ICDRR *( volatile Uint32* )( I2C_BASE + 0x18 )
-#define I2C_ICSAR *( volatile Uint32* )( I2C_BASE + 0x1C )
-#define I2C_ICDXR *( volatile Uint32* )( I2C_BASE + 0x20 )
-#define I2C_ICMDR *( volatile Uint32* )( I2C_BASE + 0x24 )
-#define I2C_ICIVR *( volatile Uint32* )( I2C_BASE + 0x28 )
-#define I2C_ICEMDR *( volatile Uint32* )( I2C_BASE + 0x2C )
-#define I2C_ICPSC *( volatile Uint32* )( I2C_BASE + 0x30 )
-#define I2C_ICPID1 *( volatile Uint32* )( I2C_BASE + 0x34 )
-#define I2C_ICPID2 *( volatile Uint32* )( I2C_BASE + 0x38 )
+
+typedef volatile CSL_I2cRegs *CSL_I2cRegsOvly;
/* I2C Field Definitions */
-#define ICOAR_MASK_7 0x007F
-#define ICOAR_MASK_10 0x03FF
-#define ICSAR_MASK_7 0x007F
-#define ICSAR_MASK_10 0x03FF
-#define ICOAR_OADDR 0x007f
-#define ICSAR_SADDR 0x0050
-
-#define ICSTR_SDIR 0x4000
-#define ICSTR_NACKINT 0x2000
-#define ICSTR_BB 0x1000
-#define ICSTR_RSFULL 0x0800
-#define ICSTR_XSMT 0x0400
-#define ICSTR_AAS 0x0200
-#define ICSTR_AD0 0x0100
-#define ICSTR_SCD 0x0020
+
#define ICSTR_ICXRDY 0x0010
#define ICSTR_ICRRDY 0x0008
-#define ICSTR_ARDY 0x0004
-#define ICSTR_NACK 0x0002
-#define ICSTR_AL 0x0001
-#define ICMDR_NACKMOD 0x8000
#define ICMDR_FREE 0x4000
#define ICMDR_STT 0x2000
-#define ICMDR_IDLEEN 0x1000
#define ICMDR_STP 0x0800
#define ICMDR_MST 0x0400
#define ICMDR_TRX 0x0200
-#define ICMDR_XA 0x0100
-#define ICMDR_RM 0x0080
-#define ICMDR_DLB 0x0040
#define ICMDR_IRS 0x0020
-#define ICMDR_STB 0x0010
-#define ICMDR_FDF 0x0008
-#define ICMDR_BC_MASK 0x0007
+
#endif /* _AUDIO_DC_CFG_H_ */