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raw | patch | inline | side by side (parent: 5dce923)
raw | patch | inline | side by side (parent: 5dce923)
| author | Frank Livingston <frank-livingston@ti.com> | |
| Mon, 27 Jun 2016 14:58:39 +0000 (09:58 -0500) | ||
| committer | Frank Livingston <frank-livingston@ti.com> | |
| Mon, 27 Jun 2016 14:58:39 +0000 (09:58 -0500) |
diff --git a/procsdk_audio_x_xx_xx_xx/test_dsp/sap/audio_dc_cfg.c b/procsdk_audio_x_xx_xx_xx/test_dsp/sap/audio_dc_cfg.c
index c8985d32cb8cd0e52fe8972bcb45fed54b5b2d50..b911dab8221ad50d3c00ab7bfa93b56963c62d31 100644 (file)
@@ -387,8 +387,11 @@ void set_audio_desc(unsigned char var1,unsigned char var2,unsigned char var3,uns
do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_SAMPLE_RATES(var1, var4));}while (ret_val !=I2C_RET_OK);
platform_delay(10000);
do{ret_val=alpha_i2c_write(HSDIO_EDID_AUDIO_DESC_MISC(var1, var5));}while (ret_val !=I2C_RET_OK);
- //platform_delay(1000);do{ret_val=alpha_i2c_write(HSDIO_ALERT(HSDIO_ALERT_INPUT_AUDIO_CHANGE_msk));}while (ret_val !=I2C_RET_OK);
- //platform_delay(1000);do{ret_val=alpha_i2c_write(HSDIO_ALERT(HSDIO_ALERT_INPUT_AUDIO_MUTE_msk));}while (ret_val !=I2C_RET_OK);
+ platform_delay(1000);
+ do{ret_val=alpha_i2c_write(HSDIO_ALERT(HSDIO_ALERT_INPUT_AUDIO_CHANGE_msk));}while (ret_val !=I2C_RET_OK);
+ platform_delay(1000);
+ do{ret_val=alpha_i2c_write(HSDIO_ALERT(HSDIO_ALERT_INPUT_AUDIO_MUTE_msk));}while (ret_val !=I2C_RET_OK);
+ platform_delay(1000);
}
void hrptredid()
Platform_STATUS status = 0;
hrptredid();
- //read_hdmi_debug();
hdmi128();
return (status);
}
-#if 0 // GJ Debug -- actively working
unsigned int read_hdmi_samprate()
{
unsigned char data[50];
//int ret_val2=0;
int clear_to_read=5;
- clear_to_read==alpha_i2c_write(HSDIO_ALERT_STS); //clear the interrupt on ~HMINT by reading the Alert Status register
+ clear_to_read=alpha_i2c_write(HSDIO_ALERT_STS); //clear the interrupt on ~HMINT by reading the Alert Status register
ret_val=alpha_i2c_write(HSDIO_AUDIO_INPUT_FREQ_STS);
- if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,0,1);
- if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,0,length);
- if(!ret_val) ret_val= data[2]; // indicates sample rate
+
+ if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&length,0,1,1);
+ if(!ret_val) i2cRead(HSR4_I2C_PORT_NUM, HSR4_I2C_ADDR,&data[0],0,1,length);
+ if(!ret_val) ret_val= data[3]; // indicates sample rate
else
ret_val = 0;
return ret_val;
}
-#endif
/* Nothing past this point */
diff --git a/procsdk_audio_x_xx_xx_xx/test_dsp/sap/sap.c b/procsdk_audio_x_xx_xx_xx/test_dsp/sap/sap.c
index 8c240f40c12170bb40713a0343f0e9d0c213952d..2238faaec513b0220686a4c7c63d4637e2a00919 100644 (file)
#endif
int sap_UNDER[SAP_UNDER_LEN]; // used for underrun
int sap_OVER = 0; // used for overrun
-
-// --- DJDBG dump main EDMA param ---
void DJDBG_SAP_EDMA_dumpParams(int tag_place)
{
unsigned int *ptrPARAM_BASE = (unsigned int *)0x02704000;
Log_info5("PARAM0x19b(%d): 0x%x 0x%x 0x%x 0x%x", tag_place, ptrPARAM0x19[4], ptrPARAM0x19[5], ptrPARAM0x19[6], ptrPARAM0x19[7]);
//Log_info1("TCC0: ERR reg %x", *((unsigned int *)0x02760120)); //DJDBG
}
-
// .............................................................................
// notes:
// . add control function to PORT table
Log_info0 ("SAP PAF_SIO_CONTROL_IDLE_WITH_CLOCKS; PAF_SIO_ERROR_IDLE_STAGE1");
pDevExt->errorState = PAF_SIO_ERROR_IDLE_STAGE1;
- //Log_info5("BEFORE EDMA (%d), EMR:%x EMRH:%x ER:%x ERH:%x", device->mode, *((unsigned int *)0x02700300), *((unsigned int *)0x02700304), *((unsigned int *)0x02701000), *((unsigned int *)0x02701004)); //DJDBG
- //DJDBG_SAP_EDMA_dumpParams(8+device->mode);
#if 1
//DJDBG, if below enableTransfer() is commented, input side continuous working.
}
#endif
//TRACE_GEN((&TR_MOD, "SAP_ctrl.%d: (0x%x) errorState = PAF_SIO_ERROR_IDLE_STAGE1 0x%x.", __LINE__, device, PAF_SIO_ERROR_IDLE_STAGE1));
- //Log_info5("AFTER EDMA (%d), EMR:%x EMRH:%x ER:%x ERH:%x", device->mode, *((unsigned int *)0x02700300), *((unsigned int *)0x02700304), *((unsigned int *)0x02701000), *((unsigned int *)0x02701004)); //DJDBG
- //DJDBG_SAP_EDMA_dumpParams(10+device->mode);
break;
// config active xfer for this buffer
result = SAP_EDMA_setupXfer(device, pDevExt->activeEdma, EDMA_HINV, pDevExt->errorEdma, pFrame);
- Log_info3("SAP_start.%d, pDevExt->activeEdma 0x%x (pDevExt->errorEdma = 0x%x)",
- __LINE__, pDevExt->activeEdma, pDevExt->errorEdma);
+ //Log_info3("SAP_start.%d, pDevExt->activeEdma 0x%x (pDevExt->errorEdma = 0x%x)",
+ // __LINE__, pDevExt->activeEdma, pDevExt->errorEdma);
// signal we have started -- this must come before last enable to prevent a race
// condition where the initial EDMA transfer is very small (e.g. due to startClocks)
// and completes before any further instructions in this thread are executed.
// will be serviced and generate an interrupt even before the McASP is enabled.
pDevExt->runState = 1;
pDevExt->shutDown = 0;
- Log_info0 ("SAP_start runState=1 & ENABLE TRANSFERS");
+ //Log_info0 ("SAP_start runState=1 & ENABLE TRANSFERS");
// enable interrupts and event servicing for this channel
EDMA3_DRV_enableTransfer (hEdma0, pDevExt->activeEdma, EDMA3_DRV_TRIG_MODE_EVENT);
if ((device->mode == DEV2_INPUT) && pDevExt->errorState)
{
-
+ Log_info1("SAP_issue: Input Error Trap, with errorState = 0x%x", pDevExt->errorState);
return SIO2_EBADIO;
}
// increment count
pDevExt->numQueued += 1;
- //DJDBG_SAP_EDMA_dumpParams(0+device->mode); //DJDBG
-
result = SAP_EDMA_setupXfer (device, pParam->hEdma, parentEdma, pDevExt->errorEdma, pFrame);
- //GJ Debug
//Log_info4("SAP_issue.%d, EDMA_setupXfer: Target EDMA: 0x%x, Parent Edma: 0x%x Error Edma: 0x%x",
// __LINE__, pParam->hEdma, parentEdma, pDevExt->errorEdma);
} */
if ((pDevExt->errorState == PAF_SIO_ERROR_IDLE_STAGE1) && (device->mode == DEV2_OUTPUT))
- {
pDevExt->errorState = PAF_SIO_ERROR_NONE;
- }
+
pDevExt->shutDown = 0;
// special case enables when not yet started
return result;
}
}
- //DJDBG_SAP_EDMA_dumpParams(2+device->mode); //DJDBG
-
Hwi_restore (key); //DJDBG
return result;
return SIO2_EBADIO;
}
- //Log_info1("SAP_reclaim: Before SEM Pend mode %d", device->mode); // GJ Debug
+ // Log_info0("SAP_reclaim: Before SEM Pend");
// wait for ISR to signal block completion
//TRACE_VERBOSE((&TR_MOD, "SAP_reclaim.%d wait for ISR to signal block completion", __LINE__));
Log_info0("SAP_reclaim, SYS_ETIMEOUT");
return SIO2_ETIMEOUT;
}
- //Log_info1("SAP_reclaim: After SEM Pend for mode: 0x%x", device->mode); // GJ Debug
- //DJDBG_SAP_EDMA_dumpParams(6+device->mode); //DJDBG
+ //Log_info1("SAP_reclaim: After SEM Pend for mode: 0x%x", device->mode);
// return error (owner must idle)
if (pDevExt->errorState == PAF_SIO_ERROR_FATAL)
// Dont clean if was for fill.
// since pend returned we know that head of fromdevice is valid
pFrame = Queue_head (device->fromdevice);
- Log_info2("SAP: Inside SAP_Reclaim with From Device Frame->Addr: 0x%x and Frame->Size: %d", pFrame->addr, pFrame->size); // GJ Debug
+ Log_info2("SAP: Inside SAP_Reclaim with From Device Frame->Addr: 0x%x and Frame->Size: %d", pFrame->addr, pFrame->size);
if ((device->mode == DEV2_INPUT) && (pFrame->addr != NULL))
Cache_inv (pFrame->addr, pFrame->size, Cache_Type_ALL, TRUE);
#endif
DEV2_Device *entry;
EDMA3_DRV_Result edmaResult;
Uint32 reqTcc;
- Int oldMask, result,i;
+ Int oldMask, result,i, Que_num;
Error_Block eb;
//TRACE_GEN((&TR_MOD, "SAP_open.%d (0x%x)", __LINE__, device));
return SIO2_EMODE;
if (device->mode == DEV2_OUTPUT)
+ {
+ Que_num = 1;
Log_info0("In SAP Open for Output");
+ }
+ else
+ Que_num = 0;
// allocate memory for device extension
hEdma0,
&pDevExt->edmaParams[i].hEdma,
&reqTcc,
- (EDMA3_RM_EventQueue) 0,
+ (EDMA3_RM_EventQueue) Que_num,
SAP_isrCallback,
(void *) device);
if (edmaResult != EDMA3_DRV_SOK)
hEdma0,
&pDevExt->errorEdma,
&reqTcc,
- (EDMA3_RM_EventQueue)0,
+ (EDMA3_RM_EventQueue)Que_num,
SAP_isrCallback,
(void *) device);
if (edmaResult != EDMA3_DRV_SOK)
// do nothing if SAP_init not yet called
if (!SAP_initialized)
{
- Log_info2("%s.%d: SAP_init not yet called.\n", (IArg)__FUNCTION__, __LINE__);
+ Log_info2("%s.%d: SAP_init not yet called.\n", __FUNCTION__, __LINE__);
return;
}
// to clean up via SIO_idle()
pDevExt->errorState = PAF_SIO_ERROR_FATAL;
//TRACE_TERSE((&TR_MOD, "SAP_watchDog.%d, PAF_SIO_ERROR_FATAL: 0x%x", __LINE__, pDevExt->errorState));
-
- if(gSapWatchDogThrottle == 0) //DJDBG
+ /* if(gSapWatchDogThrottle == 0) //DJDBG
{
Log_info3("SAP_watchDog.%d (0x%x); THROTTLED result = 0x%x", __LINE__, device, result);
}
gSapWatchDogThrottle ++;
- if(gSapWatchDogThrottle > 10) gSapWatchDogThrottle = 0;
-
+ if(gSapWatchDogThrottle > 10) gSapWatchDogThrottle = 0; */
// if outstanding pend then post to free owner thead
if (!Semaphore_pend(pDevExt->sync, 0))
Semaphore_post (pDevExt->sync);
Log_info2("Before SEM_post for device: 0x%x gIsrOutput: %d", device->mode, gisrOutput);
// signal user thread
Semaphore_post (pDevExt->sync);
+#if 0
if(gIsrCnt > 10) { //DJDBG
Log_info1("SAP isrCallback enough interrupts! %d", gIsrCnt);
+
}
+#endif
}
else
gIsrElseCnt++;
if (!(opt & EDMA3_DRV_OPT_TCINTEN_SET_MASK (1)))
{
- gIsrErrCnt++; // DJDBG
- pDevExt->errorState = PAF_SIO_ERROR_ERRBUF_XFER;
- //Log_info1("SAP isrCallback ERROR mode:%d", device->mode); // GJ Debug
+ gIsrErrCnt++;
+ pDevExt->errorState = PAF_SIO_ERROR_ERRBUF_XFER;
}
} // runState
@@ -1217,7 +1208,8 @@ Int SAP_EDMA_setupParam (DEV2_Handle device, XDAS_UInt32 targetEdma, XDAS_UInt32
MCASP_Handle hPort = sapMcaspDrv.hPort[pDevExt->pParams->sio.moduleNum];
volatile Uint32 *base = (volatile Uint32 *)(hPort->baseAddr);
- //Log_info3("%s.%d: Entered SAP_EDMA_setupParam for Target: 0x%x.\n", (xdc_IArg)__FUNCTION__, __LINE__, targetEdma); // GJ Debug
+ //Log_info3("%s.%d: Entered SAP_EDMA_setupParam for Target: 0x%x.\n", (xdc_IArg)__FUNCTION__, __LINE__, targetEdma);
+
// Init opt parameter to 0 which, without being overriden, configures as:
// A synchronized transfer (no FIFO mode on src or dst)
// no chaining or intermediate interrupts
@@ -1231,15 +1223,18 @@ Int SAP_EDMA_setupParam (DEV2_Handle device, XDAS_UInt32 targetEdma, XDAS_UInt32
edmaConfig.srcCIdx = 0;
edmaConfig.opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK (EDMA3_DRV_SYNC_AB); //DJDBG!
-
if (device->mode == DEV2_OUTPUT) {
//edmaConfig.opt |= EDMA3_DRV_OPT_DAM_SET_MASK (EDMA3_DRV_ADDR_MODE_FIFO); //DJDBG!!!
edmaConfig.opt |= 2;
}
+ else {
+ //edmaConfig.opt |= EDMA3_DRV_OPT_SAM_SET_MASK (EDMA3_DRV_ADDR_MODE_FIFO); //DJDBG!!!
+ //edmaConfig.opt |= 1;
+ }
// if regular transfer then enable interrupt with tcc code
if (targetEdma != pDevExt->errorEdma) {
- //edmaConfig.opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK (EDMA3_DRV_SYNC_AB);
+ edmaConfig.opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK (EDMA3_DRV_SYNC_AB);
edmaConfig.opt |= EDMA3_DRV_OPT_TCINTEN_SET_MASK (1);
edmaConfig.opt |= EDMA3_DRV_OPT_TCC_SET_MASK (pDevExt->firstTCC);
}
@@ -1277,12 +1272,9 @@ Int SAP_EDMA_setupParam (DEV2_Handle device, XDAS_UInt32 targetEdma, XDAS_UInt32
//edmaConfig.srcAddr= (unsigned int)edmaConfig.srcAddr+ 2;
edmaConfig.destBIdx = 0;
edmaConfig.destAddr = (unsigned int) &sap_OVER;
- ////edmaConfig.cCnt = (1024 * sizeof(int))/(edmaConfig.aCnt * edmaConfig.bCnt); //DJDBG
- //Log_info2("SAP_setupParam RX , null transfer size: 0x%x addr: 0x%x", edmaConfig.cCnt, edmaConfig.srcAddr); //DJDBG
}
}
else {
- //Log_info2("SAP dump numSers:%d, addr=0x%x", pDevExt->numSers, addr); //DJDBG
edmaConfig.destBIdx = 0;
edmaConfig.destAddr = (unsigned int) (hPort->xbufAddr);
@@ -1303,9 +1295,9 @@ Int SAP_EDMA_setupParam (DEV2_Handle device, XDAS_UInt32 targetEdma, XDAS_UInt32
}
}
edmaConfig.srcAddr = (unsigned int) getGlobalAddr(edmaConfig.srcAddr);
- edmaConfig.destAddr = (unsigned int) getGlobalAddr(edmaConfig.destAddr);
+ edmaConfig.destAddr = (unsigned int) getGlobalAddr(edmaConfig.destAddr);
- Log_info3("SAP: Inside SAP_EDMA_setupParam with targetEdma = 0x%x linked to childEdma = 0x%x & dest-addr: 0x%x", targetEdma, childEdma, edmaConfig.destAddr); // GJ Debug
+ //Log_info3("SAP: Inside SAP_EDMA_setupParam with targetEdma = 0x%x linked to childEdma = 0x%x & dest-addr: 0x%x", targetEdma, childEdma, edmaConfig.destAddr);
EDMA3_DRV_setPaRAM (hEdma0, targetEdma, &edmaConfig);
@@ -1313,7 +1305,5 @@ Int SAP_EDMA_setupParam (DEV2_Handle device, XDAS_UInt32 targetEdma, XDAS_UInt32
if (childEdma != EDMA_HINV)
EDMA3_DRV_linkChannel (hEdma0, targetEdma, childEdma);
- //DJDBG_SAP_EDMA_dumpParams(4 + device->mode); //DJDBG
-
return SIO2_OK;
} //SAP_setupParam
diff --git a/procsdk_audio_x_xx_xx_xx/test_dsp/sap/sap_d10.c b/procsdk_audio_x_xx_xx_xx/test_dsp/sap/sap_d10.c
index 5dec2bc4077bca72ca986f268bd1d4efce4448ea..41ff6b2f3c90c40d97ad27443350d0440a7476f8 100644 (file)
// Includes
#include <sap_d10.h>
+#include <audio_dc_cfg.h>
//#include <xdc/runtime/System.h>
//#define AUD_OSC_CLOCK
static int manageOutput (DEV2_Handle device, const SAP_D10_Tx_Params *pParams, float rateX);
//static int FireWorks_read1394Status (PAF_SIO_InputStatus *pStatus);
-//void HSR4_readStatus (PAF_SIO_InputStatus *pStatus);
+void HSR4_readStatus (PAF_SIO_InputStatus *pStatus);
//void HDMIGpioInit (void);
-//unsigned int HDMIGpioGetState (void);
+unsigned int HDMIGpioGetState (void);
// -----------------------------------------------------------------------------
// State machine variables and defines
0,0,0 // unused[3]
};
-#if 0
-
-// -----------------------------------------------------------------------------
-// One time initialization of the AC7xx hardware.
-// . Creation of global AK4588 handle
-// . DAC format set to I2S
-// . DAC soft mute rate to 256/fs
-// . DIR format set to I2S and clock generation
-// . configure AMUTE0 as GPIO to control DAC mute circuit
-// . Assert DAC mute circuit
-
-static inline XDAS_Int32 initD10 (DEV_Handle device)
-{
- AK4588_Attrs attrs;
- int regData;
- volatile Uint32 *mcasp0 = (volatile Uint32 *) _MCASP_BASE_PORT0;
- volatile Uint32 *mcasp1 = (volatile Uint32 *) _MCASP_BASE_PORT1;
-
- // create AK4588 instance
- attrs.controlMode = AK4588_MODE_SPI1;
- attrs.segid = device->segid;
- attrs.anaAddr = E17_AK4588_ANA_ADDR;
- attrs.digAddr = E17_AK4588_DIG_ADDR;
- hAK4588 = AK4588_create (&attrs);
- if (!hAK4588)
- return SYS_EALLOC;
-
- // AXR0[10] is SPI CS
- mcasp0[_MCASP_PFUNC_OFFSET] |= _MCASP_PFUNC_AXR10_MASK ;
- mcasp0[_MCASP_PDIR_OFFSET] |= _MCASP_PDIR_AXR10_MASK ;
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
-
- // configure DAC for I2S
- regData = AK4588_ANA_REG0_NORMAL;
-
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
- AK4588_writeAna (hAK4588, 0, regData);
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
-
- // soft mute rate = 256/fs
- regData = 0x31;
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
- AK4588_writeAna (hAK4588, 9, regData);
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
-
- // configure DIR for I2S output and generate bit/frame clocks
- regData = 0x52;
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
- AK4588_writeDig (hAK4588, 1, regData);
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
-
- // oscillator master -- default
- clockMuxTx1 (D10_MCLK_OSC, -1);
-
- // configure AMUTE1 as GPIO for mute control; and assert mute
- mcasp1[_MCASP_PFUNC_OFFSET] |= _MCASP_PFUNC_AMUTE_MASK;
- mcasp1[_MCASP_PDIR_OFFSET] |= _MCASP_PDIR_AMUTE_MASK;
- dacHardMute ();
-
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
- AK4588_readDig (hAK4588, 0, ®Data);
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
-
- regData |= 0x3|0x20;
-
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
- AK4588_writeDig (hAK4588, 0, regData);
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
-
- return 0;
-
-} //initD10
-
-#endif
-
// -----------------------------------------------------------------------------
// The McASP TX1 section is *only* used as a master clock mux.
// Mux functionality is achieved by selecting either an external high
{
// select clkxDiv table
if (sel == D10_MCLK_DIR)
- while(1); // GJ: for now, HDMI is the only valid input option. Stop here if SPDIF selected.
- //pClkxDiv = (unsigned char *) clkxDivDIR;
+ while(1);
+ //pClkxDiv = (unsigned char *) clkxDivDIR;
else if (sel == D10_MCLK_HDMI)
- pClkxDiv = (unsigned char *) clkxDivHDMI;
- //else
+ pClkxDiv = (unsigned char *) clkxDivHDMI;
+ //else
//while(1);
- // pClkxDiv = (unsigned char *) clkxDivADC;
+ // pClkxDiv = (unsigned char *) clkxDivADC;
return 0;
} //clockMuxTx1
@@ -826,9 +752,9 @@ static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PA
// since DIR set MCLK per fs
// regData = 0x3 | (dirOCKS[pStatusIn->sampleRateMeasured] << 2)|0x20;
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
+ //mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
//AK4588_writeDig (hAK4588, 0, regData);
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
+ //mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
}
else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_OSC) &
(((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_STD)) {
@@ -843,9 +769,9 @@ static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PA
// since DIR set MCLK per fs
// regData = 0x3 | (dirOCKS[pStatusIn->sampleRateMeasured] << 2)|0x30;
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
+ //mcasp0[_MCASP_PDOUT_OFFSET] = 0x000 ;
//AK4588_writeDig (hAK4588, 0, regData);
- mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
+ //mcasp0[_MCASP_PDOUT_OFFSET] = 0x400 ;
}
else if ((((pParams->d10rx.mode & D10_MCLK_MASK) >> D10_MCLK_SHIFT) == D10_MCLK_HDMI) &
(((pParams->d10rx.mode & D10_MODE_MASK) >> D10_MODE_SHIFT) == D10_MODE_HDMI)) {
@@ -853,7 +779,7 @@ static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PA
pStatusIn->nonaudio = PAF_IEC_AUDIOMODE_AUDIO;
pStatusIn->emphasis = PAF_IEC_PREEMPHASIS_NO;
-#if 0 // GJ Debug -- actively working
+
if(!HDMIGpioGetState()) {
HSR4_readStatus (pStatusIn);
pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
@@ -863,8 +789,8 @@ static int manageInput (DEV2_Handle device, const SAP_D10_Rx_Params *pParams, PA
pStatusIn->sampleRateMeasured = PrevSampRate;
pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
}
-#else
+#if 0
pStatusIn->sampleRateMeasured = PAF_SAMPLERATE_192000HZ;
pStatusIn->sampleRateData = pStatusIn->sampleRateMeasured;
#endif
@@ -1132,7 +1058,7 @@ XDAS_Int32 D10_sapControl (DEV2_Handle device, const PAF_SIO_Params *pParams, XD
// -----------------------------------------------------------------------------
-#if 0
+
extern unsigned int read_hdmi_samprate();
int RateHdmi=0;
void HSR4_readStatus (PAF_SIO_InputStatus *pStatus)
pStatus->sampleRateMeasured = RateTable_hdmi[RateHdmi];
}
-#define GP_MOD_NUM 0
-#define GP_PIN_NUM 13
-#define ACTIVE_LOW 1
-
-void HDMIGpioInit (void) {
- //gpioInitRead (GP_MOD_NUM, GP_PIN_NUM);
-}
-
unsigned int HDMIGpioGetState (void) {
- return(0);
+ return(gpioReadInput(GPIO_PORT_0, PLATFORM_AUDIO_HSR_HMINTz_GPIO));
}
-#endif
+
// -----------------------------------------------------------------------------
void *SAP_D10_getConfig(int mode)
diff --git a/procsdk_audio_x_xx_xx_xx/test_dsp/sap/sap_mcasp.c b/procsdk_audio_x_xx_xx_xx/test_dsp/sap/sap_mcasp.c
index 74641c23ce30c27b208bafd35bff85355cbd912b..8b91983635f3fb548c2bf6091f75ee84801d8fdf 100644 (file)
if (device->mode == DEV2_INPUT)
{
- //TRACE_TERSE1(( "SAP_MCASP_reset(0x%x) input device.", device));
- // disable FIFO if present
+ //TRACE_TERSE1(( "SAP_MCASP_reset(0x%x) input device.", device));
+ // disable FIFO if present
Log_info1("SAP_MCASP_reset(0x%x) input device.", device); //DJDBG
if (sapMcaspDrv.fifoPresent[mcaspNum])
fifoBase[_MCASP_RFIFOCTL_OFFSET] &=
}
else
{
- //TRACE_TERSE1(("SAP_MCASP_reset(0x%x) output device.", device));
+ //TRACE_TERSE1(("SAP_MCASP_reset(0x%x) output device.", device));
Log_info1("SAP_MCASP_reset(0x%x) output device.", device); //DJDBG
// disable FIFO if present
if (sapMcaspDrv.fifoPresent[mcaspNum])