Merge remote-tracking branch 'origin/dev_pasdk_frank_pasdk577RunTimeAudioIoCfg' into...
authorJianzhong Xu <a0869574@ti.com>
Mon, 18 Jun 2018 16:33:24 +0000 (12:33 -0400)
committerJianzhong Xu <a0869574@ti.com>
Mon, 18 Jun 2018 16:33:24 +0000 (12:33 -0400)
pasdk/test_dsp/application/itopo/evmk2g/atboot.c
pasdk/test_dsp/application/itopo/evmk2g/mcasp_cfg.c
pasdk/test_dsp/framework/audioStreamInpProcNewIO.c
pasdk/test_dsp/framework/audioStreamOutIo.c
pasdk/test_dsp/framework/audioStreamOutProc.h

index 270de83b30dad748578cdd5c89a2e22028d5fd08..bd43f338b8ef607289417df2201f9705e8ed67aa 100644 (file)
@@ -85,7 +85,7 @@ All rights reserved.
     writeVOLOffsetMasterN(0x7fff), \
     writeSYSRecreationModeDirect, \
     writeSYSChannelConfigurationRequestSurround4_1, \
-    execPAIInHDMI, \
+    execPAIInDigital, \
     execPAIOutAnalog
 #else
 // Performing PCM high-sampling rate + SRC + CAR benchmarking
index bf4886aa02e1102621d8d1437e25fd9023d8e79f..74a2fdcbd784d6f3732e888d44e357866c697d3a 100644 (file)
@@ -148,8 +148,8 @@ Mcasp_HwSetupData mcaspXmtSetupDAC = {
         /* .xstat    = */ 0x000001FF, /* reset any existing status bits       */
         /* .xevtctl  = */ 0x00000000, /* DMA request is enabled or disabled   */
         {
-//             /* .aclkxctl  = */ 0X000000E1,  // Transmit bit clock divide ratio = 2 --> works for 48khz PCM but not for DDP
-             /* .aclkxctl  = */ 0X000000E7,  // Transmit bit clock divide ratio = 8 --> working for Dolby/DTS 48khz but not for PCM
+             /* .aclkxctl  = */ 0X000000E1,  // Transmit bit clock divide ratio = 2 --> works for 48khz PCM but not for DDP
+//             /* .aclkxctl  = */ 0X000000E7,  // Transmit bit clock divide ratio = 8 --> working for Dolby/DTS 48khz but not for PCM
 //             /* .aclkxctl  = */ 0X000000E3,  // Transmit bit clock divide ratio = 4 --> Dolby/DTS 96khz
 //             /* .aclkxctl  = */ 0X000000E1,  // Transmit bit clock divide ratio = 2 --> Dolby/DTS 192khz
              /* .ahclkxctl = */ 0x00004000,
index d332c088c7547a412c26954677ed15ac889039f0..7aec882afcf7ddb68b12db930d0c509e88dc515c 100644 (file)
@@ -1142,6 +1142,7 @@ void asitPhyTransferStart(PAF_AST_IoInp *pInpIo)
 
 // Indicates whether Input has been selected
 Int d10Initialized = 0;
+
 //extern Aud_STATUS mcaspAudioConfig(void);
 //extern void McaspDevice_init(void);
 
index a5796b35b7d94857aedd89b95c0f1066510273bd..c132db7f4c7cb489e8de5c3d0c8cbadc9e9a4a91 100644 (file)
@@ -139,6 +139,7 @@ Int asopSelectDevices(
             // configure stride according to selected McASP LLD configuration
             pOut->stride = pReqLldCfg->mcaspChanParams->noOfSerRequested * 
                 pReqLldCfg->mcaspChanParams->noOfChannels;
+                
             // initialize rateX
             pOut->rateX = 1.; // rateX==1.0 for CLKXDIV==1
         }
@@ -245,7 +246,7 @@ Int asopSetCheckRateX(
     Int zMS;
     Int zE, zX;
     // "proof of concept" for McASP LLD API
-    Uint32 divider;
+    Uint32 divider, clkXDiv;
     Mcasp_HwSetupData mcaspSetup;
     Int32 status;
 
@@ -322,26 +323,32 @@ Int asopSetCheckRateX(
             //
             if (pOut->rateX != rateX)
             {
-                //UInt32 regVal;
-                
                 // Initialize divider value.
                 // This works for AHCLKX input from HDMI & sample rate = 44.1,48,88.2,96,192 kHz.
                 divider = 2;
                 
                 // Update divider based on calculated rateX
                 divider /= rateX;
-
+                
 #if 0 // debug
-                // Experimental code: directly write CLKXDIV
-                regVal = *(volatile UInt32 *)0x23400B0; // read MCASP_ACLKXCTL
-                regVal &= ~0x1F; // mask off CLKXDIV bits
-                //regVal |= 7; // set CLKXDIV for 48 kHz
-                //regVal |= 3; // set CLKXDIV for 96 kHz
-                //regVal |= 1; // set CLKXDIV for 192 kHz
-                regVal |= (divider-1); // set CLKXDIV
-                *(volatile UInt32 *)0x23400B0 = regVal; // write MCASP_ACLKXCTL
-#endif                
+                {
+                    UInt32 regVal;
+
+                    // Experimental code: directly write CLKXDIV -- produces correct output                
+                    regVal = *(volatile UInt32 *)0x23400B0; // read MCASP_ACLKXCTL
+                    regVal &= ~0x1F; // mask off CLKXDIV bits
+                    //regVal |= 7; // set CLKXDIV for 48 kHz
+                    //regVal |= 3; // set CLKXDIV for 96 kHz
+                    //regVal |= 1; // set CLKXDIV for 192 kHz
+                    regVal |= (divider-1); // set CLKXDIV
+                    *(volatile UInt32 *)0x23400B0 = regVal; // write MCASP_ACLKXCTL                    
+                }
+#endif                  
+
+                // Calculate CLKXDIV bit field value
+                clkXDiv = (divider-1) & CSL_MCASP_ACLKXCTL_CLKXDIV_MASK;
 
+#if 0 // use existing McASP LLD API functions -- results in Tx serializer channel swap
                 // get existing McASP HW setup
                 status = mcaspControlChan(pOut->hMcaspChan, Mcasp_IOCTL_CNTRL_GET_FORMAT_CHAN, &mcaspSetup);
                 if (status != MCASP_COMPLETED)
@@ -352,7 +359,7 @@ Int asopSetCheckRateX(
                 
                 // update CLKXDIV based on rateX
                 mcaspSetup.clk.clkSetupClk &= ~CSL_MCASP_ACLKXCTL_CLKXDIV_MASK;
-                mcaspSetup.clk.clkSetupClk |= (divider-1);
+                mcaspSetup.clk.clkSetupClk |= clkXDiv;
                 
                 // update McASP HW setup
                 status = mcaspControlChan(pOut->hMcaspChan, Mcasp_IOCTL_CNTRL_SET_FORMAT_CHAN, &mcaspSetup);
@@ -361,6 +368,17 @@ Int asopSetCheckRateX(
                     Log_info0("asopSetCheckRateX(): McASP set channel format failed!\n");
                     return ASOP_IO_ERR_MCASP_CFG;
                 }
+#endif
+
+#if 1 // use new McASP LLD API function -- produces correct output
+                // update CLKXDIV setup
+                status = mcaspControlChan(pOut->hMcaspChan, Mcasp_IOCTL_CNTRL_SET_FORMAT_CHAN_CLKXDIV, &clkXDiv);
+                if (status != MCASP_COMPLETED)
+                {
+                    Log_info0("asopSetCheckRateX(): McASP set channel format CLKXDIV failed!\n");
+                    return ASOP_IO_ERR_MCASP_CFG;
+                }
+#endif
                 
                 pOut->rateX = rateX; // update saved rateX
                 
index 53a29c3329e2996772f8511616c88052f83f8bb8..96e0433b16837da3830973d51bd6a7cc9cef321b 100644 (file)
@@ -208,7 +208,7 @@ typedef struct PAF_AST_OutIO {
     uint32_t ioBuffBuf2AllocCnt;        // Output buffer2 allocation (split buffer on buffer wrap) count
     uint32_t errIoBuffOvrCnt;           // Output IO overflow count
     uint32_t errIoBuffUndCnt;           // Output IO underflow count
-    float rateX;                        // Input/Output clock ratio
+    float    rateX;                     // Input/Output clock ratio
     
     // debugging counters
     uint32_t num_xfers;